ST AN2164 Application note

AN2164

Application note

Interfacing the ST10 with external memory

Introduction

The ST10 microcontrollers offer an addressable space of 16 Mbytes. The on-chip
peripherals, the on-chip RAM and Flash memory cover only a small fraction of this
addressable space leaving the remaining space to be used to interface external peripherals
and memories with the ST10.

This application note is divided into two parts. The first acts as a brief overview of features of
the ST10 external bus such as the EBC operating modes, port pins timing and maximum
addressable space.

The second part of the document describes how to connect external memory to the ST10.
In the sections contained in this part, the use of both demultiplexed and multiplexed buses is
considered, giving examples of word-wide and byte-wide memory.

This application note does not replace the ST10 user manuals or data sheets.

May 2007 Rev 1 1/14

www.st.com

Contents AN2164

Contents

1 EBC overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.1 EBC operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.2 EBC Port pins control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.3 EA pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.4 EBC timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.5 EBC maximum addressable space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 How to connect an external memory to the ST10 with a demultiplexed

bus 7

2.1 16-bit demultiplexed bus and word-wide memory example . . . . . . . . . . . . 7

2.2 16-bit demultiplexed bus and byte-wide memories example . . . . . . . . . . . 8

3 How to connect an external memory to the ST10 with a multiplexed bus

11

3.1 16-bit multiplexed bus and word-wide memory example . . . . . . . . . . . . . 11

3.2 16-bit multiplexed and byte-wide memories example . . . . . . . . . . . . . . . . 12

4 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

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AN2164 EBC overview

1 EBC overview

The ST10 External Bus Controller provides the user with a number of options:

● to enable the ST10 to be run entirely from external memory (code and/or data storage)

● to use combinations of on chip and external memories up to the 16 MBytes limit

● to access some internal resources (X-peripherals, XFlash, XRAM)

1.1 EBC operating modes

The ST10F27x offers the following operational modes:

● 16-/18-/20-/24- bit addresses and 16-bit data demultiplexed

● 16-/18-/20-/24- bit addresses and 16-bit data multiplexed

● 16-/18-/20-/24- bit addresses and 8-bit data demultiplexed

● 16-/18-/20-/24- bit addresses and 8-bit data multiplexed

The ST10 provides up to 5 CSx signals which can be programmed to operate in different
modes. Each CSx mode and characteristics are selected independently allowing the
possibility to interface the ST10 with different external resources.

CS0 operating mode is selected by hardware according to the fields BYTP0 and BYTP1
(P0L.6 and P0L.7).

CS1...CS4 operating modes are selected by software via the field BYTP in the
corresponding BUSCONx register.

For a detailed description of these modes, the ST10 EBC-related registers and their
configurations, refer to the ST10 user manuals.

1.2 EBC Port pins control

The ST10 external memory interface is implemented through 4 ports: P0, P1,P4 and P6 in
addition to some dedicated pins.

Table 1.

I/O Name Pin Number Function

P0L
AD0 .. AD7

P0H
AD8.. AD15

P1L
A0 .. A7

P1H
A8 .. A15

P4 85.. 92 O Address A16 .. A23 if needed

P6.0 .. P6.4 1 .. 5 Output Chip Select Enable CS0 .. CS4

ST10F27x EBC I/O port lines.

100 .. 107

108, 111.. 117

118 ..125 O address in 8-/16- bit demultiplexed bus

128 .. 135 O address in 8-/16- bit demultiplexed bus

I/O Data in 8-/16- bit demultiplexed bus
O address & I/O Data 8-/16- bit in multiplexed bus

I/O Data in 16-bit demultiplexed bus
O address in 8-bit multiplexed bus
O address and I/O data in 16-bit demultiplexed bus

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EBC overview AN2164

I/O Name Pin Number Function

EA 99 External Memory Access Enable pin

ALE 98 Address Latch Enable Output

READY 97 Ready input level

WR/WRL 96 External Write Enable/ External Write low byte Enable

RD 95 External Read Enable

HOLD 6 External Master Hold Request Input

HLDA 7 Hold Acknowledge Output

BREQ 8 Bus Request Output

1.3 EA pin

When the ST10 bootstrap mode is switched off, ST10 devices with embedded Flash give the
user the possibility to boot either from the internal Flash or from external memory. The boot
memory is selected according to the EA pin level during reset.

In order to start fetching code from the internal Flash, EA
reset. Otherwise, the ST10 starts executing the program code stored in the external
memory.

When booting from internal Flash, an access can be performed to an external resource if
required. This resource can be interfaced to the ST10 using any of the CSx chip selects and
the related configuration registers should be set according to its characteristics.

1.4 EBC timing

An external bus memory cycle specifies the time required to perform a read or write access
to an external resource.

It depends on the ST10 speed, the bus configuration (address and data on the same or
different busses) and the external resource characteristics.

The ST10 EBC allows the user to adapt the controller's external bus cycles to the external
memory characteristics. For example, the access time can be enlarged to allow access to
very slow memories.

The user can act on the following parameters to adapt the EBC cycle timing to the external
memory.

● Wait states: up to 15 wait states can be inserted to extend the memory access time. As

an example, a 40 MHz ST10 operating frequency gives a 25ns CPU cycle. If it is
necessary to access memory with an access time of 90ns = 25ns + 65ns, at least 3
wait states need to be inserted in the EBC cycle (25ns * 3 = 75ns).

● Ready functionality: If 15 wait states are not sufficient or in the case the external

memory access time is not constant, then the READY signal can be used to monitor
the end of the EBC cycle. In the example above, if the access time is greater than 25ns
+ 15x25ns = 400ns, then the READY signal can be used to force the ST10 to wait until
the data is available.

should have a high level during

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AN2164 EBC overview

● Tristate wait state: In the case the external memory needs time to switch off its bus, a

CPU cycle (tri-state) can be inserted after the RD command deactivation.

● ALE length signal can be lengthened by a half CPU cycle giving more time to latch the

address on the external bus.

The following parameters adapt the ST10 to the external memory without extending the
EBC cycle time

● Read/Write Delay: The Read/Write CS can be delayed by a half CPU cycle after the

falling edge of the ALE signal. This does not extend the EBC cycle.

● CS signal control: The user has the possibility to change the CS signal half CPU cycle

after the ALE rising edge or at with the ALE rising edge.

1.5 EBC maximum addressable space

The CSSELx (PH0.1 and P0H.2) field sampled at the end of a hardware reset controls the
active number of CSx signals.

The SALSELx (P0H.3 and P0H.4) field sampled at the end of a hardware reset selects the
number of address lines addressing an external location. It determines the size of the
maximum addressable space per chip select CSx. The following table gives the different
configurations.

Table 2.

P0H.3/P0H.4 Maximum EBC addressable space per CS Address lines used

ST10 EBC addressable space

01 64 Kbytes A0 .. A15 ( P1)

11 256 KBytes A0 .. A17 ( P1 , P4.0 & P4.1)

00 1 MByte A0 .. A19 ( P1, P4.0 .. P4.3)

10 16 MBytes A0 .. A23( P1 & P4)

Each CS1 … CS4 has its related ADDRSELx register to map the external memory within
the ST10 memory space. This register configures the size of the window allocated to the
external memory and its start address.

Note: The size specified in this register should not exceed the one specified by the SALSELx field.

For more details, please refer to the ST10 user manual.

CS0 can write to/read from any memory location outside the windows allocated to the
remaining CSx signals with respect to the maximum addressable space.

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