ST AN2156 Application note

AN2156

APPLICATION NOTE

STR73x Family

STR73x Hardware Getting Started

Introduction

The aim of this application note is to give users of the STR73x family devices a number of recommendations on the HW circuitry connected to the main special pins. It covers the pins for power supply (digital and analog), reset, crystal oscillator, the decoupling of the internal voltage regulator, boot modes, test pin, RC oscillator biasing pin and the JTAG debug port.

Detailed reference design schematics of the STR730-EVAL board are also contained in this document with descriptions of the main components, interfaces and modes.

Rev 1

September 2005 1/24

- AN2156

Contents

1 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.1 Power supply pins VDD/VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.2 Analog supply and reference VDDA/VSSA . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.3 Decoupling of the internal voltage regulator V18 . . . . . . . . . . . . . . . . . . . . . . 5

2 Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1 Crystal oscillator pins XTAL1, XTAL2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.2 On-chip RC oscillator and VBias pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3 Reset management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.1 Reset pin nReset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

4 Boot management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4.1 SystemMemory / User Boot mode pins M0, M1 . . . . . . . . . . . . . . . . . . . . . . . 9

4.2 Test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

5 Debug management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5.1 JTAG debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

6 Reference design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6.1 Main . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6.2 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6.3 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6.4 Boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6.5 Wake-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6.6 Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6.7 CAN interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6.8 RS232 serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6.9 Serial ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6.10 JTAG interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

7 Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

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AN2156 -

8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

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1 - Power management AN2156

1 Power management

1.1 Power supply pins VDD/VSS

All current STR73x devices are supplied with a nominal voltage of 5V. The power supply pins are organized in VDD/VSS pairs around the chip and exceptionally all pins need to be properly connected to the power supplies, VDD to 5V, VSS to GND. These connections including pads, tracks and vias should have an impedance as low as possible. This is typically achieved with thick track widths and preferably dedicated power supply planes in multi layer PCBs.

In addition, each VDD/VSS pair should be decoupled with ceramic capacitors which need to be placed as close as possible to the appropriate pins or below the pins on the contrary side of the PCB. Typical values are 10nF to 100nF, but exact values depend on the application needs. The following figure shows the typical layout on such a VDD/VSS pair.

Figure 1. Typical layout for VDD/VSS pair

Via to VSSVia to VDD

Cap.

DDVSS

STR73x

1.2 Analog supply and reference V

The V

As for the supply pins, V X7R ceramic capacitor of 47nF to 100nF can be used for this.

When full accuracy is needed, and depending on the noise rejection of the voltage regulator used to supply the STR73x device, a low pass filter may be considered. As the pin is also used as the ADC supply, the use of a serial resistor must be avoided to reduce the risk of offset error generation. An EMI component from Murata is proposed instead.

pin is used to supply the ADC and to provide it with the analog reference.

DDA

DDA/VSSA

decoupling with short connections is recommended and an

DDA/VSSA

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AN2156 1 - Power management

Figure 2. V

DDA/VSSA

decoupling with an X7R ceramic capacitor

DDA

+5V

SSA

C1 = 47 to 100nF X7R ceramic capacitor U1 = Murata NFM18PC105R0J3 – 1uF

1.3 Decoupling of the internal voltage regulator V18

All existing STR73x derivates are supplied with a single external voltage of 5V. The additional voltages needed are generated by internal charge pump circuits for the flash programming/ erasing and an internal linear voltage regulator which provides the 1.8V for the internal logic. The output of the internal voltage regulator is connected to one or two pins V18, where an external capacitance needs to be connected for decoupling/stabilization between the V18 pin and VSS/GND. There are two important notes:

1. V18 is probably the most critical pin regarding EMC emissions. Therefore the external capacitor(s) must be placed as close as possible (few mm) to the V18/VSS pair(s) or below on the other side of the PCB. If this is done, a very good EMC performance can be achieved.

2. Depending on the device, different capacitances are needed. The values mainly depend on the type of the internal voltage regulator used. Please refer to the tables below which cover the devices available or planned at the time of writing. In case of future devices which are not covered by this application note please refer to the datasheet or contact your support engineer.

The figure below shows the two affected pins (V18 and VBias) of the TQFP144 package as well as the TQFP100 package. In order to support all devices with a single PCB design, it is necessary to provide on both pins footprints for 10µF tantalum and 47-100nF ceramic capacitors. The footprint for the ceramic capacitor on pin 64 should be reusable to be soldered with a resistor instead for the biasing functionality. This may be achieved with 0805 or 0603 SMD footprints. Please refer to the tables below for the different component values and assembly options depending upon the device derivate.

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1 - Power management AN2156

Figure 3. Pin availability for V18 functionality

Pin 126 : V

TQFP144 Packages

Pin 64 : V

Bias

Table 1. Component values for TQFP144 package

Package Derivate

TQFP144/

LFBGA144

STR730 STR735

CMU /

RC osc.

yes VBias resistor (*) 1.3MΩ V18 ceramic cap 100nF

Function Component Value Function Component value

Pin 64 Pin 126

(*) only necessary for 32kHz mode of RC oscillator

Pin 88 : V

TQFP100 Packages

Pin 46 : V

Bias

Table 2. Component values for TQFP100 package

Package Derivate

TQFP100

STR731 STR736

CMU / RC

osc.

yes VBias resistor (*) 1.3MΩ V18 ceramic cap 100nF

Function Component Value Function Component value

Pin 46 Pin 88

(*) only necessary for 32kHz mode of RC oscillator

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AN2156 2 - Clock management

2 Clock management

2.1 Crystal oscillator pins XTAL1, XTAL2

All current STR73x devices have an on-chip oscillator that allows the driving of external crystals or resonators with a fundamental frequency of 4-8 MHz. The recommended circuitry for a crystal is shown below. C1, C2 and R1 values depend greatly on the crystal type and manufacturer. It is suggested that you ask your crystal supplier for the best values for these components.

Figure 4. Recommended circuitry for crystal oscillator pins XTAL1 and XTAL2

XTAL1

Resistor R1 is recommended for feedback stability and has a value of around 1M oscillator of STR73x devices has automatic gain control, there is no need to add a resistance in series.

The values of the load capacitors C1 and C2 are also heavily dependent on the crystal type and frequency. For best oscillation stability they normally have the same value. Typical values are in the range from below 10pF up to 30pF. The parasitic capacitance of the board layout also needs to be considered and typically adds a few pF to the component values.

In the PCB layout all connections should be as short as possible. Any additional signals, especially those that could interfere with the oscillator, should be locally separated from the PCB area around the oscillation circuit using suitable shielding.

XTAL2

C2C1

Ω. As the

2.2 On-chip RC oscillator and VBias pin

All devices of the STR73x family have an on-chip RC oscillator in addition to the main oscillator. This on-chip RC oscillator is capable of running at either 2MHz or 32kHz.

● The default 2MHz mode requires no external components.

● The 32 kHz mode requires an external bias resistor of 1.3 MΩ from the VBias pin towards

GND.

Note: The oscillator frequencies can be adjusted through software after reset, where the reset

frequencies are around 2.34Mhz / 29Khz.

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3 - Reset management AN2156

3 Reset management

3.1 Reset pin nReset

All current STR73x devices are specified for a nominal voltage of 5V with a tolerance of ±10%, thus between 4.5V and 5.5V. The external reset circuitry should apply a reset whenever the supply voltage is outside this voltage supply range and only release it when inside the supply range.

Being within the supply range of 5V ±10%, the absolute minimum duration of the hardware reset pulse is 100µs, but it is recommended that the reset circuitry adds increased time margin, e.g. 200µs.

Note: During power-on, a reset must be provided externally.

At power-on, the nRSTIN pin must be held low by an external reset circuit until V

is reached.

Figure 5 gives an example of the hardware implementation of the RESET circuit for STR73x

devices.

The STM1001 low-power CMOS microprocessor supervisory circuit is used to assert a reset signal whenever the V

voltage falls below a preset threshold or whenever a manual reset is

asserted.

Figure 5. Hardware reset implementation

+5V +5V

2K2*

+5V

VCC

GND

nRSTIN

Reset_PB

* these values are given only as typical examples

1nF*

not Reset

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