ST AN2132 APPLICATION NOTE

AN2132
Obsolete Product(s) - Obsolete Product(s)
Application note
STLC3075 very low single supply SLIC
for WLL application in flyback configuration
Introduction
The STLC3075 is a SLIC device specially designed for WLL (Wireless Local Loop) and ISDN terminal adapters.
19-Feb-2007 Rev 3 1/26
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Content AN2132
Content
1 Wireless local loop system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1 TQFP 10 mm x 10 mm x 1.4 mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1 VBAT voltage generat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.2 Operati on in off-hook condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.3 VPOS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.4 Start-up and DC-DC converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.5 Suggested transformers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.6 Input curr ent limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.7 VPOS current capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.7.1 With USA REN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.7.2 With European REN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.8 RSENSE setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.9 Trapezoidal ringing signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.10 Ringer load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.10.1 With European REN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.10.2 With USA REN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.11 Efficiency and powe r dissipation in flyback configuration . . . . . . . . . . . . . 14
3.12 Micro interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.13 Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.14 Ring trip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.15 PCB precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.16 Ground configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.17 Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.18 On-hook transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.19 Phone detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
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3.20 ESD immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.21 Setting resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.22 Longitudinal balance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
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AN2132 Content
3.23 TTX filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.24 Gain settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.25 Complex impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4 Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Appendix A STLC3075 in application with VPOS > 12 V. . . . . . . . . . . . . . . . . . . 24
Appendix B STLC3075 for USB suspended current specification. . . . . . . . . . . 25
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Obsolete Product(s) - Obsolete Product(s)
Wireless local loop system AN2132
WLL
SLIC
WLL SLIC
WLL SLIC

1 Wireless local loop system

Figure 1. Wireless central office to premises diagram
WLL SLIC
WLL SLIC
WLL
SLIC
Central
office
Local loop
SLIC
Base station
transceiver
Final connection
by radio link
=
wireless
local loop
The main characteristics of this device consist in the possibility to:
operate with a single supply voltage in Fly-Back or Buck-Boost config urati on (see
AN2118 for information on Buck-Boost configuration)
operate in Fly-Back configuration with a single supply voltage VPOS in a range from
+4.5 V to +12 V
generate negative battery voltage
generate a ring signal (trapezoidal wave form)
PC00335
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Obsolete Product(s) - Obsolete Product(s)
AN2132 Packaging

2 Packaging

STLC3075 is housed in standard TQFP package plastic with copper lead frame. No copper slugs protrude from the plastic body. STLC3075 uses the “standard” package option.
The thermal resistances, shown in junction and the ambient still air, and are calculated or measured in ° C/W.
Table 1. Thermal resistance versus package size
Symbol Parameter Value Unit
Rth j-amb
Rth j-amb
Thermal resistance junction ambie nt (Full plastic TQFP on single layer board)
Thermal resistance junction ambie nt (Full plastic TQFP on four layer board)
Table 1
and

2.1 TQFP 10 mm x 10 mm x 1.4 mm

Theta (j-a) on boards, in still air
Figure 2. Thermal resistance versus board structure
Figure 2
, are considered between the
70 ° C/W
45 ° C/W
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Application information AN2132

3 Application information

Figure 3. Typical application schematic
RD
CVPOS
VPOS
VPOS
GATE
RSENSE
VBAT
CLK
TIP
RING CSVR CREV
RTH RLIM IREF
T1
Q1
RF1
RF2
CSVR
RTH
N-ch
R
SENSE
D1
CV
RSF
CSF
CVB
VF CZ
RP
RP
RREF
CZ
CLK
TIP
RING
CREV
RLIM
CONTROL
INTERFACE
TTX CLOCK
DET
D0 D1 D2 PD
CCOMP
CFL
VDD
CH
RDD
RLV
RLV
RS
ZAC
TX
RX
RRX
AGND
RX
TX
RS ZAC ZAC1
ZA
ZB
ZB
GAIN SET
DET D0 D1 D2 PD CKTTX
CTTX1
CS
CTTX2 FTTX
RTTX
BGND
CAC
CVCC
CVCC
STLC3075
ILTF
SYSTEM GND
SUGGESTED GROUND LAY-OUT
AGND
BGND
PGND
RTTX
CTTX
CAC
RD
CRD
D04TL625A

3.1 VBAT voltage generation

When operated with a positive supply voltage VPOS and a correctly set clock signal (typically 125 kHz), the SLIC generates a VBAT voltage for the active and ring operations.
The VBAT voltage lev el, with a 10% spread, is defined by the voltage divider RF1 / RF2 and can be set by choosing an RF1 value from a recommended set of values (see
Table 2. VBAT voltage values (VPOS = 4.5V)
RF1 (KΩ) VBAT (Active mode) VBAT (Ring mode)
270 -46.1V -64.4V 285 -48.4V -67,8V 300 -51.9V -71.7V 315 -54.3V -75.2V
Table 2
):
330 -56.3V -78.2V
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Obsolete Product(s) - Obsolete Product(s)
AN2132 Application information
These values are referred to the device in active mode, on-hook condition (IL = 0mA) and in ring mode without load.
The VBAT value must be chosen taking into account the absolute maximum ratings of the device (VBTOT = 90 V). VBTOT = (VBAT + VPOS) = 90 V must not be exceeded.
When ring mode is selected through the control interface, the VBAT voltage is increased by an internal circuit from it’s active level to a predetermined value for ring mode. These two voltage levels (VBAT active and VBAT ring) are hence correlated. When one is set, (ring or active), the other is also set at the same time.

3.2 Operation in off-hook condition

A major feature of this device is that when changing from on-hook to off-hook conditions (IL >0 mA), the VBAT voltage is automatically adjusted depending on the loop resistance and on the programmed current limitation value (ILIM).
It should be noted that the device is optimized to operate on short loop applications (RLOOP ≤ 500 Ω) in order to obtain the co rrec t ri ng-trip detection.
In these conditions, with line current reaching the programmed constant current feed value (ILIM), the STLC3075 works like a current generator with a fixed DC current.
A fixed voltage drop, 4 V on TIP/GND and approximately 6 V on RING/VBAT, assures the DC functionality and the proper swing for the AC signal.
When the line is set off-hook, the STLC3075 automatically adjusts the generated battery voltage (VBAT) to feed the line with a fixed DC current (programmable via RLIM), and so optimizes power dissipation.
Considering maximum and minimum values for RLOOP ranging from 500 to100 Ω, and with fixed parameters ILIM = 25 mA and 2Rp = 100 Ω, the battery voltage (VBA T) will be equal to:
1. VBAT = 25 mA x (500+100) + 10 V = - 25 V
2. VBAT = 25 mA x (100+100) + 10 V = - 15 V A correctly set current threshold (typically 9 mA), programmable by external resistor RTH,
allows the correct on/off hook transition function. During the off-hook dynamic transition, the CAC capacitor is charged. The line current
regulator system senses the current flowing into RD and reduces the ILOOP current to the programmed ILIM value, set by RLIM.
The settling time of the ILIM current is about 150 ms, and it is a function of the CAC splitter capacitor (min . value allowed is 22µF).

3.3 VPOS characteristics

The input voltage VPOS can change slowly within the data sheet range (4.5 V - 12 V) without any effect on the VBAT voltage.
The STLC3075 can continue to operate correctly even if the VPOS voltage occasionally goes below 4.5 V (instantaneous value, not steady-state). The only limitation is the minimum voltage required on the external PMOS to keep it in a linear area.
Fast transients, ripples and spikes on the supply voltage V a reduced amplitude, depending upon the voltage supply rejection of the device.
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will appear on TIP/RING with
POS
Obsolete Product(s) - Obsolete Product(s)
Application information AN2132
Bench measurements on SVRR give -35 dB @ f = 50 Hz and -47 dB @ f = 4 kHz, using the test circuit configuration with the device in active mode, loaded with an RLOOP = 500 Ω, and ILIM = 25 mA.

3.4 Start-up and DC-DC converter

In order to prevent problems during start-up, an internal circuit turns-on the gate of the MOSFET only when VPOS reaches 4 V and turns it off for VPOS lower than 3 V.
For VPOS voltage higher than 4 V the DC/DC converter power-on is controlled by a soft start circuit embedded on the devices.
Figure 4. DC-DC converter circuit
VPOS
Low/high
duty cycle
comparator
125 kHz
clock
Maximum
duty cycle
comparator
(see figure VPOS current
capability circuit)
PWM
comparator
Logic
Ramp
gen.
VREF
Current
limiter
Switch
driver
CSF
RSF
CV
RSENSE
VBAT
RF1
RF2
PC00337
The DC/DC converter works in flyback condition using a two step process.
During the ON-time of the MOSFET, energy is taken from the input and stored in the
primary winding of the flyback transformer. On the secondary side, the diode is reverse biased, thus the load is being supplied by the energy stored in the output bulk capacitor.
As soon as the power-mos turns off, the primary circuit is open and the energy stored in
the primary is transferred to the secondary by magnetic coupling. The diode is forward biased, and the stored energy is delivered to the output capacitor and then on the load.
The dots on the transformer must be in accordance with the voltage, so that during the ON­time of the MOSFET they indicate the positive side with respect to the other one of the transformer. During MOSFET OFF-time they indicate the negative.
The MOSFET must be chosen with the correct Vds voltage rating, considering also the voltage reflected back (Vr) to the primary through the turns ratio n.
The reflected voltage (Vr) must be added to the input voltage VPOS giving out a much higher voltage on the drain of the Mosfet (VBAT / n ) + VPO S.
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