ST AN2132 APPLICATION NOTE

AN2132
Obsolete Product(s) - Obsolete Product(s)
Application note
STLC3075 very low single supply SLIC
for WLL application in flyback configuration
Introduction
The STLC3075 is a SLIC device specially designed for WLL (Wireless Local Loop) and ISDN terminal adapters.
19-Feb-2007 Rev 3 1/26
www.st.com
Obsolete Product(s) - Obsolete Product(s)
Content AN2132
Content
1 Wireless local loop system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1 TQFP 10 mm x 10 mm x 1.4 mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1 VBAT voltage generat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.2 Operati on in off-hook condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.3 VPOS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.4 Start-up and DC-DC converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.5 Suggested transformers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.6 Input curr ent limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.7 VPOS current capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.7.1 With USA REN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.7.2 With European REN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.8 RSENSE setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.9 Trapezoidal ringing signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.10 Ringer load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.10.1 With European REN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.10.2 With USA REN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.11 Efficiency and powe r dissipation in flyback configuration . . . . . . . . . . . . . 14
3.12 Micro interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.13 Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.14 Ring trip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.15 PCB precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.16 Ground configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.17 Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.18 On-hook transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.19 Phone detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2/26
3.20 ESD immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.21 Setting resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.22 Longitudinal balance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Obsolete Product(s) - Obsolete Product(s)
AN2132 Content
3.23 TTX filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.24 Gain settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.25 Complex impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4 Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Appendix A STLC3075 in application with VPOS > 12 V. . . . . . . . . . . . . . . . . . . 24
Appendix B STLC3075 for USB suspended current specification. . . . . . . . . . . 25
3/26
Obsolete Product(s) - Obsolete Product(s)
Wireless local loop system AN2132
WLL
SLIC
WLL SLIC
WLL SLIC

1 Wireless local loop system

Figure 1. Wireless central office to premises diagram
WLL SLIC
WLL SLIC
WLL
SLIC
Central
office
Local loop
SLIC
Base station
transceiver
Final connection
by radio link
=
wireless
local loop
The main characteristics of this device consist in the possibility to:
operate with a single supply voltage in Fly-Back or Buck-Boost config urati on (see
AN2118 for information on Buck-Boost configuration)
operate in Fly-Back configuration with a single supply voltage VPOS in a range from
+4.5 V to +12 V
generate negative battery voltage
generate a ring signal (trapezoidal wave form)
PC00335
4/26
Obsolete Product(s) - Obsolete Product(s)
AN2132 Packaging

2 Packaging

STLC3075 is housed in standard TQFP package plastic with copper lead frame. No copper slugs protrude from the plastic body. STLC3075 uses the “standard” package option.
The thermal resistances, shown in junction and the ambient still air, and are calculated or measured in ° C/W.
Table 1. Thermal resistance versus package size
Symbol Parameter Value Unit
Rth j-amb
Rth j-amb
Thermal resistance junction ambie nt (Full plastic TQFP on single layer board)
Thermal resistance junction ambie nt (Full plastic TQFP on four layer board)
Table 1
and

2.1 TQFP 10 mm x 10 mm x 1.4 mm

Theta (j-a) on boards, in still air
Figure 2. Thermal resistance versus board structure
Figure 2
, are considered between the
70 ° C/W
45 ° C/W
5/26
Obsolete Product(s) - Obsolete Product(s)
Application information AN2132

3 Application information

Figure 3. Typical application schematic
RD
CVPOS
VPOS
VPOS
GATE
RSENSE
VBAT
CLK
TIP
RING CSVR CREV
RTH RLIM IREF
T1
Q1
RF1
RF2
CSVR
RTH
N-ch
R
SENSE
D1
CV
RSF
CSF
CVB
VF CZ
RP
RP
RREF
CZ
CLK
TIP
RING
CREV
RLIM
CONTROL
INTERFACE
TTX CLOCK
DET
D0 D1 D2 PD
CCOMP
CFL
VDD
CH
RDD
RLV
RLV
RS
ZAC
TX
RX
RRX
AGND
RX
TX
RS ZAC ZAC1
ZA
ZB
ZB
GAIN SET
DET D0 D1 D2 PD CKTTX
CTTX1
CS
CTTX2 FTTX
RTTX
BGND
CAC
CVCC
CVCC
STLC3075
ILTF
SYSTEM GND
SUGGESTED GROUND LAY-OUT
AGND
BGND
PGND
RTTX
CTTX
CAC
RD
CRD
D04TL625A

3.1 VBAT voltage generation

When operated with a positive supply voltage VPOS and a correctly set clock signal (typically 125 kHz), the SLIC generates a VBAT voltage for the active and ring operations.
The VBAT voltage lev el, with a 10% spread, is defined by the voltage divider RF1 / RF2 and can be set by choosing an RF1 value from a recommended set of values (see
Table 2. VBAT voltage values (VPOS = 4.5V)
RF1 (KΩ) VBAT (Active mode) VBAT (Ring mode)
270 -46.1V -64.4V 285 -48.4V -67,8V 300 -51.9V -71.7V 315 -54.3V -75.2V
Table 2
):
330 -56.3V -78.2V
6/26
Obsolete Product(s) - Obsolete Product(s)
AN2132 Application information
These values are referred to the device in active mode, on-hook condition (IL = 0mA) and in ring mode without load.
The VBAT value must be chosen taking into account the absolute maximum ratings of the device (VBTOT = 90 V). VBTOT = (VBAT + VPOS) = 90 V must not be exceeded.
When ring mode is selected through the control interface, the VBAT voltage is increased by an internal circuit from it’s active level to a predetermined value for ring mode. These two voltage levels (VBAT active and VBAT ring) are hence correlated. When one is set, (ring or active), the other is also set at the same time.

3.2 Operation in off-hook condition

A major feature of this device is that when changing from on-hook to off-hook conditions (IL >0 mA), the VBAT voltage is automatically adjusted depending on the loop resistance and on the programmed current limitation value (ILIM).
It should be noted that the device is optimized to operate on short loop applications (RLOOP ≤ 500 Ω) in order to obtain the co rrec t ri ng-trip detection.
In these conditions, with line current reaching the programmed constant current feed value (ILIM), the STLC3075 works like a current generator with a fixed DC current.
A fixed voltage drop, 4 V on TIP/GND and approximately 6 V on RING/VBAT, assures the DC functionality and the proper swing for the AC signal.
When the line is set off-hook, the STLC3075 automatically adjusts the generated battery voltage (VBAT) to feed the line with a fixed DC current (programmable via RLIM), and so optimizes power dissipation.
Considering maximum and minimum values for RLOOP ranging from 500 to100 Ω, and with fixed parameters ILIM = 25 mA and 2Rp = 100 Ω, the battery voltage (VBA T) will be equal to:
1. VBAT = 25 mA x (500+100) + 10 V = - 25 V
2. VBAT = 25 mA x (100+100) + 10 V = - 15 V A correctly set current threshold (typically 9 mA), programmable by external resistor RTH,
allows the correct on/off hook transition function. During the off-hook dynamic transition, the CAC capacitor is charged. The line current
regulator system senses the current flowing into RD and reduces the ILOOP current to the programmed ILIM value, set by RLIM.
The settling time of the ILIM current is about 150 ms, and it is a function of the CAC splitter capacitor (min . value allowed is 22µF).

3.3 VPOS characteristics

The input voltage VPOS can change slowly within the data sheet range (4.5 V - 12 V) without any effect on the VBAT voltage.
The STLC3075 can continue to operate correctly even if the VPOS voltage occasionally goes below 4.5 V (instantaneous value, not steady-state). The only limitation is the minimum voltage required on the external PMOS to keep it in a linear area.
Fast transients, ripples and spikes on the supply voltage V a reduced amplitude, depending upon the voltage supply rejection of the device.
7/26
will appear on TIP/RING with
POS
Obsolete Product(s) - Obsolete Product(s)
Application information AN2132
Bench measurements on SVRR give -35 dB @ f = 50 Hz and -47 dB @ f = 4 kHz, using the test circuit configuration with the device in active mode, loaded with an RLOOP = 500 Ω, and ILIM = 25 mA.

3.4 Start-up and DC-DC converter

In order to prevent problems during start-up, an internal circuit turns-on the gate of the MOSFET only when VPOS reaches 4 V and turns it off for VPOS lower than 3 V.
For VPOS voltage higher than 4 V the DC/DC converter power-on is controlled by a soft start circuit embedded on the devices.
Figure 4. DC-DC converter circuit
VPOS
Low/high
duty cycle
comparator
125 kHz
clock
Maximum
duty cycle
comparator
(see figure VPOS current
capability circuit)
PWM
comparator
Logic
Ramp
gen.
VREF
Current
limiter
Switch
driver
CSF
RSF
CV
RSENSE
VBAT
RF1
RF2
PC00337
The DC/DC converter works in flyback condition using a two step process.
During the ON-time of the MOSFET, energy is taken from the input and stored in the
primary winding of the flyback transformer. On the secondary side, the diode is reverse biased, thus the load is being supplied by the energy stored in the output bulk capacitor.
As soon as the power-mos turns off, the primary circuit is open and the energy stored in
the primary is transferred to the secondary by magnetic coupling. The diode is forward biased, and the stored energy is delivered to the output capacitor and then on the load.
The dots on the transformer must be in accordance with the voltage, so that during the ON­time of the MOSFET they indicate the positive side with respect to the other one of the transformer. During MOSFET OFF-time they indicate the negative.
The MOSFET must be chosen with the correct Vds voltage rating, considering also the voltage reflected back (Vr) to the primary through the turns ratio n.
The reflected voltage (Vr) must be added to the input voltage VPOS giving out a much higher voltage on the drain of the Mosfet (VBAT / n ) + VPO S.
8/26
Obsolete Product(s) - Obsolete Product(s)
AN2132 Application information
A MOSFET with a VDS greater than two times the VPOS voltage is recommended. The STN4NF03L, with a VDS of 30 V satisfies this parameter.
In the same way, the diode SMBYT01-400 with a VRRM of 400 V is able to operate properly considering a reverse voltage value calculated by VPOS x turns ratio + VBAT. In order to guarantee correct discharge timing to the transformer, avoiding possible saturation phenomenon, the max duty-cycle is limited to 60%, with a minimum duty-cycle of about 5%.

3.5 Suggested transformers

COEV magnetics type MGPWG-00007 Flyback transformer: 4 W; 1:16 To be used in VPOS range = 4.5 V/8.5 V
Table 3. Transformer Electrical specifications - VPOS range = 4.5V/ 8.5V
Test description Limit Units Tol. Notes
Inductance 0.019 mH +/- 8% 1-3, 10 kHz, 100 mVA C, Ls. Leakage inductance 0.400 µH Max. 1-3, 10 kHz, 10 mA, Ls.
(1)
DC resistance 0.101 DC resistance 19.50 Turns ratio 16:1 - +/-4% (4-6): (1-3), 10 kHz, 100 mVAC
Dielectric 1.500 VAC 500 µA
1. @ +20° C unless noted otherwise
Max. 1-3 Max. 4-6
1-4, 1 second test, 500µA max leakage current
COEV magnetics type MGPWG-00008 Flyback transformer: 4 W; 1: 8 To be used in VPOS range = 8.5 V/12 V
Table 4. Electrical specifications - VPOS range = 8.5V/12V
Test description Limit Units Tol Notes
Inductance 0.019 mH +/- 8% 1-3, 10 kHz, 100 mVAC, Ls. Leakage inductance 0.400 µH Max. 1-3, 10 kHz, 10 mA, Ls. DC resistance 0.101 DC resistance 5.83 Turns ratio 8: 1 - +/-4% (4-6): (1-3), 10 kHz, 100 mVAC
Dielectric 1.500 VAC 500 µA
1. @ +20° C unless noted otherwise.
Max. 1-3 Max. 4-6
1-4, 1 second test, 500 µA max leakage current
(1)
9/26
Obsolete Product(s) - Obsolete Product(s)
Application information AN2132
Table 5. Coilcraft type FA2469-AL electrical specifications
Test description Limit Unit Tol Notes
Inductance 0.0205 mH Max 1-3, 10 kHz, 100 mVmrs
Leakage inductance 0.414 µHMax
DC resistance 0.036
Max 1-3
1-3, 100 kHz, 100 mVmrs short pins 4,6
DC resistance 16.50 Turns ratio 16:1 - +/-4% (4-6):(1-3), 10 kHz, 100 mVAC
HI POT 1.500 VAC
Table 6. Coilcraft type FA2470-AL electrical specifications
Test description Limit Unit Tol Notes
Inductance 0.0205 mH Max 1-3, 10 kHz, 100 mVmrs
Leakage inductance 0.40 µHMax
DC resistance 0.036 DC resistance 7.92 Turns ratio 8:1 - +/-3.3% (4-6):(1-3), 10kHz, 100 mVAC
HI POT 1.500 VAC

3.6 Input current limitation

Max 4-6
VDC to be applied for 1 second from pins 1,3 to pins 4,6. 500 µA max leakage current
1-3, 100 kHz, 100 mVmrs Short pins 4,6
Max 1-3 Max 4-6
VDC to be applied for 1 second from pins 1,3 to pins 4,6. 500 µA max leakage current
In WLL applications, the power supply usually does not have high-power current capability. Therefore when a ring trip occurs, the status of the SLIC changes from ring mode to off­hook condition. As the loop current control does not react immediately, the line current reaches the output stages current limitation value of about 80 mA.
As a consequence, a high peak current is sunk from VPOS which could be higher than its maximum current capability . In this case, if no limiting current circuit is used, (RSENSE = 0), the VPOS voltage would drop.
To prevent this, the STLC3075 incorporates a circuit to limit peak current on the VPOS input. The peak current value is defined by the formula:
IPEAK
375mV
--------------------------=
RSENSE
This input current limitation circuit operates during all transients caused by changes in the
10/26
line current conditions.
Obsolete Product(s) - Obsolete Product(s)
AN2132 Application information

3.7 VPOS current capability

The following tables summarize the approximate value of the Ivpos current, drawn from the VPOS supply vs. REN 20Hz condition (For REN definition see section
RSENSE = 0.22 mΩ.

3.7.1 With USA REN

1REN (USA) = 8 µF + 6930 Transformer MGPWG-00007 for the VPOS range 4.5 V- 8 V. Transformer MGPWG-00008 for the VPOS range 9.0 V-12 V
Table 7. Ivpos, average current (USA REN)
VPOS (V)
4.5 185 340 520 750 6 145 260 360 640 8 115 145 270 440 9 100 180 240 400
10 90 150 220 330 12 80 130 180 280
Table 8. Ivpos, peak current (USA REN)
1REN 2REN 3REN 5REN
Ivpos (mA) Ivpos (mA) Ivpos (mA) Ivpos (mA)
3.10
below).
1REN 2REN 3REN 5REN
VPOS (V)
Ivpos (mApk) Ivpos (mApk) Ivpos (mApk) Ivpos (mApk)
4.5 800 1100 1300 1700 6 700 1000 1400 1800 8 800 1000 1400 1900 9 800 1100 1300 1900
10 800 1100 1300 1700 12 800 1100 1300 1700
11/26
Obsolete Product(s) - Obsolete Product(s)
Application information AN2132

3.7.2 With European REN

1REN (Europe) = 1 µF+1800 Transformer MGPWG-00007 for the VPOS range 4.5 V- 8 V Transformer MGPWG-00008 for the VPOS range 9.0 V-12 V
Table 9. Ivpos, average current (European REN)
1REN 2REN 3REN
VPOS (V)
Ivpos (mA) Ivpos (mA) Ivpos (mA)
4.5 150 270 370 6 115 185 270 8 90 145 200 9 80 125 180
10 75 120 170 12 65 100 140
Table 10. Ivpos, peak current (European REN)
1REN 2REN 3REN
VPOS (V)
Ivpos (mApk) Ivpos (mApk) Ivpos (mApk)
4.5 700 1900 1900 6 900 1300 1600 8 900 1300 1600 9 900 1300 1500
10 1000 1300 1500 12 1000 1300 1500
Figure 5. VPOS current capability circuit
12/26
Obsolete Product(s) - Obsolete Product(s)
AN2132 Application information

3.8 RSENSE setting

The RSENSE resistor sets the input peak current value, which must be lower than the power supply current capability limit.
In a typical application, the input peak current is fixed at 1.7 ApK (375 mV / 220 mΩ) in order to guarantee optimum performance in the total range of the current loop (20 to 40 mA) and the V
supply (4.5 to 12 V), driving up to 5REN of load.
POS

3.9 Trapezoidal ringing signal

In the application domain targeted for this product (Integrated Access Device, Set Top Box,
Small Offic e Home Of fice e tc... .) non sinus oidal ring w av ef o rms are acce pted. Therefore the
STLC3075 generates ringing signals with a trapezoidal waveform. This type of waveform is very similar to a sine wave whose distortion can be kept lower than
5% and crest factors have a value of 1.2, just by corr ect selection of the external CREV capacitor.
Because the value of CREV is a function of the ringing frequency, this value has to be adapted to the ringing frequency used.
A CREV in the range 18 to 22 nF gives a trapezoidal ringing signal and correct shaping with 20 to 25 Hz ringing frequency. To increase the ringing frequency to 68 Hz, the value of CREV should be chosen in the range of 6.8 to 8.2 nF.

3.10 Ringer load

3.10.1 With European REN

In a typical application the STLC3075 can drive up to 3REN european standard (1REN = 1800 Ω + 1 µF), @ f = 20 Hz, with crest factor (VppK / Vrms) = 1.22. The levels measured at the ringer terminal are summarized in the following tables.
Table 11. Ringer load (VPOS = 4.5 V) with European REN
CREV Crest factor
22nF 1.22 65.6V 53.5V 64.8V 52.8V
Table 12. Ringer load (VPOS = 12 V) with European REN
CREV Crest factor
22nF 1.22 66.4V 54.2V 65.6V 53.2V
1 REN
Vppk Vrms
1 REN
Vppk Vrms

3.10.2 With USA REN

If the device has to drive up to 5REN, as requested by USA specifications (1REN = 8 µF + 6930 Ω) it is necessary to modify the value of RD = 2.2 kΩ in order to avoid false off-hook detection (IRTH = 100/RD). The following tables summarize the results @ 20Hz ringing frequency.
3 REN
Vppk Vrms
3 REN
Vppk Vrms
13/26
Obsolete Product(s) - Obsolete Product(s)
Application information AN2132
Table 13. Ringer load @ 20 Hz ringing frequency (V
CREV Crest factor
1 REN
Vppk Vrms
Vppk Vrms
= 4.5V) with USA REN
POS
3 REN
5 REN
Vppk Vrms
22nF 1.22 65.0V 53.2V 62.8V 51.5V 61.2V 50.0V
Table 14. Ringer load @ 20Hz ringing frequency (V
CREV Crest factor
1 REN
Vppk Vrms
=12V) with USA REN
POS
3 REN
Vppk Vrms
5 REN
Vppk Vrms
22nF 1.22 65.6V 53.7V 63.2V 52.0V 61.2V 50.3V

3.11 Efficiency and power dissipation in flyback configuration

At the fixed CLK frequency (125 kHz), the best DC/DC converter efficiency can be obtained with:
a good compromise between RDS-ON and the parasitic input/output capacitances
value of the NchMOS. For this reason the power Mos STN4NF03L has been chosen.
a high efficiency, fast recovery diode, like the ST SMBYT01-400, showing a Trr max of
35 ns @ VF = 1 A.
a transformer suited to DC/DC applications.
The following tables (
Table 15
and
Table 16
) summarize the measurements of the DC/DC
converter efficiency, made on an ST board. The efficiency parameter η is calculated with the following formula:
Idc
--------
VBAT
dc
------------ ------------- ------------ ----------- ------------- --
η
IVPOStot IVPOSslic
VPOS=
Figure 6. Circuit configuration for DC/DC converter efficiency measurements
AGND
IVPOS Tot
BGND
IVPOS
VPOS
GATE
RSENSE
VBAT
Idc/dc
CSF
CVPOS
RSF
CV
Q1
N-ch
R
SENSE
T1
D1
VPOS
D05tl632
14/26
Obsolete Product(s) - Obsolete Product(s)
AN2132 Application information
Table 15. H.I. feeding @ open circuit
VPOS (V)
4.5 13.80 3.75 0.12 51.8 64.20 5.07 6 14.10 4.4 0.12 52.0 76.80 5.07
8.5 14.15 4.13 0.12 52.0 89.59 5.08 1/16
8.5 12.40 4.75 0.12 52.0 58.82 5.08 1/8
12 13.05 4 .2 0.12 52.0 96.48 5.08
Table 16. Active mode @ RLOOP = 500
VPOS
(V)
4.5 205 6.5 29.26 24.5 893.25 716.87 80% 1/16 6 154 7.1 29.28 24.53 881.40 718.24 81%
8.5 113 7.58 29.3 24.54 896.07 719.02 80% 1/16
8.5 105 7.7 29.34 24.5 827.05 718.83 87% 1/8
12 77.7 8.05 29.38 24.57 835.80 721.87 86% 1/8
Ivpos
(mA Tot)
Ivpos
(mA Tot)
Ivpos
(mA
pin25)
Ivpos
(mA
pin25)
IDC/DC
IDC/DC
(mA)
(mA)
VBAT
Note: Note that for a given value of supply voltage V
supply will be influenced by the electrical characteristics of the selected transformer.
(mW)
Pvpos
(mW)
Pvbat
(mW)
VBAT (V)
Pvpos
(V)
, the current consumption from V
POS
Pvbat
(mW)
Eff%
Ratio
trafo
Ratio
η
trafo
POS

3.12 Micro interface

The input levels are interpreted as TTL levels, therefore both 3.3 or 5 V CMOS input signals can be accepted by the STLC3075.
The output DET signal is an open drain (needing an external pull-up resistor to VCC), therefore both 3.3 and 5 V logic levels can be generated, depending on the value of VCC.

3.13 Protection

Different circuit configurations can be used to protect the device from overvoltages. The best solution to use depends on the specified overvoltage and on whether or not the
environment where the STLC3075 has to work is defined by the K20 requirements. If K20 is requested, a solution that includes a transient voltage suppressor LCP1521, PTC
resistors, and two transils has to be used (see Two diodes inside the LCP1521 will clamp to ground any positive lightning, power cross and
voltage overstress. For negative overvoltages, the device will fire because of the gate triggered on the voltage
VBAT. A series of two transils (2 x SM6T39A), to best fit the voltage clamp (typically 78 V), will avoid exceeding the total voltage (Vbtot) applied to the device supply pins.
Figure 7
).
15/26
Obsolete Product(s) - Obsolete Product(s)
Application information AN2132
Note: Vbtot = VPOS + VBAT = 90V according to the absolute maximum rating of the STLC3075.
PTC resistors like the Raychem TR250/80T series will prevent damaging during power cross conditi ons.
Figure 7. Standard overvoltage protection configuration for K20 compliance
BGND
STLC3055N
TIP
RP1
RP2
TIP
2 x
SM6T39A
RING
VBAT
RP1
LCP1521S
RP2
RP1 = 30ohm: RP2 =Fuse or PTC > 18ohm
RING
RP1 = 30 Ω and RP2 ≥18 Ω When K20 requirements are not necessary, a simpler solution consists in the adoption of
diodes between VBAT/TIP, RING, TIP, and RING/GND. Suggested diodes are:
BYT 11-600 or BYW 100-200 for through hole assembly
STTB 106U or STPR 120A for SMD assembly .
Also in this case, 2 x SM6T39A transils must be used (see
Figure 8
).
Figure 8. Simplified configuration for indoor overvoltage protection
STPR120A
RP2
RP2
TIP RING
2 x
BGND
STLC3055N
TIP
RING
SM6T39A
RP1
RP1
VBAT
STPR120A
RP1 = 30ohm: RP2 =Fuse or PTC > 18ohm
RP1 = 30 Ω and RP2 ≥18 Ω
16/26
Obsolete Product(s) - Obsolete Product(s)
AN2132 Application information

3.14 Ring trip

In this SLIC, the ring trip detection is performed by sensing the average current (an image of the line current) injected in the RD resistor, rectified by a dedicated circuit.
It is then filtered by a CAC capacitor and compared to the internally programmed ring trip threshold (IRTH) by the RD resistor itself. Do not confuse this with the RTH resistor which sets the off-hook threshold for active and H.Z. modes.
If the average of the trapezoidal AC current changes in the transition from higher ring impedance (On-hook condition) to low impedance (Off-hook condition), the voltage on the RD resistor increases.
As soon as this voltage goes over the programmed threshold (IRTH), the ring trip will be detected.
In ring mode there is no DC current into the RD resistor, but only the rectified average current. It is clear that the previously described ring trip method is optimized to operate in short loop (<500 Ω) applications and not in the presence of a very long line.
The ring-trip detection threshold is programmed by the formula: IRTH = 100/RD. With 20 Hz of ring frequency, CAC=22 µF, and RD=4 kΩ, the pin DET goes low about
100 ms after the off-hook transition. When the SLIC is in ring mode, the maximum average current depends of the REN load.
During normal functioning, this current must be lower than the IRTH threshold. Typical applications can guarantee up to 3REN of load. By increasing the REN number up to
5REN, the AC load will increase. The average current l can then become higher than IRTH and a ring trip will be detected. It is possible to readjust this situation by reducing the value of RD. Alternatively, increasing the IRTH threshold will also increase the ring trip time.
In summary, the ring trip is a function of:
the load (REN number)
the value of the ring trip rectified average threshold current "IRTH"
the value of the maximum peak current sunk from VPOS "Ipk" - higher the REN number
lower the value of RSENSE
17/26
Obsolete Product(s) - Obsolete Product(s)
Application information AN2132

3.15 PCB precautions

Figure 9. Layout reference
VPOS
AGND BGND
VPOS
SENSE
R
CVPOS
GATE
RSF
CSF
VBAT
CV
Q1
N-ch
R
SENSE
T1
D1
PC00342
Good PCB layout is a basic requirement to avoid noise problems that can have a negative impact on the device operating conditions.
In practice, noise can come from grounding, power supply, parasitic coupling between PCB tracks, and from high impedance points.
The PCB layout should prevent any coupling between the DC/DC converter components and analog pins that are referred to AGND (for example: RD, IREF, RTH, RLIM, VF).
As a first recommendation, the components CV, T1, D1,N-MOS, CVPOS, and RSENSE should be kept as close as possible to each other and isolated from the other components.
Noise could be produced by ripple on the CVBAT capacitor and in particular across its equivalent series resistor value (ESR). The lower this value, the lower the ripple that can be present on VBAT.
Particular care has to be taken on the tracks used for connection between VPOS and the DC/DC converter, which must be low impedance tracks due to the high current flowing in them.
Noise can also be prevented by connecting RREF (26K1) as close as possible to the IREF pin.
18/26
Obsolete Product(s) - Obsolete Product(s)
AN2132 Application information

3.16 Ground configuration

Another important point is the ground connection: a star configuration is suggested (see
Figure 10
Figure 10. Suggested ground lay-out
It is important to create a specific P-GND area on the layout, with connections to:
the GND of the CV electrolytic capacitor,
the GND of the CVPOS electrolytic capacitor,
the GND of the transformer T1.
This P-GND area has to be connected to the center of the star via a dedicated track. In this way, any disruptions from the peak current produced by the switching transistor will
be cooled by the center of the GND star (system GND), without any disturbance on the other GND (AGND/BGND).
).
System GND
GND
AGND
BGND
PGND
All the other components have to be connected on the GND area.

3.17 Capacitor

Ceramic capacitors CVB and C14 may be used to filter the high frequency ripple and noise that electrolytic capacitors CV and CVPOS respectively are unable to reject.
It is also advisable to connect a 100 nF capacitor from VPOS and GND in order to cancel any high frequency noise on the VPOS pin. This capacitor may not be required, depending on the high frequency sensitivity of the apparatus that the STLC3075 device is included in.
CRD avoids noise coupling on the RD pin, which is a high impedance input.

3.18 On-hook transmission

Voice transmission performances are guaranteed in the complete range of loop currents down to 0mA, when setting the SLIC in active mode, and receiving data on the RX pin during ringing pause.
The maximum output voltage is correlated to the 2 wire overload voltage parameter (see the datasheet).
19/26
Obsolete Product(s) - Obsolete Product(s)
Application information AN2132

3.19 Phone detection

The pin DET can also be used to detect the load status of the line. When the loop is in on-hook condition with a typical telephone connected, setting the SLIC
in active reverse polarity and then changing its status to H.I. feeding, pin DET will go to low level for a time of about 1.5 ms. If the line is open, this time is reduced to about 2 µs.

3.20 ESD immunity

The ESD protection in this device withstands a discharge of 2kV with the Human Body Model. If the STLC3075 must operate in sensitive apparatus where equipment tests against ESD immunity are required (4kV, 8kV), some precautions have be taken.
During these tests, where the device is usually powered, ESD transients can put the internal ESD protection diodes (connected on VPOS and RSENSE pins) into the ON condition.
When the transient disappears and the VPOS supplied is higher than 9 V, the internal ESD diodes are not able to recover back to the OFF condition.
Using a VPOS supply of less than 9 V, the recovery of the ESD diodes is guaranteed and the equipment will be able to pass the ESD immunity tests. When it is not possible to use a reduced VPOS voltage, a solution can be found by putting a 100 resistor in series at pin VPOS, without any impact on the threshold of the input limitation circuit.
Figure 11. Circuit configuration for V
CVPOS
VPOS
VPOS
GATE
RSENSE
VBAT
CVCC
CVCC
100
VF
POS
>9V
CSF
CVB
RSF
RF1
RF2
Q1
N-ch
R
SENSE
T1
D1
CV
PC00344

3.21 Setting resistor

The following current is flowing into the resistor of the STLC3075 application:
IRLIM, IRTH, IRREF = 1.3 V/R
IRD = Iline/100
IRSENSE = 100 mV/RSENSE
IRF1, IRF2 can be considered around 300 µA
No DC current flows into RS, ZAC, ZA, ZB, RLV, RTTX.
20/26
Obsolete Product(s) - Obsolete Product(s)
AN2132 Application information

3.22 Longitudinal balance

To avoid degradation on this parameter, it is very important to use Rp resistors with 1% tolerance, and (if used) PTC resistors with 1% matching.
Low longitudinal balance rejection, caused by the mismatching of the resistors or PTC, can generate noise problems. For example in a GSM based WLL, noise can be generated from the 25 Hz produced by the 4 ms burst of the antenna transmission.

3.23 TTX filter

A dedicated metering pulse low pass filter (12 kHz to 16 kHz), with 3rd order filtering can be obtained by choosing the following values for the external components:
RLV=16K2//16K2 =8.1K, CFL=1.5 nF, R1=1.3 MΩ, R2=180K, C1=47 pF, C2=6.8 pF. If the TTX is not requested, the components RLV, CS, CFL, RTTX, CTTX can be removed.
In addition, the pins CKTTX, CTTX1, CTTX2, FTTX have to be connected to GND, and the pin RTTX open.

3.24 Gain settings

In order to adapt the SLIC versus the 3.3 V low supply voltage CODEC, the device provides the possibility to change the TX and RX gains by the gain set control pin.
Table 17. TX and RX gains by the gain set control pin
Gain set RX gain TX gain Impedance synthesized scale factor
0 0dB - 6dB X 50 1 + 6 dB - 12dB X 25

3.25 Complex impedance

Most countries (administration) adopt complex impedance for both the “Exchange Impedance” (Zexch) and the “Balance impedance”, instead of a 600 purely resistive impedance. As a consequence, the AC input impedance that the SLIC plus protection resistor shows at its line terminals (Zs), has to be calculated in order to correctly match the Zexch, to obtain good performance on the return loss parameter.
When Zexch is a complex impedance, the synthesized impedance Zs will be calculated as:
where 50 is a fixed scale factor. (For ZAC definition see datasheet.) For gain set = 1 the scale factor is 25.
Zs
ZAC
------------ 2Rp+= 50
Considering, for example, the ETSI 2 complex impedance Zexch = 270 + (750//150nF).
21/26
Obsolete Product(s) - Obsolete Product(s)
Application information AN2132
An AC input impedance has to be synthesized on pins TIP/RING of the SLIC (ZAC), to do so, considering the line terminal, the proper Zs have to be calculated as:
ZAC =(Zs-2Rp)*50 because 2Rp = 100
ZAC = (270-100)*50 + [(750*50)//(150 nF/50)] = ZAC = 8.5K + (37.5K//3 nF)
In this way the SLIC will synthesize Zs impedance matching correctly the Zexch. Also for the 2 to 4 wire conversion, the administration defines an AC terminal balance
impedance Zb properly used to obtain the THL performance. Good trans-hybrid loss performance, and therefore proper echo cancellation, can be
obtained by correctly matching the two external impedances, ZA and ZB, which can also be complex impedances.
ZA = 50 x Zexch ZB = 50 x Zb For gain set = 1, the scale factor is 25. In case of Zb = Zexch, the impedances ZA and ZB can be replaced by two resistors
calculating their value as: ZA = ZB = 50 x |Zexch|. For gain set = 1 the scale factor is 25. Where |Zexch| is t he modules @ 1 kHz. For ETSI 2 the value |Zexch| = 842 ZA = ZB = 50 x 842 Ω = 42.1 k A typical value of 120 pF (with gain set = 0) for the capacitors CComp and CH guarantee
both the loop stability and good THL performance. For gain set = 1 the capacitor value is doubled.
22/26
Obsolete Product(s) - Obsolete Product(s)
AN2132 Support

4 Support

Please contact your local ST sales office for details of the STLC3075 firmware.

5 Revision history

Table 18. Document revision history
Date Revision Changes
09-Jun-2006 1 Initial release. 09-Jun-2006 2 Updated
19-Feb-2007 3
Updated added
Section 3.7 Figure 3
Table 5
and
. Added
. Added references to Coilcraft in
Table 6
Appendix A
.
and
Appendix B
Table 4
.
and
23/26
Obsolete Product(s) - Obsolete Product(s)
STLC3075 in application with VPOS > 12 V AN2132

Appendix A STLC3075 in application with VPOS > 12 V

In a typical application the STLC3075 can operate correctly up to a 12 V VPOS voltage. Using the Fly Back configuration, and by modifying the typical circuit configuration by just
adding a zener diode or a voltage regulator, it is possible to provide the right voltage to VPOS (pin 26) in order to get a voltage lower than 12V.
Using this circuit configuration it is necessary to use a MOSFET type STN3NF06L with a VDS of 60V.
Figure 12. STLC3075 for supply voltage >12 V
BZX84C-4V7
(sot-23)
47uF
26
26
VPOS
STLC3075
Vsupply (16V)
47nF
47uF
T1
T1
24/26
Obsolete Product(s) - Obsolete Product(s)
AN2132 STLC3075 for USB suspended current specification
V
Appendix B STLC3075 for USB suspended current
specification
In Power Down or H.I. mode, the current consumption from VPOS by the STLC3075 is about 12 mA. By turning off the DC/DC converter, pin CLK to GND, this value is reduced to about 4 mA.
In a USB bus-powered device, the total current taken from the USB bus has to be no more than 500 µA (see USB 2.0 para 7.2.3). To meet this specification, the only possibility is to turn-off the SLIC.
One possible way to do that is shown in the schematic below. Adding a few components, and using the STLC3075 in Fly-back configuration, it is possible
to meet this specification up to 4.75 V supply voltage, considering 250 mV as a max Vdrop of T2.
The STLC3075 can be set in self oscillation mode, hardware connecting pin CLK to pin CVCC.
A digital command, logic level High, connected to the SUS input will enable the two transistors T1 and T2 to provide the correct power supply to the pin 26 of the SLIC.
Figure 13. STLC3075 for USB suspend current specification
Vsupply >4.75
(a)
10K
T2
Pin 26 VPOS
T1
Pin CLK to pin VCC or High digital level
10K
SUS Input
100µF47nF
T1
T1
a. Current consumption < 1mA
25/26
Obsolete Product(s) - Obsolete Product(s)
AN2132
Please Read Carefully:
Information in this document is provided sole ly in connecti on with ST produ cts. STMicro electroni cs NV and its subsi diaries (“ST ”) reserve the right to make changes , cor recti ons , modif ic ations or improv ement s, t o th is documen t, and the prod ucts an d servic es des crib ed he rein a t any time, without notice.
All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no
liability whatsoever relating to the choice, selection or use of the ST products and servic es described herein. No license, express or implied, by estoppel or otherwis e, to any intellectual property rights is granted under this document. If any part of this
document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein.
UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZE REPRESENTATIVE OF ST, ST PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS, WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE.
Resale of ST products with prov isions differen t from the state ments and/or tec hnical featur es set forth in th is document shall immediatel y void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST.
ST and the ST logo are trademark s or registered trademarks of ST in various countries.
Information in this document su persedes and replaces all information previously supplied.
The ST logo is a registered trade mark of STMicroelectronics. All other names are the property of t heir respective owners.
© 2007 STMicroelectronics - All rights reserv ed
STMicroelectronics group of companies
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -
Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United St ates of America
www.st.com
26/26
Loading...