The STLC3075 is a SLIC device specially designed for WLL (Wireless Local Loop) and
ISDN terminal adapters.
This document contains a description of the device functions in buck-boost configuration,
and provides some application hints. The device data sheet is an essential complement to
this application note, providing important reference information that will simplify
understanding of the content.
Figure 1.Wireless central office to premises diagram
WLL
SLIC
☎
WLL
SLIC
WLL
SLIC
☎
☎
Central
office
Local loop
SLIC
Base station
transceiver
Final connection
by radio link
=
wireless
local loop
☎
PC00335
The main characteristics of this device consist in the capability to:
●operate with a single supply voltage in Buck-Boost or Fly-Back configuration (see
AN2132 for information on Fly-Back configuration).
●In Buck-Boost configuration, it can operate as in the standard STLC3055N
application, with a VPOS voltage in a range from +5.5 V to +12 V.
●generate negative battery voltage
●generate a ring signal (trapezoidal wave form)
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Obsolete Product(s) - Obsolete Product(s)
AN2118Packaging
2 Packaging
The STLC3075 is housed in standard TQFP package plastic with copper lead frame. No
copper slugs protrude from the plastic body. STLC3075 uses the “standard” package option.
The thermal resistances, shown in
junction and the ambient still air, and are calculated or measured in ° C/W.
Table 1.Thermal resistance versus package size
SymbolParameter Value Unit
Rth j-amb
Rth j-amb
Thermal resistance junction ambient
(Full plastic TQFP on single layer board)
Thermal resistance junction ambient
(Full plastic TQFP on four layer board)
Table 1
and
2.1 TQFP 10 mm x 10 mm x 1.4 mm
Theta (j-a) on boards, in still air.
Figure 2.Thermal resistance versus board structure
Figure 2
, are considered between the
70° C/W
45° C/W
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Obsolete Product(s) - Obsolete Product(s)
Typical application schematicAN2118
3 Typical application schematic
Figure 3.Typical application schematic
VPOS
CVCC
CVPOS
RSENSE
VPOS
RSENSE
GATE
VBAT
CVB
VF
CLK
CLK
RP
TIP
RREF
RP
CREV
RLIM
RING
CSVR
CREV
RTH
RLIM
IREF
RD
RD
CRD
RING
D00TL489B
Q1
P-ch
D1
RF1
L
CV
RF2
TIP
CSVR
RTH
CCOMP
DET
CONTROL
D0
INTERFACE
D1
D2
PD
TTX CLOCK
SUGGESTED GROUND LAY-OUT
SYSTEM GND
TX
RX
RRX
AGND
TX
RX
RS
RS
ZAC
ZAC1
ZAC
ZA
CH
VDD
RDD
RLV
RLV
CFL
ZB
ZB
GAIN SET
DET
D0
D1
D2
PD
CKTTX
CTTX1
CS
CTTX2
FTTX
RTTX
RTTX
AGND
BGND
PGND
CTTX
BGND
CAC
CVCC
ILTF
CAC
3.1 VBAT voltage generation
When operated with a positive supply voltage VPOS and a correctly set clock signal
(typically 125 kHz), the SLIC generates a VBAT voltage for the active and ring operations.
The VBAT voltage level, with a 10% spread, is defined by the voltage divider RF1 / RF2 and
can be set by choosing an RF1 value from a recommended set of values (see
Table 2.VBAT voltage values
RF1 (kΩ) VBAT (Active mode) VBAT (Ring mode)
270 -45.8 V -64.0 V
285 -48.2 V -67,4 V
300 -51.2 V -71.8 V
315 -54.0 V -75.3 V
330 -56.0 V -78.2 V
These values are referred to the device in active mode, on-hook condition (IL = 0 mA), and
in ring mode without load.
The VBAT value must be chosen taking into account the absolute maximum ratings of the
device (VBtot = 90 V). VBtot = (VBAT + VPOS) = 90 V must not be exceeded.
When ring mode is selected through the control interface, the VBAT voltage is increased by
an internal circuit from it’s active level to a predetermined value for ring mode. These two
Table 2
):
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Obsolete Product(s) - Obsolete Product(s)
AN2118Typical application schematic
voltage levels (VBAT active and VBAT ring) are hence correlated. When one is set, (ring or
active), the other is also set at the same time.
3.2 Operation in off-hook condition
A major feature of this device is that when changing from on-hook to off-hook conditions
(IL >0 mA), the VBAT voltage is automatically adjusted depending on the loop resistance
and on the programmed current limitation value (ILIM).
It should be noted that the device is optimized to operate on short loop applications
(RLOOP ≤ 500 Ω) in order to obtain the correct ring-tr i p detec ti on.
In these conditions, with line current reaching the programmed constant current feed value
(ILIM), the STLC3075 works like a current generator with a fixed DC current.
A fixed voltage drop, 4 V on TIP/GND and approximately 6 V on RING/VBAT, assures the
DC functionality and the proper swing for the AC signal.
When the line is set off-hook, the STLC3075 automatically adjusts the generated battery
voltage (VBAT) to feed the line with a fixed DC current (programmable via RLIM), and so
optimizes power dissipation.
Considering maximum and minimum values for RLOOP ranging from 500 to100 Ω, and with
fixed parameters ILIM = 25 mA and 2Rp = 100 Ω, the battery voltage (VBAT) will be equal to:
1. VBAT = 25 mA x (500+100) + 10 V = - 25 V
2. VBAT = 25 mA x (100+100) + 10 V = - 15 V
A correctly set current threshold (typically 9 mA), programmable by external resistor RTH,
allows the correct on/off hook transition function.
During the off-hook dynamic transition, the CAC capacitor is charged. The line current
regulator system senses the current flowing into RD and reduces the ILOOP current to the
programmed ILIM value, set by RLIM.
The settling time of the ILIM current is about 150 ms, and it is a function of the CAC splitter
capacitor (min . value allowed is 22 µF).
3.3 VPOS characteristics
The input voltage VPOS can change slowly within the data sheet range (5.5 V - 12 V)
without any effect on the VBAT voltage.
The STLC3075 can continue to operate correctly even if the VPOS voltage occasionally
goes below 5.5 V (instantaneous value, not steady-state). The only limitation is the minimum
voltage required on the external PMOS to keep it in a linear area.
Fast transients, ripples and spikes on the supply voltage V
a reduced amplitude, depending upon the voltage supply rejection of the device.
Bench measurements on SVRR give -35 dB @ f = 50 Hz and -47 dB @ f = 4 kHz, using the
test circuit configuration with the device in active mode, loaded with an RLOOP = 500 Ω,
and ILIM = 25 mA.
will appear on TIP/RING with
POS
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