ST AN2117 APPLICATION NOTE
AN2117
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APPLICATION NOTE
STLC3055N SINGLE SUPPLY SLIC
FOR WLL APPLICATION
The STLC3055N is a slic device specially designed for WLL ( Wireless Local Loop) and ISDN
Terminal Adapters. It is a feature optimization of the first STLC3055Q generation
1 WIRELESS LOCAL LOOP SYSTEM
Figure 1.
The main characteristics of this device consist in the possibility to :
– operate with a single supply voltage in a range from + 5.5V to +12V
– generate the negative battery
– generate a ring signal (trapezoidal wave form)
In the following paragraphs a detailed description about device functionalities, as well as application hints, can be found. Having at hand a copy of the device Data Sheet is essential for
quicker and easier understanding of the content of this Application Note.
Rev. 2
AN2117/1105
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AN2117 APPLICATION NOTE
2 PACKAGE
STLC3055N is housed in standard TQFP package plastic with copper leadframe. No copper
slug surfaces out of the plastic body. STLC3055N uses the package option “standard”.
The thermal resistances, shown in Table 1 and Figure 2, are considered between the junction
and the ambient, in still air, and are calculated or measured in °C/W.
Table 1. Thermal Resistance versus Package Size
Symbol Parameter Value Unit
R
th j-amb
R
th j-amb
2.1 TQFP 10 x 10 x1.4
Theta (j-a) on boards - STILL AIR
Figure 2. Thermal Resistance versus Board Structure.
Thermal Resistance Junction Ambient (Full plastic TQFP on single layer board) 70 °C/W
Thermal Resistance Junction Ambient (Full plastic TQFP on four layer board) 45 °C/W
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3 TYPICAL APPLICATION SCHEMATIC
Figure 3.
CVCC
TX
RX
CVPOS
AN2117 APPLICATION NOTE
VPOS
RSENSE
CCOMP
DET
CONTROL
INTERFACE
SUGGESTED GROUND LAY-OUT
TTX CLOCK
D0
D1
D2
PD
SYSTEM GND
CFL
VDD
CH
RDD
RLV
RLV
ZAC
AGND
TX
RS
RX
RS
ZAC
ZAC1
ZA
ZB
ZB
GAIN SET
DET
D0
D1
D2
PD
CKTTX
CTTX1
CS
CTTX2
FTTX
RTTX
AGND
BGND
PGND
RTTX
BGND
CAC
CTTX
CAC
ILTF
CVCC
VPOS
RSENSE
GATE
VBAT
CLK
RING
CSVR
CREV
RTH
RLIM
IREF
RD
RD
CRD
CVB
VF
CLK
RREF
RP
RP
RING
CREV
RLIM
D00TL489A
TIP
Q1
D1
RF1
CV
RF2
TIP
CSVR
RTH
3.1 VBAT VOLTAGE GENERATION
The slic, when operated with a positive supply voltage V
125KHz), is able to generate a V
The V
voltage level, with a 10% of spead, is defined by the voltage divider RF1, RF2 and
BAT
voltage for the Active and Ring operation.
BAT
and a proper clock signal (typ
POS
can be set choosing a proper value of RF1 among a recommended set of values
P-ch
L
Table 2.
RF1 (KΩ)
V
270 -45.8V -64.0V
285 -48.2V -67,4V
300 -51.2V -71.8V
315 -54.0V -75.3V
330 -56.0V -78.2V
These values are referred to the device in Active mode, On-Hook condition (I
(Active mode) V
BAT
(Ring mode)
BAT
= 0mA) and in
L
Ring mode without load.
Of course the V
(V
) of the device, therefore, V
Btot
By an internal circuit this V
mined value generating the V
value has to be choosen taking into account the Absolute Max. Ratings
BAT
= (V
Btot
voltage (in active mode IL = 0) will be increased to a predeter-
BAT
for the R
BAT
BAT
+ V
ING
) = 90V mustn't be overcome.
POS
status, whenever the Ring mode is selected
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AN2117 APPLICATION NOTE
through the control interface.
These two voltage levels (i.e. V
Active, V
BAT
ring) are hence correlated, fixing one (Ring or
BAT
Active), the other will be fixed at the same time.
3.2 OPERATION IN OFF-HOOK CONDITION
Main feature of this device is that changing from On-Hook to Off-Hook condition, I
voltage will be automatically adjusted depending of the loop resistance and by the current
V
BAT
limitation value programmed (I
LIM
).
It should be noted that the device is optimised to operate on short loop applications (R
>0mA, the
L
loop
≤500Ω) in order to obtain a correct ring-trip detection.
In these conditions and for a line current reaching the programmed constant current feed value
(I
), the STLC3055N works like a current generator with a fixed DC current.
LIM
A fixed voltage drop, 4V on TIP/gnd and about 6V on RING/Vbat, assures the DC functionality
and the proper swing for the AC signal.
Therefore, once the line is set in Off-Hook, the STLC3055N automatically adjust the self generated battery voltage (V
) to feed the line with a fixed DC current (programmable via R
BAT
LIM)
OPTIMISING IN THIS WAY THE POWER DISSIPATION.
Therefore, considering max. and min. R
rameters, I
–1) V
–2) V
= 25mA, and 2Rp = 100Ω, the battery voltage (V
LIM
= 25mA x (500+100) + 10V = - 25V
BAT
= 25mA x (100+100) + 10V = - 15V
BAT
values ranging from, 500, 100Ω, with a fixed pa-
loop
) will be almost equal to :
BAT
A proper current threshold (typ.9mA), programmable by external resistor RTH, allows the correct on/off hook transition function.
During the off-hook dynamic transition the CAC capacitor is charged and the line current regulator system, sensing the current flowing into RD, reduces the Iloop current to the programmed I
The settling time of the I
value, set by R
LIM
.
LIM
current is about 150ms and it is function of the CAC splitter ca-
LIM
pacitor (min. value allowed is 22µF).
,
3.3 VPOS CHARACTERISTICS
The input voltage V
out effect on the V
The STLC3055N can operate correctly when the V
can change slowly, within the data sheet range value (5.5V-12V), with-
POS
voltage.
BAT
voltage goes below the 5.5V (only in-
POS
stantaneous value, no steady-state), the only limitation is the minimum voltage required on the
external PMOS to keep it in a proper linear area.
Fast transients, ripple and spikes, on the supply voltage V
, will appear on TIP/RING, with
POS
a reduced amplitude, according to the voltage supply rejection of the device.
Bench measurements on SVRR give -35dB @ f = 50Hz, -47dB @ f = 4KHz using the test cir-
cuit configuration with the device in Active mode loaded with R
of 500Ω and I
loop
= 25mA.
LIM
3.4 START-UP AND DC-DC CONVERTER
In order to prevent problem during start-up, an internal circuit turns-on the gate of the Mosfet
only when V
For V
voltage higher than 4V the dc/dc converter power-on is controlled by a soft start cir-
POS
reaches 4V and turns it off for V
POS
lower than 3V.
POS
cuit embedded on the devices.
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AN2117 APPLICATION NOTE
Figure 4. DC-DC Converter Circuit
The dc\dc converter works in Buck-Boost configuration and its operation can be described as
a two step process.
Mosfet in turn-on condition :
energy from Vpos is stored in the inductor, diode reverse biased, load on V
powered by the
BAT
energy stored in the output capacitors CV.
Mosfet in turn-off condition :
energy stored in the inductor is delivered to the output capacitor and hence on the load, by the
diode forward biased.
An internal circuit controls the duty-cycle of the gate signal so that the output current of dc\dc
converter can be proportional to the load. When, for a short time, an higher power is required,
an enbedded circuit fix the max duty-cycle to about 95%.
The Rsense, in this case, guarantees the maximum value of the limited current.
3.5 INPUT CURRENT LIMITATION
The power supply, in the WLL applications, usually hasn't got high power current capability
so that, when a ring trip occurs, the status of the slic changes from Ring mode to off-hook condition and since the loop current control is not immediately working, the line current reaches
the output stages current limitation value that is about 80mA.
As a consequence, an high peak current is sunk from V
that could be higher of its maxi-
POS
mum current capability. In this case, if no limiting current circuit is used, (Rsense = 0), the
voltage would drop down.
V
POS
To prevent this type of problem, the STLC3055N incorporates a circuit on the V
iting the peak current, that is sunk from V
, to a value defined by the formula:
POS
I
peack
100m V
-------------------=
R
sense
This input current limitation circuit will be working, avoiding the overload problem on V
input lim-
POS
POS
,
during all the transient caused by changes of the line current conditions.
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3.6 VPOS CURRENT CAPABILITY
In the table below are summarized the value of the current drawn from V
supply vs R
POS
EN
@ 20Hz condition (For REN definition see section 3.9 below)
Table 3.
1REN (EUROP.) 3REN (EUROP.) 5REN (USA)
Vpos (V) Ivpos (mA Tot) Ivpos (mA Tot) Ivpos (mA Tot)
5.5 130 420 590
6.0 120 280 520
9.0 90 180 360
12.0 60 140 270
Of course when the power supply-voltage cannot feed the max. current, i.e. it hasn't got
enough current capability, the V
voltage will be affected.
POS
3.7 RSense SETTING
The RSENSE resistor set the input peak current value.
Of course, the input peak current value selected have to be lower than the power supply cur-
rent capability limit.
In typical application the input peak current is fixed to 900mApK (100mV / 110mΩ) in order
to guarantee a proper performances in the total range of the current loop (20-40mA) and the
Vpos supply (5.5-12V), driving up to 3REN of load.
If the device have to drive up to 5REN the value of R
, have to be reduced up to 100 -
SENSE
90 mΩ in order to increase the input peak current to 1 - 1.1Apk just to guarantee the correct
operation at low Vpos voltage condition (5.5V - 6V) using ringing frequency 20-25Hz .
If the device have to work with a limited input peak current of about 0.6Apk, setting the R
SENSE
resistor value in a range from 170-180mΩ, it is mandatory to use a Vpos voltage of 12V.
3.8 TRAPEZOIDAL RINGING SIGNAL
In the application domain targeted by our product ( Integrated Access Device, Set Top Box,
Small Office Home Office etc...) not sinusoidal ring waveform are accepted, for this reason,
the STLC3055N generates ringing signal with a trapezoidal waveform.
This type of waveform is very similar to a sinewave wose distortion can be kept lower than 5%
and Crest Factors value of 1.2, just properly selecting the external C
Because the value of C
is function of the ringing frequency, this value have to be adapted
REV
capacitor.
REV
to the ringing frequency used.
A C
of ringing frequency, increasing this one to 68Hz, the value of C
=18/22nF gives a proper trapezoidal ringing signal and a proper shaping with 20/25Hz
REV
should be choosen in a
REV
range 6.8nF/8.2nF
3.9 RINGER LOAD
In the typical application the STLC3055N can drive up to 3REN European standard (1REN =
1800Ω + 1µF), @ f = 20Hz, Crest Factor (VppK/Vrms) = 1.22 the level measured at Ringer
terminal are summarized in the following tables
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