ST AN2099 Application note

AN2099

APPLICATION NOTE

Guidelines for connecting via JTAG protocol to the STR71x microcontroller

INTRODUCTION

This application note provides guidelines on how to connect a Host debugger to a target STR71x board via a JTAG protocol converter, taking into account the internal features of the STR71x microcontroller product family.

This document is targeted for third party tool suppliers or application engineers interested in connecting to the STR71x using the JTAG connector. For basic references on the JTAG targeted for the ARM core, please refer to the ARM7TDMI Technical Reference manual

Figure 1. Hardware Setup Example

JTAG protocol converter	JTAG CONNECTOR
HOST PC
	POWER
STR71x BOARD	SUPPLY

Rev. 1

AN2099/0405

1/8

1

Guidelines for connecting via JTAG protocol to the STR71x microcontroller

1 OVERVIEW

One of the features of the STR71x is to allow the user to boot an application from internal RAM, which could be used for debugging purposes. However, that system configuration may potentially result in a hang-up when the debugger attempts to initiate the JTAG communication with the microcontroller. This could be caused by some random code in RAM that could set the STR71x in an unpredictable mode and prevent JTAG connection to the target.

Section 2 of this application note describes the inherent features of the STR71x affecting the JTAG connection. Section 3 presents a set of solutions for overcoming all the connection issues. Finally, Section 4, gives a detailed description of the JTAG connection sequence from the point of view of the JTAG protocol converter.

2 PARAMETERS AFFECTING JTAG CONNECTION

This section covers all the known parameters that affect the JTAG connection.

2.1 DELAY FOR FLASH INITIALIZATION

One aspect to be taken into account is the time for the internal STR71x flash initialization following a system reset. The flash initialization holds an internal signal controlling the ARM JTAG Reset pin in an undefined state for a deterministic amount of time. This is explained in detail in section 3.2.

2.2 RESET SIGNALS CONNECTED

Having both system reset and the JTAG reset connected to the same signal will prevent connection since the system reset has to be asserted during the JTAG communication protocol and released before the start of the application. Therefore having both pins tied to the same signal will prevent any JTAG communication with the embedded ICE registers.

2.3 PUTTING THE STR71x CPU IN HALT MODE

The Halt Mode of the STR71x CPU is used for debug purposes. This means that once debug state is initiated, the core is stopped and isolated from the rest of the system until the debugger restores the system state.

The STR71x can only switch to debug state by switching from the main CPU clock (MCLK) to the ARM JTAG clock (DCLK) controlled by the debugger. The STR71x CPU enters Halt mode on the next falling edge of MCLK after DBGRQ is asserted. Therefore MCLK has to be running internally to be able to connect via JTAG. For this reason, it is not possible to connect via JTAG when the STR71x is in WFI (Wait For Interrupt) mode or STOP mode.

2/8

Guidelines for connecting via JTAG protocol to the STR71x microcontroller

2.4 CONNECTION SEQUENCE FROM STANDBY MODE

When the core is in Standby, the core and peripherals are powered down, therefore a straight connection to the JTAG is not possible if the wakeup logic or system reset has not been triggered. To exit Standby, the wakeup sequence needs to be run to switch the main voltage regulator (which supplies the core and on-chip peripherals) back on to its nominal value. The wakeup procedure triggers a system reset sequence.

2.5 CONNECTION WHEN CODE IS EXECUTING FROM STR71x MEMORY

Attempting to connect while the STR71x is executing code from its memory is not recommended as this is not considered as a robust solution. For example, the target could have already executed the code to put the STR71x in Standby mode and therefore any subsequent attempt might fail.

3 CONNECTION METHODS

3.1 BOOT FROM FLASH, COPY TO RAM

One way to bypass the possibility of hitting a random instruction in RAM that might put the system in an undefined state is to boot an application from address 0x0 in Flash which then copies an image to internal RAM and executes from it. This will prevent any illegal or unwanted instruction being hit since the Flash is manufactured with known data contents, and this is also the case when a flash sector is erased. This eliminates the possibility of hitting a random code when the application is booted from internal RAM.

3.2 FLASH INITIALIZATION

As mentioned in Section 2, no JTAG connection to the target is possible during the Flash initialization phase, as described in Figure 2. The JTAG_EN signal is asserted and might reset the ARM TAP.

Taking into account the Flash initialization procedure, the JTAG connection sequence can not be initiated before phase 3 described in Figure 2.

3/8