ST AN2077 Application note

AN2077

APPLICATION NOTE

EEPROM Emulation with STR71x

INTRODUCTION

External EEPROMs are often used in applications to store data that may be later updated or adjusted. On the other hand, the microcontrollers used in these systems are based more and more on embedded Flash.

The trend to continuously reduce the number of components is forcing designers to look to use Flash memory to emulate EEPROM.

This application note explains the differences between external EEPROMs and embeddedFlash and gives advice on how to substitute external EEPROM to emulated-EEPROM using the on-chip Flash of STR71xF devices.

Although the concept is easy to explain and implement “as is”, there are some embedded aspects that have to be taken into account.

Substituting external EEPROM with emulated EEPROM from the embedded-Flash of the microcontroller is a complex development. This application note assumes that readers are already familiar with the techniques used to secure the content of evolutive information in external EEPROM of embedded applications.

This application note is organized in 4 parts:

–Description of the differences between external EEPROMs and embedded-Flash,

–General description of EEPROM emulation concept,

–Introduction to embedded application aspects,

–Software example.

Although this application note is mainly refers to STR710FZ1, STR710FZ2, STR711FR1, STR711FR2, STR712FR2 and STR712FR2, most of its content is not dependent on the microcontroller.

Rev. 2.0

AN2077/0705

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1

Table of Contents

INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 EMBEDDED FLASH AND EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 DIFFERENCE IN WRITE ACCESS TIME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 DIFFERENCE IN WRITING METHOD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.3 DIFFERENCE IN ERASE TIME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.4 ADDITIONAL INFORMATION ON FLASH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 EEPROM EMULATION CONCEPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 PRINCIPLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 PROGRAM/ERASE CYCLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.3 READ-WHILE-WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.4 FLASH ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.5 DATA-SET STATUS BITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.6 ACTIVE FLASH BANK SELECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3 EMBEDDED APPLICATION ASPECTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1 READING THE FLASH WHILE ERASING OR PROGRAMMING . . . . . . . . . . . . 8

3.1.1 Suspend and resume commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1.2 Minimum software to be copied into the on-chip RAM . . . . . . . . . . . . . . . . . . . . . . . . 9

3.2 DATA PROGRAMMING / ERASING WITH STR71XF . . . . . . . . . . . . . . . . . . . . 9

3.2.1 Flash field reprogramming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.3 FIELD REPROGRAMMING WITH STR71XF . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.3.1 Field events and Flash reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.3.2 List of Events and Suggested Handling Methods . . . . . . . . . . . . . . . . . . . . . . . . . . 10

4 SOFTWARE EXAMPLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.1 SOFTWARE EXAMPLE CONCEPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.2 SOFTWARE OUTPUT FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.2.1 EEPROM_Init . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.2.2 EEPROM_DataRead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.2.3 EEPROM_DataWrite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.3 EEPROM OUTPUT FUNCTIONS USE EXAMPLE . . . . . . . . . . . . . . . . . . . . . . 15 5 SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

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EEPROM Emulation with STR71x

1 EMBEDDED FLASH AND EEPROM

Before describing the proposed concept for EEPROM emulation, it is important to bear in mind the main differences between the embedded-Flash memory of a microcontroller and serial external EEPROMs. These differences apply to any microcontroller (i.e. not specific to STR71xF variants). They are summarized in the table below.

Table 1. Differences between Embedded Flash and EEPROM

	Feature	EEPROM	Emulated EEPROM from Embedded-
			Flash
		several ms
	Write time	random byte: 5 to 10ms	several µs
		page: equivalent to hundred µs / word (5 to	(ex: 16µs per word)
		10ms per page)
	Erase time	N/A	seconds
			(ex: 1.5s)
		once started, is not CPU-dependent;	once started, is CPU-dependent: a CPU
	Write method		reset will stop the write process even if
		needs only proper supply.	supply stays within specification.
		serial: hundred µs	parallel: hundred ns
	Write access	random word: 92µs
			a small number of CPU cycles per word.
		page: 22.5µs /byte

1.1 DIFFERENCE IN WRITE ACCESS TIME

As Flash has a shorter write access time, critical parameters can be stored faster in the emulated EEPROM than in a serial external EEPROM, thereby improving the robustness of the system if the same safety concept is kept.

1.2 DIFFERENCE IN WRITING METHOD

One of the important differences between external EEPROM and emulated EEPROM for embedded applications is the writing method.

–Stand-alone external EEPROM: once started by the CPU, the writing of a word cannot be interrupted by a CPU reset. Only supply failure will interrupt the writing process; so properly sizing the decoupling capacitors can secure the complete writing process inside a standalone EEPROM.

–Emulated EEPROM from an embedded-Flash: once started by the CPU, the writing can be interrupted by a power failure and by a CPU reset.

This difference should be analysed by system designers to understand the possible impact(s) on their applications and to define the proper handling method.

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EEPROM Emulation with STR71x

1.3 DIFFERENCE IN ERASE TIME

The difference in erase time is the other important difference between stand-alone EEPROMs and emulated EEPROM with embedded-Flash. Unlike Flash, EEPROM does not require a block erase operation to free-up space before write. This means that some form of software management is required to store data in Flash. Moreover, as the erase process of a block in the Flash takes few seconds, power shut-down and other spurious events that may interrupt the erase process (ex: reset) should be considered when designing the Flash management software. This means that to design a robust Flash management software it is necessary to have a deep understanding of the Flash erase process.

The Flash erase process is split in 3 phases:

–phase1: write all bits to 0, starting from the initial content. An interrupt during this phase will result in some memory cells being at “0” logic level and the rest of the memory cells will still contain their initial content.

–phase2: write all bits to 1, starting from the all “0” configuration. The longer the time before this phase is interrupted, the higher the number of cells will return a “1” logic level. The rest of the memory cells will contain their initial content, their content can be considered as totally random.

–phase3: equalization. This phase is necessary to recover over-erased cells. The Flash management software for EEPROM emulation should guarantee that this phase was successfully completed before programming in this bank.

The consequence of an interrupt during phase2 is that a single bit approach should be avoided to flag the completion of the erasing process (find more details in section 2.5 on page 6). The consequence of an interrupt during phase1 and/or phase2 is that it is recommended to have fixed data inside the emulated EEPROM so that a checksum can be run to tell which Flash bank keeps the valid data.

The most important point is to ensure that the Flash has been completely erased (phase3 was not interrupted) before programming data inside a bank.

Note The design of Flash software management is easier if programming in a new bank is always made just after erasing of this bank (when erasing of one bank is necessary).

1.4 ADDITIONAL INFORMATION ON FLASH

Incremental programming: the Flash controller will accept to program a word that is already programmed if the new word is adding more “0” bits.

Programming completion: programming completion is important to guarantee data retention time; the programming is complete when the Flash controller status indicates the end of programming without showing any error flag. If programming is interrupted (ex: supply fail, CPU reset), the cells of the word being programmed will be partially programmed. This can result in unstable “0”s when reading this word.

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EEPROM Emulation with STR71x

2 EEPROM EMULATION CONCEPT

2.1 PRINCIPLE

Different concepts are described in the literature. Each of them rely on partitioning a bank of the Flash into several Data-sets and on using control bits (per Flash bank and per Data-set) to compute which Flash bank and which Data-set is the valid one. For variable-length Data-sets, linked data-list structures should be considered.

The method described in this document is based on fixed-length Data-sets and 2 Flash banks.

Figure 1. Bank partitioning for emulated EEPOM

STR71x Flash Bank-x			STR71x Flash Bank-y
Data-set-n			Data-set-m

Area for Data-set storage

Data-set-2

Data-set-2

Status bits for

Data-set-1

Data-set-1

Data-set-n

Data-set-0

Data-set-0

n

m

Area for status bit storage

(Data-set bits and

Flash bank bits)

2

1

0

2

1

0

Switch between each bank (Erase one when using the other)

Variable update frequency

The variable update frequency may set high requirements on the program/erase cycle of the Flash and on the Flash features (ex: Read-While-Write). Those features are analysed in detail in the following pages.

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EEPROM Emulation with STR71x

2.2 PROGRAM/ERASE CYCLE

The requirement number of program/erase cycles is computed by dividing the needed number of erase cycles by the total number of Data-sets in the Flash banks (for example in Figure 1: n+m). When this number is still higher than the Flash write/erase endurance characteristics, a closer analysis is needed to understand when the Data-sets are updated:

–When Data-sets need to be updated during operation, it is proposed to use a buffer in RAM and to save the data before shutting-down the microcontroller.

–When Data-sets are updated only before a power-down sequence, it is proposed to increase the size of the Flash bank or to use a 3rd bank (see additional information in Section 3).

2.3 READ-WHILE-WRITE

Most currently available Flash technologies must complete a program or erase operation before code or data can be read from another memory block. There is a common misconception that EEPROM emulation can only be done when Read-While-Write functionality is implemented. Read-While-Write, when present, allows other memory blocks to be accessed during erasing and programming; this means that the CPU program does not need to be copied into RAM during programming/erasing. Read-While-Write does not prevent having a RAM buffer if access into the emulated-EEPROM is needed during programming.

When Read-While-Write is not supported, program or erase suspend command can be used to temporarily read code. All STR71xF variants support program and erase suspend commands.

2.4 FLASH ORGANIZATION

The concept described above shows the Flash bank split into 2 parts:

–Data-set storage: which keeps all variable information,

–Status bit storage: which keeps status of the Flash bank and of the Data-sets.

Other organizations are possible (ex: to include the Data-set status bits inside each Data-set) for which users may see advantages for their application.

2.5 DATA-SET STATUS BITS

Two status bits are proposed for each Data-set with the combinations shown in the following table.

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