ST AN2067 Application note

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APPLICATION NOTE

VIPower: DIMMABLE WHITE LEDS

POWER SUPPLY WITH VIPer53

In the same way that LED manufacturers succeed to realize blue LEDs, they now propose white LEDs inside a monolithic chip, or so called “singlechip white ” LED s . A current source is the mo re appropriate way to drive LEDs. For a maximum of flexibility, a large voltage range must be supported at the output due to the large threshold of these white LEDs, and the possible serial arrangement of them. Furthermore, if these LEDs h av e to be dimmable, they must be driven with a PWM (current generator). As a consequence, key features for this off-line power supply is a current generator, which can work as a Pulses Width M odulated mode, with a wide output voltage range, and must also suite any input voltage standard, and a galvanic isolation.

1. VIPer53 DESCRI PTION

VIPer53, the first multichip device of the VIPer family has been chosen to fulfill the requirements. It f eatures very l ow R a typical power of 35W in wide range in a standard DIP-8 package without a heatsink, answering the

of 1Ω allowing to deliver

dson

need for higher efficiency and reduced space thanks to a lower power dissipation.

1.1. General features

The block diagram is given on Figure 1. An adjustable oscillator is driving a current controlled PWM at a fixed switching frequency. The peak drain current is set for each cycle by the voltage present on the COMP pin. The useful range of the COMP pin extends from 0.5V to 4.5V, with a corresponding drain current range from 0A to 2A. This COMP pin can be either used as an input when working in secondary feedback configuration, or as an output when the internal error amplifier connected on the VDD pin is operating in primary feedback to regulate the VDD voltage to 15V. The VDD under voltage comparator drives a h igh voltage startup current source, which is switched off during the normal operation of the device. This feature together with the burst mode capability allows to reach very low level of input power in standby mode, when the converter is lightly loaded.

Table 1. White LEDs Power Supply Specification

Parameter Name Conditions Min Typ Max Unit

Output current I Output voltage V Output Power P Input Voltage V

OUT

= 20V 200 1000 mA

OUT

= 1A 5 40 V

OUT

40 W

82 265 V

Rev. 1

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Figure 1. VIPer 5 3 bl oc k diagram

ON/OFF

OVERTEMP.

DETECTOR

OSC DRAIN

OSCILLATOR

PWM

LATCH

R3 R4 R5

BLANKING TIME

SELECTION

COMP

CURRENT

AMPLIFIER

VDD

8.4/

11.5V

15V

18V

UVLO

COMPAR ATOR

ERROR

AMPLIFIER

OVERVOL TAGE

COMPAR ATOR

0.5V

4.35V

STANDBY

COMPAR ATOR

OVERLOAD

COMPAR ATOR

150/400ns BLANKING

4.5V

0.5V

PWM

COMPAR ATOR

125k

TOVL COMP SOURCE

converter, the output power is first limited by the

1.2. Overload protection

A threshold of 4.35V typical has been implemented on the COMP pin. This overload threshold is 150mV below the clamping voltage of

4.5V which corresponds to the current limitation of the device. In case of a COMP v oltage exc eedi ng the overload threshold, the pull up resistor on the TOVL pin is released and the external capacitor connected on this pin begins to charge. When reaching a value of 4V typical, the device stops switching and remains in this state until the VDD voltage reaches V

, or resumes normal

DDoff

operation if the COM P voltage returns t o a value below the overload threshold. The drain current that the device is able to deliver without triggering the overload threshold is called “current capability”, specified as I

in the data

Dmax

sheet. This value must be used to size correctly the converter versus its max imum output power. When an overload occurs on secondary side of the

current limitation of the device. If this overload is lasting for more than a time constant defined by a capacitor connected on the TOVL pin, the device is reset, and a new restarting sequence is initiated by turning on the startup current source. The capacitors on the VDD pin and on the TOVL pin will be defined together in order to insure a correct startup and a low res tart d uty cycle in ov erload or short circuit operation. Here are the typical corresponding formulas:

Where t

OVL

VDD

12.56–×10 tss⋅>



84×10



--------------------------





and D

---------------- 1–



RST

⋅

DD1tss

DDhyst

are respectively the time

RST

⋅

OVLIDDch2

-------------------------------------------⋅⋅>

DDhyst

needed for the output voltages to pass from 0V to

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AN2067 - APPLICAT ION NOTE

their nominal values at startup, and the restart duty cycle in overload or short circuit condition. A typical value of 10 % is generally set for this last parameter, as it insures that the output diodes and the transformer don’t overheat. The other parameters can be found in the data sheet of the device. As the VDD capacitor has to respect two condition s, the max imu m valu e will b e ret ained to define its value.

1.3. Stand-by operation

On the opposite load config uration, the converter is lightly loaded and the COMP voltage is decreasing until reaching the shutdown threshold at typically 0.5V. At this point, the switching is disabled and no more energy is passed on secondary side. So, the output voltage is decreasing and the regulation loop is rising again above the shutdown threshold, thus resuming the normal switching operation. A burst mode with pulse skipping is taking place, as long as the output power is below t he one corresponding to the minimum turn on of the device. As the COMP voltage is working around 0.5V, the peak drain current is very low (it is actually defined by the minimum turn on time of the d evice, and by the primary winding of the transformer) and no audible noise is generated. In addition, the minimum turn on time depends on the COMP voltage. Below 1V (V blanking time increases to 400ns, whereas it is 150ns for higher voltages. The minimum turn on time resulting from these values are respectively 600ns and 350ns, when taking into account the internal propagation time. This feature brings the following benefit:

• This brutal change induces an hysteresis between normal operation and burs t mode which is reached sooner when the output power is decreased.

• A short value in normal operation insures a good drain current control in case of short circuit on secondary side.

• A long value in standby operation reinforces the burst mode by skipping more switching cycles, thus decreasing switching losses. More details regarding the stan dby operation c an be found in the data sheet. See also the prac tical

COMPbl

), the

results obtained in the corresponding section of this document.

2. WHITE LEDS POWER SUPPLY

2.1. Schematic

The power topology is an off-line fly-back, working at a fixed frequency of 66KHz. The overall schematic is presented on Figure 2.

2.1.1. Primary section

On the left hand side of the schematic, there is the fuse F1, inrush current limiter CTN1, input filter T1, followed by the rectifier BR1 and its bulk capacitance C3. R4, C4 and D4 built the RCD clamper, for discharging the leakage inductance of the transformer. D2, R2 and C5 is the rectifier and filtering of the primary auxiliary winding, used in forward mode (refer to Section 3). This generates a voltage supply from 21 V up to 80 V, proportional to turns ratio between main primary winding and au xiliary primary winding, and versus input voltage range (110 V A serial voltage regulator is required to supply the VIPer 53 with the correct voltage (around 12 V). It is built with R14, DZ14, Q1 and C12. Notice that the V 80 V. This transistor may also dissipate 0.7 W when input voltage is 250 V The COMP pin filter is done using C8, R9 and C9.

2.1.2. Transformer

By definition, a current generator may have a large output voltage variation, according to the output load. Then, if auxiliary winding is used in fly-back mode, there could be a large voltage variation on auxiliary winding as it is proportional to the reflected voltage. So, it will be used in forward mode in order to limit the voltage variation for supplying the VIPer53. In order to guaranty the functionality even with low output voltage load, an auxiliary winding at secondary side has been added, instead using the main secondary output to supply the regulation loop and the voltage limitation (using the TSM 101). For similar reasons, this auxiliary winding will be also used in forward mode.

up to 250 VAC).

of this transistor must be higher than

CE0

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Figure 2. Current Generator Schem at i c

1A OUTPUT

J107

VREF INPUT

P101

1KA

2.2K

R103

R107

R131

2.2K

C131

10nF

R101

12K

0.25

R100

6.8K

R107

C113

22nF

C111

100nF

C110

10uF/63V

L101

10µH

C112

220uF/63V

D101

STTH302

R102

680

U2A

C114

100nF

PC817

R108

100K

R106

10K

3.3

R122

D122

BAS21

R109

345

Vref

VCC

GND

TSM101

U103

C121

22uF/40V

330

R105

U2B

PC817

C_YCAP

2.2nF/2KV

DRAIN

SOURCECOMP

BAS21

EBR44-600

47K/4W

1nF/250V

R14

3.3K/0.5W

VIPER53

TOVL

VDD

15V

OSC

C11

4.7nF

5.1K

2N5550

C12

22uF/25V

DZ14

12V/0.5W

470nF

6.8K

4.7nF

C10

100nF

100uF/400V

1uF/100V

BR1

1A/600V

100nF/400V

COMMON

MODE

0.5A

FILTER

100nF/400V

CTN1

AC INPUT

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2.1.3. Secondary section

On the right hand side of the schematic, the secondary winding is used in fly-back mode. D101, C112 are respec tively the rectifying di ode and its filtering. L101 and C110 bui ld another low pass filter.

The auxiliary sec ondary winding used in forw ard mode (refer to Section 3) in association with R122, D122 and C121 built the rectifier and filtering for the supply of the regulation loop, using a dedicated component (TSM101). This supply is independent from the load voltage.

TSM 101 has been design for voltage and current controller, which can be used for the control of a current generator, in association with a voltage limitation. It includes its own reference voltage (bandgap), and two operational amplifiers.

2.1.4. Current regulation loop

The output current is sensed through the shunt resistor R100. The shunt voltage is amplified using R101 and R107 in association with one OPamp of the TSM 101, building the error amplifier. The current target is set through the trimmer P101. R103 and P101 provide a fraction of the reference voltage provided by the TSM 101 (U103).

There is also another way to set the current target, using the connector J107 for dimming (see Section 2.2).

C113 with R107 is the integrator network of this amplifier, in order to cancel the static error of the regulation loop.

Then, the regulation loop continue with the opt ocoupler U2 (diode and transistor). This set the level of the COMP pin filter, which set the peak drain current VIPer53’s power cell (current control mode). Thus, the energy stored inside the transformer during each cycles is transferred on the secondary side, which supply the output current.

R131 and C131 is a phase lead net work in order to compensate the phase delay due to L101/C110 filter, for whole loop stability purpose.

2.2. Dimming

2.2.1. Dimming purpose

The main purpose of this application is to supply “single-chip white LEDs”, and to dim the brightness of these LEDs.

Because the white color is obtained from two peaks in the spectrum (a blue ray and a yellow ray), there is a dependency between the driving current and the white color spectrum.

2.2.2. Dimming in the application

This application do not propose any PW M and its oscillator circuitry, which can be easily found in dedicated literature. The way to proceed is to apply an external PWM signal on the node VREF_INPUT.

Provided that output impedance of the generator is not higher than 50 Ω, the input voltage is forced by the external generator instead of the DC reference voltage of the TSM 101.

The low level voltage of this PWM signal must be 0V, and high level voltage must be around 1 V.

Then, the peak current of the PWM generator can be set using the trimmer P101, a s in DC mode, from 0 up to 1 A.

The maximum frequency allowed is limited by dynamic behavior of the PWM current generator (refer to Section 2.2.4). The best way to use this power supply, is to set the lowest frequency convenient for human eye versus flicker. The highest the period, the highest the dimming range.

2.2.3. Audible noise

When using the power supply with a P WM signal, some audible noise may be heard, especially if the frequency of the external signal is inside the audible range.

This noise is emitted by the core of the transformer, and is a normal way to work. This noise is proportional to the output power transferred through it.

This noise can be reduced by optimiz ation of the transformer.

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