AN2050
APPLICATION NOTE
3-PHASE AUXILIARY POWER SUPPLY DESIGN BASED ON EMITTER SWITCHED BIPOLAR TRANSISTORS (ESBTS)
1. INTRODUCTION
This document presents the results of a 3-Phase auxiliary power supply designed with the UC3845 PWM driver and an ESBT, the new STC03DE170, as main switch. This work is supplemented by the release of a 45W dual output SMPS demo board, widely used as auxiliary power supply in 3-phase motor drive applications.
Moreover, the ESBT base driving circuit and some guidelines for the optimization of the power dissipation are given. The influence of parasitic capacitance on ESBTs is also described in detail. Furthermore, the slope compensation has been added in order to remove the oscillation during max input voltage and min load. Accordingly, the discussion in theory is presented. Finally, the realization methods of the output short circuit's protection function are provided.
Product(s)
2. DESIGN SPECIFICATIONS AND SCHEMATIC DIAGRAM
For a complete design reference of an auxiliary power supply using an ESBT you may refer also to the application note AN1889.
The table below lists the converter specification data and the main parameters fixed for the demo board.
Table 1: Converter Specification Data and Fixed Parameters |
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S ym bol |
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V alues |
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D escription |
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V inm in |
R ectified m inim um Input voltage |
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450 |
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V in |
R ectified m axim um Input voltage |
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850 |
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V out1 |
O utput v oltage 1 |
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15V/2A |
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V out2 |
O utput v oltage 2 |
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15V/1A |
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P out |
M axim um O utput P ower |
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45W |
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η |
Conv erter Efficiency |
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>75% |
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F |
Switching frequency |
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100 kH z |
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V fl |
R eflected fly back voltage |
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400 V |
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V s pik e |
M ax over voltage lim ited by clam ping circuit |
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200 V |
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October 2004 |
1/20 |
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AN2050 - APPLICATION NOTE
The power supply is based on a standard fly-back schematic including the RCD clamping network and the TL431 plus opto-coupler for the secondary side regulation. The relevant schematic is reported in figure 1.
Figure 1: Complete Schematic Diagram
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TR1 |
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Lp=2.4uH, Np=160, Ns=5, lg=0.68mm |
D |
D |
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D1 |
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R3 |
C3 |
DDV2 |
CV21 |
CV22 |
J3 |
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IN4007 |
82K/2W |
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1.5n/2KV |
STS20H100CT |
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C1 |
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680u/50V |
680u/50V |
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J1 |
F1 |
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150u/450V |
R4 |
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D3 |
BY269 |
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82K/2W |
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R1 |
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DDV1 |
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CV11 |
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CV12 |
J2 |
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D2 |
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220K/0.5W |
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D4 BY269 |
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1 |
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STS20H100T |
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1000u/50V |
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1000u/50V |
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IN4007 |
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C2 |
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C |
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150u/450V |
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D9 IN4148 |
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C |
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D8 |
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R5 |
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IN4148 |
12/0.5W |
C4 |
C5 |
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R2 |
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R6 |
47u/50V |
100u/50V |
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RF4 |
RF5 |
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220K/0.5W |
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1K/0.5W |
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810/0.5W |
1K/0.25W |
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Ccom |
10K/0.25W |
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CS |
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RG1 |
RS |
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U2 |
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RF2 |
RF3 |
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VREF |
PIC817 |
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10K/0.5W |
option |
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Rb1 |
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D7 |
BA159 TOR1 |
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R8 |
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56K0.5W |
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C4 |
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FB10K/0.25W |
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U3 |
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CF |
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1 |
0.1u/60V |
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0.1u/60V |
10/3 |
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TL431 |
8 |
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B |
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R7 |
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RF1 |
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2.6K/0.25W |
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Dz1 |
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Dz2 |
Dz3 |
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2K/0.5W |
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U1 |
UC3845 |
IN4148 |
IN4148 |
IN4148 |
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Q1 |
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Rb 0.56/0.5W |
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FB |
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VCC |
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22/0.5W |
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ESBT |
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Rcom |
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FB |
OUT |
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RG |
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10K/0.25W |
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COMP |
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VREF 8 |
VREF |
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Rcs |
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4 |
ISENSE |
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RT/CT |
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1K/0.25W |
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RT |
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470p/60V |
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10K/0.25W |
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471/60V |
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1.4/1W |
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A |
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1n/60V |
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Title |
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Size |
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B |
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Date: |
23-Jun-2004 |
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File: |
C:\Documents and Settings\songliu\My Documents\esbtDrawn.ddbBy: |
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3. MEASUREMENTS |
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PARAMETER |
Product(s)LOW LINE=160Vac |
NOMLINE=220Vac |
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HILINE=300Vac |
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SPEC.LIMIT |
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The board has a voltage doubler in the input stage to allow its testing with a standard main. The two |
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tables below report the efficiency measurement at full and minimum load. |
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Table 2: Full Load: 15V@2A, 15V@1A, Vin: 160Vac, 220Vac, 300Vac (with Voltage Doubler) |
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Obsolete |
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57.5 |
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57.7 |
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55.3 |
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I/P Power |
(W ) |
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O/P Power |
( W ) |
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45.5 |
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45.5 |
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45.5 |
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Efficiency |
( % ) |
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79.2% |
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79% |
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82.3% |
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75% |
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Table 3: Min Load: 15V@0.2A, 15V@0.1A Vin: 160Vac, 220Vac, 300Vac (with Voltage Doubler) |
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PARAMETER |
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LOW LINE=160Vac |
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NOMLINE=220V ac |
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HILINE =300Vac |
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SPEC.LIMIT |
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I/P Power |
(W ) |
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10.2 |
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9.8 |
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9.7 |
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O/P Power |
( W ) |
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4.6 |
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4.6 |
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4.6 |
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Efficiency |
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45% |
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47% |
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47% |
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2/20
AN2050 - APPLICATION NOTE
The main waveforms in steady state condition at full load are reported below. It is worth noticing the behavior of the base current with an initial high peak pulse needed to minimize the effect of the dynamic saturation voltage.
Figure 2: VinDC = 450V Full Load
Figure 3: VinDC 600V Full Load
Product(s)
Obsolete
3/20
®
AN2050 - APPLICATION NOTE
Figure 4: : VinDC = 850V Full Load
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Table 4: Measurement Results |
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Product(s) |
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Component |
Measured Temperature |
Power Dissipation |
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160 Vac |
68.7 |
4.37 W |
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the parasitic capacitance of the transformer, |
andObsoletethe output capacitance |
of the ESBT in parallel with the |
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ESBT |
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220 Vac |
78.9 |
5.39 W |
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300Vac |
62.1 |
3.71 W |
Major differences in power dissipation are mainly due to turn-on operation, and are strongly correlated to
heat-sink package parasitic capacitance. This-issue will be treated deeply in paragraph 5.
4. BASE DRIVINGProduct(s)CIRCUIT DESIGN
In practical applications, such as SMPS, where the load is variable, the collector current varies as well. As a consequence, it is very important to provide a base current to the device that is correlated to the
collector current in order to avoid the over saturation of the device at low load and to optimize its
Obsoleteperformance in terms of power dissipation. One common method to do this is the proportional driving method provided by a current transformer as shown in Figure 1. As already stated in the previous
chapter, it is recommended to provide a short current pulse to the base to make the turn-on as fast as possible and to reduce the dynamic saturation phenomenon. This pulse is achieved by using the capacitor and the zener diode in figure 5.
4/20
AN2050 - APPLICATION NOTE
Figure 5: Proportional Driving Schematic and its Equivalent Circuit
The current transformer turn ratio imposes a zone in the current characteristics with fixed IC/IB, its turn ratio has to be designed according to the characteristics of the chosen transistors and in particular to its gain. As an example, the STC03DE170 exhibits hfe=5 at IC=1.8A, VCE=5V, so that in order to ensure the right saturation level of the transistor at full load operations we can fix at first a turn ratio:
NP |
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Product(s) |
NS |
5 |
contrast each other, lead to a few iterative designObsoletesteps. The magnetic permeability of the core of the current transformer has to be as high as possible in order to minimize the magnetization current Im that is
A correct design of the current transformer has to take into consideration some constraints that, being in
a fraction of the primary current that flows in the core and is not transferred to the secondary side (see |
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figure 5b). On the other end, too high a permeability- |
core may lead to the saturation even with a very |
Product(s) |
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small magnetization current unless the number of primary turns as well as the size of the core is increased. On the contrary, by choosing a core with a very small magnetic permeability, it is possible to reduce the number of primary turns and the core size, but the consequent small permeability would not
ensure the necessary current on the secondary side because almost all of the primary current would be |
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used as magnetization current. Among some possible choices, a ferrite ring with 12.5mm diameter and |
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relative permeability in the range of 4500 ÷ 7000 has been selected. |
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Obsolete |
NTP = 2 V1 Tonmax |
Starting from the preliminarily fixed turn ratio (N=0.2), we must determine the minimum primary turns needed to avoid the core saturation. By applying the Faraday's law and imposing the maximum flux Bmax equals to Bsat/2:
Where, Bsat is the saturation flux of the core and depends on its magnetic permeability.
Looking at figure 5b the equivalent schematic diagram of the transformer has been modeled with its secondary closed with a voltage generator, whose value can be calculated doing some consideration on the circuit in fig. 5a. In fact, during the conduction time, the junction base-emitter of ESBT can be seen as a forward biased diode, to this we have to add the voltage drop on both diode D and resistor RB in series
5/20
®
AN2050 - APPLICATION NOTE
with the base of the ESBT (the Vdson of the mosfet can be neglected). In this way the voltage source at secondary side Vs is given by:
VS =VBEon +VD +VRB 2.5V
Since the magnetization inductance cannot be neglected, only IP, a fraction of the total collector current, will be transferred to the secondary. As a result, the magnetization current has to be firstly as low as possible. Meanwhile, the value of the magnetization inductance must be taken into account for the proper calculation of the transformer primary turns and turns ratio. The magnetization voltage drop, that is, the voltage at the primary of the current transformer, can be now easily calculated:
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N1T |
= 2.5 |
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= 0.5 [V ] |
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The magnetization current will be: |
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IM max = |
V1TON max |
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LTP |
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The number of primary turns should be increased if IMmax results relativelyProduct(s)high; obviously the core must |
have a window area large enough to hold both primary and secondary windings. Once both core material
and size are fixed, the turn ratio must be adjusted to get the desired IC/IB ratio according to the below |
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equation: |
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IObsoleteI −I |
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N |
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eff |
= |
P |
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C max M max |
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IC |
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IB |
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Next step is to selectProduct(s)the zener diode, the capacitor Cb and the resistor Rb. The turn-on performance of |
is the max magnetization current.
Particular care must be taken in order to ensure the insulation between primary and secondary sides since the voltage on the primary side during the off time can exceed 1500V.
Obsolete
ESBT is related to the initial base peak current and its duration tpeak that is approximately given by:
tpeak =3RbCb
A suitable value for Rb that gets rid of the ringing on the base current after the peak, and at the same time generates negligible power dissipation is 0.56Ω.
The tpeak value can be determined once the minimum on time is set upon the operating frequency. Bear in mind that in practical applications it should never be lower than 200ns. The value of Cb can be now
easily calculated since the values of tpeak and Rb were chosen.
The Ipeak amplitude must be limited in order to avoid an extra saturation of the device. This action is
6/20