ST AN2050 Application note

AN2050

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APPLICATION NOTE

3-PHASE AUXILIARY POWER SUPPLY DESIGN BASED ON

EMITTER SWITCHED BIPOLAR TRANSISTORS (ESBTS)

1. INTRODUCTION

This document presents the results of a 3-Phase auxiliary power supply designed with the UC3845 PWM driver and an ESBT, the new STC03DE170, as main switch. This work is supplemented by the release of a 45W dual output SMPS demo board, widely used as auxiliary power supply in 3-phase motor drive applications. Moreover, the ESBT base driving circuit and some guidelines for the optimization of the power dissipation are given. The influence of parasitic capacitance on ESBTs is also described in detail. Furthermore, the slope compensation has been added in order to remove the oscillation during max input voltage and min load. Accordingly, the discussion in theory is presented. Finally, the realization methods of the output short circuit's protection function are provided. For a complete design reference of an auxiliary power supply using an ESBT you may refer also to the application note AN1889.

2. DESIGN SPECIFICATIONS AND SCHEMATIC DIAGRAM

The table below lists the converter specification data and the main parameters fixed for the demo board.

Table 1: Converter Specification Data and Fixed Parameters

Symbol Description

Rectified minimum Input voltage 450

inm in

Vin Rectified maximum Input voltage 850

Output voltage 1 15V/2A

out1

Output voltage 2 15V/1A

out2

Maximum Output Power 45W

out

F Switching frequency ≅ 100 kHz

Vfl Reflected fly back voltage 400 V

Max over voltage limited by clamping circuit 200 V

spike

Converter Efficiency >75%

Values

October 2004

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The power supply is based on a standard fly-back schematic including the RCD clamping network and the TL431 plus opto-coupler for the secondary side regulation. The relevant schematic is reported in figure 1.

Figure 1: Complete Schematic Diagram

1 2

RF2

10K/0.5W

0.1u/60V

RF 3 option

RF 1 2K/0.5W

54321

TR1

1.5n/2KV

D7 BA159

D3 BY269

D4 BY269

TOR1

10/3

RG1

10K/0.25W

Lp=2.4uH, Np=160, Ns=5, lg=0.68mm

DDV2

STS20H100CT

DDV1 STS20H100T

12/0.5W

IN4148

1K/0.5W

ESBT

1.4/1W

CV21

680u/50V

D9 IN4148

C4 47u/50V

CV22

680u/50V

C5 100u/50V

1 2

1000u/50V

10K/0.25W

CV11

RF4

810/0.5W

U2 PIC817

VREF

2.6K/0.25W

TL431

Title

Number RevisionSize

Date: 23-Jun-2004 Sheet of File: C:\Documents and Settings\song liu\My Documents\esbt.ddbDrawn By:

CV12

1000u/50V

RF 5

1K/0.25W

IN400 7

3 2 1

IN400 7

Rb1

56K0.5W

U1 UC 3 8 4 5

VREF

CT 1n/60V

VCC

COMP

VREF

RT/CT

RT 10K/0.25W

Rco m

10K/0.25W

Cc o m

470p/60V

1 2 3 4 56

150u/450V

R1 220K/0.5W

C2 150u/450V

Dz1

IN414 8

OUT

ISENSE

82K/2W

Dz2 IN4148

220K/0.5W

Dz3

IN4148

Rc s

1K/0.25W

471/60V

0.1u/60V

0.56/0.5W

22/0.5W

3. MEASUREMENTS

The board has a voltage doubler in the input stage to allow its testing with a standard main. The two tables below report the efficiency measurement at full and minimum load.

Table 2: Full Load: 15V@2A, 15V@1A, Vin: 160Vac, 220Vac, 300Vac (with Voltage Doubler)

PARA METER LOW LINE=160Vac NO MLINE=220Vac HILINE =300Vac SPEC.LIMIT

I/P Power (W ) 57.5 57.7 55.3

O/P Power ( W ) 45.5 45.5 45.5

Efficiency ( % ) 79.2% 79% 82.3% 75%

Table 3: Min Load: 15V@0.2A, 15V@0.1A Vin: 160Vac, 220Vac, 300Vac (with Voltage Doubler)

PARAMETER LOWLINE=160Vac NOMLINE=220Vac HILINE=300Vac SPEC.LIMIT

I/P Power (W ) 10.2 9.8 9.7

O/P Power ( W ) 4.6 4.6 4.6

Efficiency ( % ) 45 % 47% 47%

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The main waveforms in steady state condition at full load are reported below. It is worth noticing the behavior of the base current with an initial high peak pulse needed to minimize the effect of the dynamic saturation voltage.

Figure 2: VinDC = 450V Full Load

Figure 3: VinDC 600V Full Load

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Figure 4: : VinDC = 850V Full Load

Table 4: Measurement Results

Power Dissipation

4.37 W

5.39 W

3.71 W

ESBT

Component Measured T emperature

160 Vac

220 Vac

300Vac

68.7

78.9

62.1

Major differences in power dissipation are mainly due to turn-on operation, and are strongly correlated to the parasitic capacitance of the transformer, and the output capacitance of the ESBT in parallel with the heat-sink package parasitic capacitance. This issue will be treated deeply in paragraph 5.

4. BASE DRIVING CIRCUIT DESIGN

In practical applications, such as SMPS, where the load is variable, the collector current varies as well. As a consequence, it is very important to provide a base current to the device that is correlated to the collector current in order to avoid the over saturation of the device at low load and to optimize its performance in terms of power dissipation. One common method to do this is the proportional driving method provided by a current transformer as shown in Figure 1. As already stated in the previous chapter, it is recommended to provide a short current pulse to the base to make the turn-on as fast as possible and to reduce the dynamic saturation phenomenon. This pulse is achieved by using the capacitor and the zener diode in figure 5.

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⋅

∆

Figure 5: Proportional Driving Schematic and its Equivalent Circuit

The current transformer turn ratio imposes a zone in the current characteristics with fixed IC/IB, its turn ratio has to be designed according to the characteristics of the chosen transistors and in particular to its gain. As an example, the STC03DE170 exhibits h

=5 at IC=1.8A, VCE=5V, so that in order to ensure the

right saturation level of the transistor at full load operations we can fix at first a turn ratio:

A correct design of the current transformer has to take into consideration some constraints that, being in contrast each other, lead to a few iterative design steps. The magnetic permeability of the core of the current transformer has to be as high as possible in order to minimize the magnetization current Im that is a fraction of the primary current that flows in the core and is not transferred to the secondary side (see figure 5b). On the other end, too high a permeability core may lead to the saturation even with a very small magnetization current unless the number of primary turns as well as the size of the core is increased. On the contrary, by choosing a core with a very small magnetic permeability, it is possible to reduce the number of primary turns and the core size, but the consequent small permeability would not ensure the necessary current on the secondary side because almost all of the primary current would be used as magnetization current. Among some possible choices, a ferrite ring with 12.5mm diameter and relative permeability in the range of 4500 ÷ 7000 has been selected. Starting from the preliminarily fixed turn ratio (N=0.2), we must determine the minimum primary turns needed to avoid the core saturation. By applying the Faraday's law and imposing the maximum flux Bmax equals to Bsat/2:

⋅⋅≅=

∆

TPeTPTP

=⇒

max1

sate

⋅

Where, Bsat is the saturation flux of the core and depends on its magnetic permeability. Looking at figure 5b the equivalent schematic diagram of the transformer has been modeled with its secondary closed with a voltage generator, whose value can be calculated doing some consideration on the circuit in fig. 5a. In fact, during the conduction time, the junction base-emitter of ESBT can be seen as a forward biased diode, to this we have to add the voltage drop on both diode D and resistor R

in series

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≅++

−

with the base of the ESBT (the Vdson of the mosfet can be neglected). In this way the voltage source at secondary side Vs is given by:

VVVVV

5.2

RBDBEonS

Since the magnetization inductance cannot be neglected, only I

, a fraction of the total collector current,

will be transferred to the secondary. As a result, the magnetization current has to be firstly as low as possible. Meanwhile, the value of the magnetization inductance must be taken into account for the proper calculation of the transformer primary turns and turns ratio. The magnetization voltage drop, that is, the voltage at the primary of the current transformer, can be now easily calculated:

5.2 5

[]

5.0

=⋅==

The magnetization current will be:

max1

results relatively high; obviously the core must

Mmax

max

The number of primary turns should be increased if I

have a window area large enough to hold both primary and secondary windings. Once both core material and size are fixed, the turn ratio must be adjusted to get the desired I

ratio according to the below

C/IB

equation:

eff

maxmaxCMC

where I

is the max magnetization current.

Mmax

Particular care must be taken in order to ensure the insulation between primary and secondary sides since the voltage on the primary side during the off time can exceed 1500V. Next step is to select the zener diode, the capacitor Cb and the resistor Rb. The turn-on performance of ESBT is related to the initial base peak current and its duration t

CRt 3

bbpeak

that is approximately given by:

peak

A suitable value for Rb that gets rid of the ringing on the base current after the peak, and at the same

time generates negligible power dissipation is 0.56 The t

in mind that in practical applications it should never be lower than 200ns. The value of C

easily calculated since the values of t

The I

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value can be determined once the minimum on time is set upon the operating frequency. Bear

peak

and Rb were chosen.

peak

amplitude must be limited in order to avoid an extra saturation of the device. This action is

peak

Ω.

can be now

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