ST AN2030 Application note

AN2030

APPLICATION NOTE

BACK EMF DETECTION

DURING PWM ON TIME BY ST7MC

INTRODUCTION

The direct back EMF sensing scheme used by ST72141 synchronously samples the motor back EMF during PWM “off” time without the need to sense or re-construct the motor neutral in a sensorless BLDC motor drive system. Since this direct back EMF sensing scheme requires minimum PWM “off” time to sample the back EMF signal, the duty cycle can't reach 100%. Also in some applications, i.e. HVAC using high inductance motors, we see the zero crossing detection is unsymmetrical in the ST72141 sensorless drive system at high speed. It is found that the long settling time of a parasitic resonant between the motor inductance and the parasitic capacitance of power devices causes false zero crossing detection of back EMF. This application note provides an analysis of the resonant transient during PWM “off” time. As a result, the back EMF detection during PWM “on” time is used in ST7MC to solve the problem.

AN2030

Rev 2

1/13

1

BACK EMF DETECTION DURING PWM ON TIME BY ST7MC

1 TRANSIENT ANALYSIS DURING PWM OFF TIME

Generally, a brushless dc motor is driven by a three-phase inverter with what is called six-step commutation. The conducting interval for each phase is 120° by electrical angle. Therefore, only two phases conduct current at any time, leaving the third phase floating. This opens a window to detect the back EMF in the floating winding.

For the direct back EMF sensing scheme, the PWM signal is applied on high side switches only, and the back EMF signal is synchronously sampled during the PWM off time. The low side switches are only switched to commutate the phases of the motor. The true back EMF can be detected during off time of PWM because the terminal voltage of the motor is directly proportional to the phase back EMF during this interval. Also, the back EMF information is referenced to ground, which eliminates the common mode noise; and the synchronous sampling rejects the high-frequency switching noise. Only three resistors are required to detect the back EMF, as shown in Figure 1.

Ideally, the terminal voltage for the floating phase is directly proportional to the back EMF signal in steady state during PWM off time [1]. The equation is as following:

v

 

=

3

(1)

a, b, c

--e

 

 

2

a, b, c

Where Vx is the terminal voltage, ex is the back EMF of the floating phase.

Figure 1. Direct Back EMF Sensing block diagram

MCIC

MCIB

MCIA

ST72141

MC00

MC01

MC02

MC03

MC04

MC05

Microcontroller

Back EMF Sensing

R1

R2

R3

motor

 

 

 

 

 

 

 

 

 

 

 

 

 

 

drive

 

Power stage

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Gate

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

The equation (1) is valid only in steady state.

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2

BACK EMF DETECTION DURING PWM ON TIME BY ST7MC

Considering the parasitic capacitance Coes in the switches, the voltage in the floating phase will have some transition time during PWM off time. Figure 2 shows the circuit where the PWM is applied to phases A and B while phase C is floating.

Figure 2. Phase C is floating

Vdc

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Coes

r

 

L

 

 

 

 

ea

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

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Vb

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Vn

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

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GND

We can simplify the circuit by using the neutral voltage Vn=1/2 * ec during PWM off time [1] and during PWM on time (see next chapter) to get the equivalent circuit in Figure 3.

Figure 3. Simplified equivalent circuit when phase C is floating

 

 

 

 

 

 

 

 

 

 

 

3

e

c

 

 

 

r

 

 

 

 

 

 

 

Vc

 

 

 

 

L 2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2*Coes

When PWM is on in phase A and B, the terminal voltage in steady state will be:

v

 

=

1

 

3

(2)

c

--v

dc

+ --e

 

 

2

2

c

which is the initial condition in the capacitor during PWM off time.

3/13

ST AN2030 Application note

BACK EMF DETECTION DURING PWM ON TIME BY ST7MC

Coes is not a fix value for IGBTs, which depends on the voltage. Figure 4 shows the curve for STGB7NB60HD.

Figure 4. Coes curve

Assuming the back EMF has just passed the rising edge of the zero crossing. When PWM is off, the voltage across the capacitor will be discharged in a resonant way. Figure 5 shows a terminal voltage and the current waveform.

Figure 5. Waveform of floating phase terminal voltage and inductor current

10m A/div

t0 t1 t1’ t2

At the time t0, PWM is off.

4/13

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