ST AN2021 APPLICATION NOTE

AN2021

Application note

Porting an application from the ST10F269 to the ST10F272B/E

Introduction

The ST10F272B and ST10F272E are members of the STMicroelectronics ST10 family of 16-bit single-chip CMOS microcontrollers. They are functionally upward compatible with the ST10F269.

The ST10F272B and the ST10F272E devices differ only in terms of XRAM memory size and XPeripherals. In this application note, the ST10F272B and ST10F272E will be referred to as ST10F272 for all aspects that are applicable to both products. For points specific to each product, the full name with the B or E extension will be used.

The goal of this document is to highlight the differences between ST10F269 and ST10F272 devices. It is intended for hardware or software designers who are adapting an existing application based on the ST10F269 to the ST10F272.

This document presents the ST10F272’s modified functionalities and the new ones, and goes on to describe the modified and the new registers. For each part, the differences with the ST10F269 that may have an impact when replacing the ST10F269 by the ST10F272 are stressed and some advice is given on the way they can be handled.

January 2007 Rev 2 1/39

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Contents AN2021

Contents

1 Modified features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.1.1 Pinout modification summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.1.2 Pin 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.1.3 Pin 56 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.1.4 Pin 99 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.1.5 Pins 143 and 144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.2 XRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.2.1 ST10F272B’s XRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.2.2 ST10F272E’s XRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

1.3 Flash EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

1.3.1 Hardware impact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

1.3.2 Software impact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

1.4 A/D converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

1.4.1 Hardware / Software impact: conversion timing control . . . . . . . . . . . . . 12

1.4.2 Hardware impact: electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 13

1.4.3 Software impact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

1.5 Real time clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

1.5.1 Hardware impact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

1.5.2 Software impact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

1.6 CAN modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

1.6.1 Hardware impact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

1.6.2 Software impact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

1.7 Port input control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

1.7.1 Hardware impact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

1.7.2 Software impact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

1.8 Ports output control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

1.8.1 Hardware impact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

1.8.2 Software impact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

1.9 PLL and main on-chip oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

1.9.1 Hardware impact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

1.9.2 Software impact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

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AN2021 Contents

2 New features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.1 Additional XPeripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.1.1 Hardware impact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.1.2 Software impact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.2 Programmable divider on CLKOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.2.1 Hardware impact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.2.2 Software impact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.3 New multiplexer for X-Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.3.1 Hardware impact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.3.2 Software impact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.4 Additional ports input control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

2.4.1 Hardware impact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

2.4.2 Software impact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3 Modified registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.1 XPERCON register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.1.1 Hardware impact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.1.2 Software impact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4 New registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4.1 XADRS3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4.1.1 Hardware impact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4.1.2 Software impact for the ST10F272B . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4.1.3 Software impact for the ST10F272E . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4.2 XPEREMU register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

4.2.1 Hardware impact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

4.2.2 Software impact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

4.3 Emulation-dedicated registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

4.3.1 Hardware impact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

4.3.2 Software impact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

4.4 XMISC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

4.4.1 Hardware impact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

4.4.2 Software impact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5.1 DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

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Contents AN2021

5.1.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5.1.2 Overview of the DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5.2 AC characteristics at 40 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

5.2.1 External memory bus timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

5.2.2 Hi-speed synchronous serial interface (SSC) . . . . . . . . . . . . . . . . . . . . 36

6 Referenced documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

4/39

AN2021 List of tables

List of tables

Table 1. Pinout modifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 2. Flash memory key characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 3. Flash memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 4. ST10F272 conversion timing table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 5. ST10F272 vs ST10F269 sample time comparison table . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 6. ADC differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 7. ADCON register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 8. XMISC register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 9. RTCCON register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 10. PICON register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 11. ST10F269 vs ST10F272 PLL ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 12. XCLKOUTDIV register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 13. X-Interrupt detailed mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 14. XPICON register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 15. XPERCON register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 16. XADRS3 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 17. Definition of address area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 18. XMISC register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 19. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 20. Multiplexed bus timings (ns) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 21. Demultiplexed bus timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 22. Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

5/39

List of figures AN2021

List of figures

Figure 1. ST10F272 clock generation diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 2. X-Interrupt basic structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6/39

AN2021 Modified features

1 Modified features

1.1 Pinout

1.1.1 Pinout modification summary

Ta bl e 1 summarizes the modifications made to the pinout.

Table 1. Pinout modifications

number

17 DC2

56 DC1

99 EA

143 V

144 V

ST10F269 ST10F272

Name Function Name Function

Internal voltage regulator decoupling.

Connect to nearest V capacitor.

Internal voltage regulator decoupling. Connect to nearest VSS via a 330nF capacitor.

Selects code execution out of internal Flash memory or external memory according to level during reset.

Ground pin XTAL3

5V power supply pin XTAL4

via a 330nF

EA-V

STBY

5V power supply pin

Internal voltage regulator decoupling. Connect to nearest V 10 - 100nF capacitor.

Selects code execution out of internal Flash memory or external memory according to level during reset. Power supply input for the standby mode.

Input to the 32 kHz oscillator amplifier circuit. When not used, must be tied to ground to avoid consumption. Additionally, bit OFF32 in RTCCON register must be set.

Output of the 32 kHz oscillator amplifier circuit. When not used, must be left open to avoid spurious consumption.

via a

1.1.2 Pin 17

On the ST10F269, a decoupling capacitor of 330nF minimum has to be connected between the pin 17 (named DC2) and the nearest V

This is no longer the case for the ST10F272 device where pin 17 is a V

Hardware impact

PCB must be adapted.

Software impact

None.

pin.

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Modified features AN2021

1.1.3 Pin 56

On the ST10F269, a decoupling capacitor of 330nF minimum has to be connected between the pin 56 (named DC1) and the nearest V

On the ST10F272, pin 56 is named V

and 100nF maximum must be connected between it and the nearest V

pin.

and a capacitor of value between 10nF minimum

pin.

Hardware impact

Change on the capacitor value. As the value is much lower, the footprint of the capacitor might be smaller and then a modification of the PCB is needed.

Software impact

None.

1.1.4 Pin 99

On the ST10F269, pin 99 is EA and used upon reset to select the start from the internal Flash memory or the external memory.

On the ST10F272, pin 99 has the additional function of providing the 5V power supply to the device in standby mode (new power-saving mode), it is called E

A-V

STBY

Hardware impact

The modification depends on the previous use of the ST10F269 and on whether the Standby mode is used or not.

For an application where the Standby mode is not used, no change to the PCB is required. If the new application uses the Standby mode, the EA common 5V and have a specific supply path.

Software impact

None.

1.1.5 Pins 143 and 144

These pins are VSS and VDD, respectively, in the ST10F269. On the ST10F272 they are used as XTAL3 and XTAL4 for connection to an optional 32 kHz crystal to clock the Real Time Clock during power-down.

Hardware impact

PCB must be redesigned.

If the optional 32 kHz is not used:

● Pin 143 (XTAL3) must be linked to ground like on the ST10F269

● Pin 144 (XTAL4) must be left open. It can also be connected to ground via a capacitor

to reduce the potential RF noise that might be propagated inside the device if the pin is left floating.

-V

pin must be separated from the

STBY

8/39

AN2021 Modified features

Software impact

In case the optional 32 kHz is not used, the OFF32 bit of the RTCCON register must be set. Prior to setting the OFF32 bit in the RTCCON register, the RTC must be enabled by setting RTCEN, bit 4 of XPERCON, and XPEN, bit 2 of SYSCON.

1.2 XRAM

The ST10F272B and ST10F272E devices do not have the same size of XRAM. Each configuration is detailed hereafter.

1.2.1 ST10F272B’s XRAM

The ST10F269 and the ST10F272B have the same size of extension XRAM: 10 Kbytes.

The XRAM of the ST10F269 is divided into two ranges being XRAM1 of 2 Kbytes and XRAM2 of 8 Kbytes:

● The XRAM1 address range is 00’E000h - 00’E7FFh if enabled (XPEN and XRAM1EN,

bit 2 of SYSCON register and of XPERCON register, respectively, must both be set).

● The XRAM2 address range is 00’C000h - 00’DFFFh if enabled (XPEN and XRAM2EN,

bit 2 of SYSCON register and bit 3 of XPERCON register, respectively, must both be set).

The XRAM of the ST10F272 is divided into two ranges, XRAM1 of 2 Kbytes (compatible with the ST10F269) and XRAM2 of 8 Kbytes with a user re-programmable address range and the StandBy mode.

● The XRAM1 address range is 00’E000h - 00’E7FFh if enabled (XPEN and XRAM1EN,

bit 2 of SYSCON register and bit 2 of XPERCON register must both be set).

● The XRAM2 address range is 09’0000h - 09’1FFFh, by default (mirrored every

16 Kbytes in the range 09’0000h -0F’FFFFh), if enabled (XPEN and XRAM2EN, bit 2 of SYSCON register and bit 3 of XPERCON register, must both be set).

Hardware impact

None.

Software impact

There is no change in the enabling of the XRAM blocks: XPERCON register bits, XRAM1EN and XRAM2EN, and SYSCON register bit, XPEN, are used to enable them.

The memory mapping of the application is impacted by the difference in XRAM2 location. A new register has been created in order to allow the user to remap XRAM2 (please refer to

Section 4.1: XADRS3 register on page 28 for details).

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Modified features AN2021

1.2.2 ST10F272E’s XRAM

The ST10F269 has 10 Kbytes of extension RAM whereas the ST10F272E has 18 Kbytes.

The XRAM of the ST10F269 is divided into two ranges being XRAM1 of 2 Kbytes and XRAM2 of 8 Kbytes:

● The XRAM1 address range is 00’E000h - 00’E7FFh if enabled.

● The XRAM2 address range is 00’C000h - 00’DFFFh if enabled.

The XRAM of the ST10F272E is divided into two ranges being XRAM1 of 2 Kbytes (compatible with the ST10F269) and XRAM2 of 16 Kbytes with a user reprogrammable address range:

● The XRAM1 address range is 00’E000h - 00’E7FFh if enabled (XPEN and XRAM1EN,

bit 2 of SYSCON register and bit 2 of XPERCON register, respectively, must be set).

● The XRAM2 address range is 09’0000h - 09’3FFFh, by default (mirrored every

16 Kbytes in the range 09’0000h -0F’FFFFh), if enabled (XPEN and XRAM2EN, bit 2 of SYSCON register and bit 3 of XPERCON register, respectively, must be set).

Hardware impact

None.

Software impact

There is no change in the enabling of the XRAM blocks: XPERCON register bits, XRAM1EN and XRAM2EN, and SYSCON register bit, XPEN, are used to enable them.

The memory mapping of the application is impacted by the difference in XRAM size and by the location of XRAM2. A new register has been created in order to allow the user to remap the XRAM2 (please refer to Section 4.1: XADRS3 register on page 28 for details).

1.3 Flash EEPROM

Table 2. Flash memory key characteristics

Characteristic ST10F269 ST10F272

Flash size 256 Kbytes 256 Kbytes

Flash organization 7 blocks 8 blocks

Programming voltage 5 volts 5 volts

Programming method Write/Erase Controller Write/Erase Controller

Program / Erase cycles 100000 cycles 100000 cycles

10/39

AN2021 Modified features

Table 3. Flash memory mapping

Segment ST10F269 Flash mapping ST10F272 Flash mapping

8 08’0000-08’FFFF External memory 08’0000-08’FFFF Flash registers

7..5 05’0000-07’FFFF External memory 05’0000-07’FFFF Reserved

4 04’0000-04’FFFF Block6: 64 Kbytes 04’0000-04’FFFF Block7: 64 Kbytes

3 03’0000-03’FFFF Block5: 64 Kbytes 03’0000-03’FFFF Block6: 64 Kbytes

2 02’0000-02’FFFF Block4: 64 Kbytes 02’0000-02’FFFF Block5: 64 Kbytes

01’8000-01’FFFF Block3: 32 Kbytes 01’8000-01’FFFF Block4: 32 Kbytes

01’0000-01’7FFF

00’8000 - 00’FFFF

00’6000 - 00’7FFF Block 2: 8 Kbytes 00’6000 - 00’7FFF Block3: 8 Kbytes

00’4000 - 00’5FFF Block 1: 8 Kbytes 00’4000 - 00’5FFF Block2: 8 Kbytes

00’0000 - 00’3FFF Block 0: 16 Kbytes

External memory or remap of Blocks 0-2

External memory Internal RAM and Registers

01’0000-01’7FFF

00’8000 - 00’FFFF

00’2000 - 00’3FFF Block1: 8 Kbytes

00’0000 - 00’1FFF Block0: 8 Kbytes

External memory or remap of Blocks 0-3

External memory Internal RAM and Registers

1.3.1 Hardware impact

None.

1.3.2 Software impact

As the first 32 Kbytes of Flash memory are now divided into four sectors of 8 Kbytes each in the ST10F272 whereas the ST10F269 had only three sectors, the mapping of the application is impacted.

Moreover, the Flash memory Write/Erase controller is different and therefore the programming routines must be updated.

When the bit ROMEN of the SYSCON register is set, that is, when the internal Flash memory is enabled, accesses to the address range 05’0000h - 07’FFFFh are not redirected to external memory. The linker-locator configuration of the toolchain should be checked in order to prevent any use of this memory range.

11/39

Modified features AN2021

1.4 A/D converter

In the ST10F272, the analog/digital converter has been redesigned (compared to the A/D converter in the ST10F269). The ST10F272 still provides an analog/digital converter with 10-bit resolution and an on-chip sample and hold circuit.

1.4.1 Hardware / Software impact: conversion timing control

The A/D converter in the ST10F272 is not fully compatible with that of the ST10F269 (timing and programming model).

In the ST10F269, the sample time (to charge the capacitors) and the conversion time are programmable and can be adjusted to the external circuitry. The total conversion time is compatible with the formula used for ST10F269, whereas the meanings of the ADCTC and ADSTC bit fields are no longer compatible.

Table 4. ST10F272 conversion timing table

ADCTC ADSTC Sample Comparison Extra Total conversion

00 00 TCL * 120 TCL * 240 TCL * 28 TCL * 388

00 01 TCL * 140 TCL * 280 TCL * 16 TCL * 436

00 10 TCL * 200 TCL * 280 TCL * 52 TCL * 532

00 11 TCL * 400 TCL * 280 TCL * 44 TCL * 724

11 00 TCL * 240 TCL * 120 TCL * 52 TCL * 772

11 01 TCL * 280 TCL * 560 TCL * 28 TCL * 868

11 10 TCL * 400 TCL * 560 TCL * 100 TCL * 1060

11 11 TCL * 800 TCL * 560 TCL * 52 TCL * 1444

10 00 TCL * 480 TCL * 960 TCL * 100 TCL * 1540

10 01 TCL * 560 TCL * 1120 TCL * 52 TCL * 1732

10 10 TCL * 800 TCL * 1120 TCL * 196 TCL * 2116

10 11 TCL * 1600 TCL * 1120 TCL * 164 TCL * 2884

The user should take care of the Sample time parameter: This is the time during which the capacitances of the converter are charged via the respective analog input pins. Ta bl e 5 shows the differences in sample time.

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