How it Works
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AN2014
APPLICATION NOTE
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ST AN2014 APPLICATION NOTE

AN2014
Application note
How a designer can make the most of STMicroelectronics Serial
EEPROMs
Introduction
Electrically erasable and programmable memory (EEPROM) devices are standard products, used for the non-volatile storage of parameters and fine-granularity data.
This document has been designed to give precisely this level of background understanding for one of those technologies: EEPROM, from STMicroelectronics. It describes how STMicroelectronics’ EEPROM is constructed, how it works, and gives useful guidelines for achieving high reliability applications under some of the most stringent conditions, such as those that are experienced in the automotive market.
March 2012 Doc ID 10701 Rev 8 1/69
www.st.com
Contents AN2014
Contents
1 EEPROM cell and memory array architecture . . . . . . . . . . . . . . . . . . . . 7
1.1 Floating gate operation within an EEPROM cell . . . . . . . . . . . . . . . . . . . . 7
1.1.1 Reading the value stored in a memory cell . . . . . . . . . . . . . . . . . . . . . . . 9
1.1.2 Writing a new value to the memory cell . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.1.3 Cycling limit of EEPROM cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.2 Electrical architecture of ST serial EEPROM arrays . . . . . . . . . . . . . . . . 14
1.2.1 Memory array architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.2.2 Decoding architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.2.3 Intrinsic electrical stress induced by programming . . . . . . . . . . . . . . . . 15
2 Choosing a suitable EEPROM for your application . . . . . . . . . . . . . . . 17
2.1 Choosing a memory type suited to the task to be performed . . . . . . . . . . 17
2.2 Choosing an appropriate memory interface . . . . . . . . . . . . . . . . . . . . . . . 17
2.3 Choosing an appropriate supply voltage and temperature range . . . . . . 18
3 Recommendations to improve EEPROM reliability . . . . . . . . . . . . . . . 19
3.1 Electrostatic discharges (ESD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1.1 What is ESD? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1.2 How to prevent ESD? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1.3 ST EEPROM ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2 Electrical overstress and latchup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.2.1 What are EOS and latchup? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.2.2 How to prevent EOS and latchup events . . . . . . . . . . . . . . . . . . . . . . . . 20
3.2.3 ST EEPROM latchup protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.3 Power supply considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.3.1 Power-up and power-on-reset sequence . . . . . . . . . . . . . . . . . . . . . . . . 22
3.3.2 Stabilized power supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.3.3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4 Hardware considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.1 I2C family (M24xxx devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.1.1 Chip enable (E0, E1, E2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.1.2 Serial data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.1.3 Serial clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2/69 Doc ID 10701 Rev 8
AN2014 Contents
4.1.4 Write control (WC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.1.5 Recommended I
2
C EEPROM connections . . . . . . . . . . . . . . . . . . . . . . 29
4.2 SPI family (M95xxx devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.2.1 Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.2.2 Write Protect (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.2.3 Serial Data input (D) and Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . 31
4.2.4 Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.2.5 Serial Data output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.2.6 Recommended SPI EEPROM connections . . . . . . . . . . . . . . . . . . . . . . 33
4.3 MICROWIRE® family (M93Cxxx and M93Sxxx devices) . . . . . . . . . . . . . 35
4.3.1 Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.3.2 Serial Data (D) and Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.3.3 Organization Select (ORG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.3.4 Serial Data output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.3.5 Don’t use (DU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.3.6 Recommended MICROWIRE EEPROM connections . . . . . . . . . . . . . . 37
4.4 PCB Layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.4.1 Cross coupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.4.2 Noise and disturbances on power supply lines . . . . . . . . . . . . . . . . . . . 38
5 Software considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.1 EEPROM electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.2 Optimal Write control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.2.1 Page mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.2.2 Data polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.3 Write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.3.1 Software write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.3.2 Hardware write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.4 Data integrity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
5.4.1 The checksum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
5.4.2 Data redundancy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
5.4.3 Checksum and data redundancy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
5.4.4 Extra redundancy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
5.5 Cycling endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5.5.1 Values specified in device datasheets . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5.5.2 Optimal cycling with ECC (error correction code) . . . . . . . . . . . . . . . . . 48
Doc ID 10701 Rev 8 3/69
Contents AN2014
5.5.3 Cycling and temperature dependence . . . . . . . . . . . . . . . . . . . . . . . . . . 50
5.5.4 Defining the application cycling strategy . . . . . . . . . . . . . . . . . . . . . . . . 51
5.5.5 Overall number of write cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6 Power supply loss and application reset . . . . . . . . . . . . . . . . . . . . . . . 53
6.1 Application reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6.1.1 I2C family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6.1.2 SPI family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.1.3 MICROWIRE family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
6.2 Power supply loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.2.1 Hardware recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.2.2 Supply voltage energy tank capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.2.3 Interruption of an EEPROM request . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6.3 Robust software and default operating mode . . . . . . . . . . . . . . . . . . . . . . 62
7 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
7.1 Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
7.2 Humidity and chemical vapors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
7.3 Mechanical stress . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
8 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
9 Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
4/69 Doc ID 10701 Rev 8
AN2014 List of tables
List of tables
Table 1. Three serial bus protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 2. ESD generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 3. Typical POR threshold values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 4. Connecting the Ei inputs of I²C products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 5. Calculation rules for pull-up resistor on SDA
Table 6. Connecting WC inputs in I2C products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 7. Calculation for external pull-up and pull-down resistors in SPI products . . . . . . . . . . . . . . 34
Table 8. Calculating external pull-up and pull-down resistors in MICROWIRE products . . . . . . . . . 37
Table 9. Column and page address bits according to page length. . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 10. Application cycling profile evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 11. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Doc ID 10701 Rev 8 5/69
List of figures AN2014
List of figures
Figure 1. Structure of an EEPROM floating gate transistor, and circuit symbol. . . . . . . . . . . . . . . . . . 7
Figure 2. MOSFET-like operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. Floating gate reservoir full of electrons (Erased state) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. Floating gate reservoir empty of electrons (Written state) . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 5. Using the voltage on the control gate to determine the charge on the floating gate. . . . . . . 9
Figure 6. During erase, electrons go through the tunnel oxide into the floating gate. . . . . . . . . . . . . 10
Figure 7. During write, electrons go through the tunnel oxide out of the floating gate . . . . . . . . . . . . 11
Figure 8. VPP signal applied to EEPROM cells
(HiV is the output of the charge pump) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 9. Accumulation of negative or positive charges in the tunnel oxide . . . . . . . . . . . . . . . . . . . 13
Figure 10. Architecture of the memory array (showing the grouping in bytes). . . . . . . . . . . . . . . . . . . 14
Figure 11. Decoding block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 12. Latchup mechanism and protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 13. Latchup test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 14. Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 15. Local EEPROM supply filtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 16. Chip Enable inputs E0, E1, E2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 17. Serial Data input/output SDA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 18. SDA bus conflict with push-pull buffers (NOT RECOMMENDED) . . . . . . . . . . . . . . . . . . . 26
Figure 19. Serial Clock input SCL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 20. Write Control input (WC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 21. Recommended I²C connections – safe design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 22. Recommended I²C connections – robust design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 23. Chip Select, Clock, Data, Hold input pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 24. Write Protect input W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 25. Output pin tri-state buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 26. Recommended SPI connections - safe design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 27. Recommended SPI connections - robust design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 28. Chip Select, Clock, Data input pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 29. Organization input ORG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 30. Recommended MICROWIRE connections - safe design . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 31. Recommended MICROWIRE connections - robust design . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 32. PCB decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 33. I
Figure 34. SPI data polling algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 35. MICROWIRE data polling algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 36. .Recommended use of the WC pin in I²C products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 37. Recommended use of the W pin in SPI products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 38. Example of how to duplicate data safely . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 39. Write cycling versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 40. I
Figure 41. SPI bus enters the high impedance state (Master reset) . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 42. MICROWIRE bus enters the high impedance state (Master reset) . . . . . . . . . . . . . . . . . . 56
Figure 43. EEPROM power backup capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 44. Emergency sequence I
Figure 45. Emergency sequence SPI products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 46. Emergency sequence MICROWIRE products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
2
C data polling algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2
C bus enters the high impedance state (Master reset) . . . . . . . . . . . . . . . . . . . . . . . . . . 54
2
C products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6/69 Doc ID 10701 Rev 8
AN2014 EEPROM cell and memory array architecture
AI10227
Tunnel Oxide
Control Gate
Floating Gate
Source
Drain
Gate Oxide
Oxide
Channel Region
Drain
Source
Control Gate Floating Gate
!)B
6
G
)
D
6
!
$RAIN
3OURCE
6
G
)
D

1 EEPROM cell and memory array architecture

1.1 Floating gate operation within an EEPROM cell

From the user’s point of view, this EEPROM device is a circuit for storing digital information.
To interface with the EEEPROM device a set of standard instructions are used. Behind this
simple interface, however, there are a number of sensitive analog and physical processes.

Figure 1. Structure of an EEPROM floating gate transistor, and circuit symbol

Figure 1. shows the key component of a single EEPROM cell, the floating gate transistor
(also known as a FLOTOX transistor). Figure 2. shows how it can be considered to be just
like any other type of MOSFET device. As the voltage, V
electrode, so the current flowing through the drain, I
, is increased on the Control Gate
g
, increases in proportion. For the
d
present, we can assume that this is a fairly linear relationship.

Figure 2. MOSFET-like operation

Figure 3 shows what happens if the Floating Gate can be made more negatively charged,
by filling it with extra electrons. This is used for the Erased state of the EEPROM cell.
Figure 4 shows what happens if the Floating Gate can be made less negatively charged, by
emptying it some of its normal electrons. This is used for the Written state of the EEPROM
cell.
Doc ID 10701 Rev 8 7/69
EEPROM cell and memory array architecture AN2014
AI10228
Tunnel Oxide
Control Gate
- - - - - - - - - - - - - - - -
Source
Drain
Gate Oxide
Oxide
V
g
V
g
I
d
- - - - - -
V
th.erase
Channel Region
AI10229
Tunnel Oxide
Control Gate
+ + + + + + + + + + + + +
Source
Drain
Gate Oxide
Oxide
V
g
V
g
I
d
+ + + + +
V
th.write
Channel Region

Figure 3. Floating gate reservoir full of electrons (Erased state)

1. Control Gate threshold value (V = f(Vg) characteristic shows Id=0 for Vg<V
2. I
d
th.erase
) is positive.
th.erase
.
The effect, as viewed from the channel region of the transistor, is that the Control Gate voltage, V
, is offset by an extra negative or positive amount. Viewed from the outside,
g
black-box electrical behavior of the device, the charge on the Floating Gate has the effect of moving the threshold MOSFET voltage, V
, at which the linear conduction region begins. In
th
other words, a FLOTOX transistor is a MOS transistor with a variable Control Gate threshold value, V
.
th
The Floating Gate acts as the storage element, and, being completely surrounded by insulating oxide, as shown in Figure 1, keeps its charge even when there is no power supply.

Figure 4. Floating gate reservoir empty of electrons (Written state)

1. Control Gate threshold value (V =f(Vg) characteristic shows Id=0 for Vg<V
2. I
d
8/69 Doc ID 10701 Rev 8
th.write
) is negative
th.write
.
AN2014 EEPROM cell and memory array architecture
AI10234
V
g
I
d
V
g.ref
I
d.ref
I

1.1.1 Reading the value stored in a memory cell

Figure 5 puts the three curves together, by way of comparison. It shows that for a given
Control Gate voltage, V higher or lower than that of the neutral device, depending on whether the reservoir of electrons on the Floating Gate has been filled up, or emptied. This, then, is the basis of how the memory cell can be read.
Figure 5. Using the voltage on the control gate to determine the charge on the
floating gate
, the current that flows through the drain, Id, will be detectably
g
1. A written cell draws a current IµA (where IµA > I
); an erased cell does not draw any current (0µA).
d.ref
In most of ST EEPROM products, a predetermined biasing condition on the Control Gate and the drain makes it possible to compare the current absorbed by the FLOTOX transistor with a reference. Basically, with the predetermined biasing condition an erased FLOTOX cell is not able to sink as much current as the reference (ideally the transistor is off). On the other hand, a written FLOTOX cell sinks a current that is superior to the reference (the transistor is on). By comparing to a reference current, the device is able to retrieve the stored information as a digital signal on the output pins of the memory device.
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AI10232
Vg=+18V
Vd=0V
Electric Field
Tunneling Electrons
Control Gate
Source
Drain
Gate Oxide
Oxide
Channel Region
Floating Gate
e
-

1.1.2 Writing a new value to the memory cell

The next question, of course, is how the charge can be changed on the Floating Gate, given that it is so well insulated by oxide, and keeps its charge even when there is no power supply. The answer is that the Tunnel Oxide, shown in Figure 1, is very thin, and can be used to transfer charge, when much higher voltages are applied than those normally used during Read operations.
Filling the Floating Gate reservoir with negative charges (electrons) is called erase. After erase, the FLOTOX transistor is in the Erased State (see Figure 3). Pulling out negative charges from the Floating Gate is called Program. After Program, the FLOTOX transistor is in the Written State (see Figure 4). One state is used to represent logic-0, and the other logic-1, but the exact choice is manufacturer and product-type dependent).
Both operations use the Fowler-Nordheim tunneling effect. For this, a high electric field (1 million V/mm, or more) is needed to make electrons pass through the thin Tunnel Oxide. For a Tunnel Oxide thickness of 100Å, the high voltage needs to be at least 10V. In fact, higher voltages, in the range 15 to 18V, are normally used, to reduce the time taken for the operation. Voltages higher than this cannot be used, since they would damage the thin Tunnel Oxide.
For erase, the cell Control Gate is made positive, and the source-drain region is grounded (as shown in Figure 6). The electric field makes electrons move from the substrate towards the Floating Gate, thereby filling the reservoir, and increasing the characteristic threshold voltage of the transistor (as shown in Figure 3).
Figure 6. During erase, electrons go through the tunnel oxide into the floating gate
1. Characteristic threshold Vth increases and becomes positive as shown in Figure 3
For write, the Control Gate is grounded and the source-drain region is made positive (as shown in Figure 7). The electric field is the opposite of that for erase, and so electrons move out from the Floating Gate, thereby emptying the reservoir, and decreasing the characteristic threshold voltage of the transistor (as shown in Figure 4).
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AI10233
Vg=0V
Vd=+18V
Electric Field
Tunneling Electrons
Control Gate
Source
Drain
Gate Oxide
Oxide
Channel Region
Floating Gate
e
-
Figure 7. During write, electrons go through the tunnel oxide out of the floating
gate
1. Characteristic threshold decreases and becomes negative as shown in Figure 4
Typically EEPROM erase/write cycles require a high voltage of about 15 to 18V for approximately 5ms. As EEPROM devices use a single supply voltage, the high voltage must be generated and managed internally. A set of analog circuits is available to generate and control the high voltage from the single external power supply:
● voltage and current references to control oscillators and timings
● a regulated charge pump that generates a stable 15 to 18V voltage, HiV, from the
single external power supply
● a ramp generator that, from the stable HiV voltage, makes the specific waveform
(shown in Figure 8) that is to be applied to the cells
V
is the high voltage that is directly applied to the FLOTOX cell, as described earlier. The
PP
precise shape of the V
voltage waveform is critical, and has a direct effect on the reliability
PP
and endurance of the memory cells. The slope, plate time and maximum level are parameters that are very carefully controlled.
Writing new data in an EEPROM array triggers an auto-erase of all the addressed bytes, resets them all to the Erased state, and then selectively programs those bits that should be set to the Written state.
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V
PP
5ms
t(ms)
HiV
18V
Auto-Erase
Program
Write Cycle = Auto-Erase + Program
Figure 8. VPP signal applied to EEPROM cells
(HiV is the output of the charge pump)
To summarize: Binary information is coded by means of a FLOTOX transistor. The Floating
Gate is a reservoir filled with negative electric charges that modify its electrical characteristics. The electric charges can be made to migrate into or out of the reservoir by applying a high voltage to a thin Tunnel Oxide. The binary information is read by comparing the cell (FLOTOX transistor) current to a reference.
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Control Gate
Source
Horizontal electric barrier disturbing erase and write
Oxide
- - + - - -
Channel Region
+
+
Vertical electric path leading to leakage
Gate Oxide
Floating Gate

1.1.3 Cycling limit of EEPROM cells

When a cell is cycled (repeatedly erased and programmed) two common phenomena occur and are amplified during the memory cell lifetime. When tunneling, negative charges can either be trapped in some imperfection of the oxide or damage the Tunnel Oxide:
1. Charge trapping
The accumulation of negative charges in the thin Tunnel Oxide creates an electric barrier in the Tunnel Oxide. The high voltage needed for the tunneling effect becomes even higher: programming high voltages are no more able to move enough charges to program the cell properly. The Erased and Written states become undifferentiated.
2. Stress on oxide
When the Tunnel Oxide deteriorates, a positive charge path may appear, that facilitates undesirable leakage through the Tunnel Oxide. The Floating Gate is no more 100% insulated, and loses its charges, and so the data retention time drops drastically.
Figure 9. Accumulation of negative or positive charges in the tunnel oxide
Charge trapping and oxide damage are accelerated at high temperatures. They are directly involved in cell cycling and endurance limitations.
Permanent digital information storage has to cope with physical phenomena and analog nonlinear behaviors that have natural limits and are sensitive to wear-out and improper use conditions.
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Cg-Line 0
8 Bit-Line Latches
Cg line
Bit line
Bit line
Bit line
8 Select
transistors
8 FLOTOX transistors
Row-
Line 0
b07 b06 b00
Cg-Line i
8 Bit-Line Latches
bi7 bi6 bi0
Control
Gate
transistor
Row-
Line n
AI10224b
Column 0 Column i
Byte
Select
transistor
FLOTOX transistor
Memory Cell

1.2 Electrical architecture of ST serial EEPROM arrays

In the previous section, the EEPROM functionality was considered at the single bit level. We will now zoom out of the memory cell to the full EEPROM array, in order to give an
overview of the architecture of an EEPROM device.

1.2.1 Memory array architecture

An EEPROM device is made of an array of memory cells whose organization allows byte granularity, the automatic erasing of the addressed bytes (Erased state), and the programming of only those bits that are to be changed to ‘1’ (Written state). The array (as shown in Figure 10) is organized as follows:
● Each memory cell consists of one Select transistor in series with a FLOTOX transistor
and each byte is made up of eight memory cells and a Control Gate transistor with a drain that is common to the control gates of all eight FLOTOX transistors.
● Rows (in the horizontal direction) are made up of 16 bytes (or more, depending on the
memory size (the number of bytes within each row being a function of the array size). For each row, all Select transistors and all Control Gate transistors are connected to the Row line.
● Columns are grouped by eight bit-lines and one Cg-line. This is then repeated as many
times as the number of bytes in a row.
● A bit-line is common to all the drains of the Select transistors of each memory cell in the
column. A Cg-line is common to all the sources of the Control Gate transistors of the column.
Figure 10. Architecture of the memory array (showing the grouping in bytes)
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Address Shift Register
Column
Decoder
Bit-line and Cg-line Latches: RAM Buffer
Row
Decoder
Array
Cg-lines and Bit-lines
Row-lines
Read/Write Analog
Voltages
Serial Input
MSB Address Bits LSB Address Bits

1.2.2 Decoding architecture

To address a single byte in a full array, decoding circuits are necessary. One logical address is associated with one byte location. The address bits are inserted serially into a Shift Register. Then, with parallel output, the decoding structures receive all of the bits at the same time, to perform the decoding and addressing. The row decoder decodes and brings correct biasing to a single row line. As one or more bytes of the same row can be programmed at the same time, the column decoder decodes one or more column(s), and a RAM buffer memorizes the data to write, and enables the right path for Cg-line and Bit-line biasing.
Figure 11. Decoding block diagram

1.2.3 Intrinsic electrical stress induced by programming

Whatever kind of data must be programmed and whether the request is made by byte or page, all high-voltage circuits are stressed by HiV (a high voltage ranging between 15 and 18V). In particular, the internal nodes of the charge pump can see voltages equal to HiV + V regulation, decoding, latches) are submitted to higher stress than active low voltage transistors. The overall time during which the high voltage circuits are active is relatively short compared to the product lifetime (10ms x 1Mcycles = 10000 seconds => less than 3 hours).
A standard ST EEPROM device has a few hundred high voltage transistors, for low memory density products (1Kbit). This number can rise to a few thousand for high memory density products (1Mbit).
Consider, by way of example, the stress induced on the array elements when programming one single byte in a 1Kbit EEPROM, organized as 128 x8 bit. The memory array is composed of 8 pages (or rows) of 16 bytes (or columns).
(that is as much as 23 V). All circuits that receive and carry HiV (ramp generator,
CC
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EEPROM cell and memory array architecture AN2014
Erase cycle: the complete row (page) that contains the addressed byte receives the VPP
signal, on the selected Row-line, as does the complete column, on the selected Cg-line:
● Control Gates of all the Select transistors in the given row: 1 row x 16 bytes x 8 bits
=128
● Control Gates of all the Control Gate transistors in the given row: 1 row x 16 bytes = 16
● Drains of all the Control Gate transistors that are connected to the given Cg-line: 1
column x 8 rows = 8 The Bit-lines of the addressed bytes are floating. Write cycle: the complete row (page) that contains the addressed byte receives the V
PP
signal, on the selected Row-line:
● Control Gates of all the Select transistors in the given row: 1 row x 16 bytes x 8 bits
=128
● Control Gates of all the Control Gate transistors in the given row: 1 row x 16 bytes = 16
● The Cg-line of the addressed byte is held at ground voltage
● The Bit-lines are left floating or receive V
case is when FFh is to be written, and all Bit-lines receive the V
● Drains of all the Select transistors sharing the same 8 Bit-lines: 1 column x 8 rows x 8
depending on data to be written. The worst
PP
PP
signal
bits = 64 This example shows how one single byte, being erased or programmed, incurs a lot of High
Voltage stress on elements that are on the same row, column and bit-line as the one addressed. For a 1Kbit EEPROM, programming one single byte to FFh induces stress on 128 Select transistors and 24 Control Gate transistors during auto-erase, and 192 Select transistors and 16 Control Gate transistors during the write cycle, even though only 17 transistors (8 Select transistors, 8 FLOTOX transistors, 1 MOS transistor) were really being addressed for the data change.
The bigger the memory array, the larger the number of additional transistors that are involved. This is why when high cycling performance is required, it is recommended to gather cycled data in contiguous blocks and use the write page mode as much as possible.
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2 Choosing a suitable EEPROM for your application

ST "Automotive Grade" EEPROM products are made to meet automotive’s stringent requirements. They are produced by a longstanding process and benefit from being tested continuously for quality as well as specific test strategies like Statistical Bin Limits, Parametric Average Testing and qualification following the AEC Q100, specific product buffer stocks, etc.
Nevertheless, the reliability on EEPROM products are also closely linked to the way they are designed in Applications.The aim of this part of the document is to provide our automotive customers with a set of practical recommendations for achieving immediate improvements in application reliability and robustness.
In the case of automotive applications, ST strongly recommends the use of products that are classified as automotive grade. These devices are designed to satisfy the most stringent requirements of automotive, sensitive and safety applications. "Grade 3" and Automotive Grade EEPROMs are tested with STMicroelectronics’ High Reliability Certified Flow (described in Quality Note, QNEE9801) insuring a very high level of quality.

2.1 Choosing a memory type suited to the task to be performed

EEPROM devices are particularly suited to the tasks of code traceability and parameter storage. The Serial protocol offers the best compromise of performance versus cost where the access time is not critical.

2.2 Choosing an appropriate memory interface

ST is specialized in Serial Access EEPROMs, which are based on three main protocols: I²C, SPI and MICROWIRE (see Ta bl e 1 ).
Fundamental requirements such as noise immunity, ESD, latchup and cycling Endurance are basic features of each ST Serial EEPROM device (independent from the protocol used).
The choice of the most appropriate Serial EEPROM depends mainly on the hardware resources of the master and on the architecture built around it. See the following:
● The I
● The SPI bus and MICROWIRE bus are 4-wire protocols allowing higher communication
Data Write protection is different for each protocol family and is also a key factor when selecting the memory interface. I and MICROWIRE products provide both hardware and software protection. Refer to
Section 5.3: Write protection.
2
C bus offers a 2-wire protocol working at a maximum clock rate of 400 kHz and so, is preferred when the hardware resources are limited and the data rate is not a constraint at all. The multiple slave configuration requires no extra hardware and is managed by software.
speed (speed is determined by each manufacturer design and technology). The number of slaves is unlimited but each slave requires an additional master resource for the chip select line. Both SPI and MICROWIRE can be used with only 3 wires providing that the D and Q pins are tied together to a bidirectional I/O.
2
C products offer only hardware Write protection while SPI
If none of the standard products exactly meets all the requirements to produce an Application Specific Memory (as described in AN1292), customizing is also possible.
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Table 1. Three serial bus protocols

I2C SPI MICROWIRE
®
ST Families M24Cxx, 1 Kb to 2 Mb M95xxx, 1 Kb to 2 Mb
Interface 2 wires: Single I/O line, clock
Clock Rate
(max)
Data
Management
Specific
Features
Page: 16 bytes to 256 bytes
Up to 8 devices cascadable
1 Mb/s Up to 20Mb/s 2 Mb/s
Byte
Global write control
on the same bus
4 wires: data in, data out,
clock & CS
Byte
Page: 16 bytes to 256 bytes
Hold mode (input pin)
Write control for 4 blocks
M93Cxx, 1 Kb to 16 Kb
M93Sxx, 1 Kb to 4 Kb
4 wires: data in, data
out, clock & CS
Byte or word
Page: 4 words
Block write protection
defined by software for
M93Sxxx family

2.3 Choosing an appropriate supply voltage and temperature range

These are essential parameters that will define the device reliability when operating in the application. The V within the limits defined in ST datasheets.
values and the temperature values of the application must always stay
CC
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3 Recommendations to improve EEPROM reliability

3.1 Electrostatic discharges (ESD)

ESD damage can happen any time during the product lifetime, from the moment it is delivered to the final field service operation. ESD damage can be destructive or latent. In the first case, a simple functional test can screen faulty devices; in the second case, the part is partially damaged and may be able to operate correctly, but its operating life may be drastically reduced, causing the device to fail prematurely in field service.

3.1.1 What is ESD?

Static Electricity results from the contact and separation of two bodies, which creates an unbalance in the number of electrons at the surface of the bodies. Practically, the bodies become charged to a specific electrical potential that depends on the material from which they are made (see Tab l e 2 ). An electrostatic discharge is defined as the transfer of charges between two bodies at different electrical potentials. It is instantaneous (a few nanoseconds) and thus induces high energy peaks which are very difficult to control and predict.

3.1.2 How to prevent ESD?

An ESD can be managed if the discharge is driven through a known and controlled path on the silicon die. Specific design rules and techniques can be used by designers to better protect against ESDs, such as Faraday shields, perimeter ground lines or ground planes.
In a production line, the part handling until the assembly line has to be carefully ESD­protected.
Table 2. ESD generation
ESD generation means Static voltage levels
Walking across a carpet 1 500 V to 35 000 V
Worker on a bench 100 V to 6 000 V
Chair with Urethane Foam 1 500 V to 18 000 V
1. The charge unbalance depends on many factors such as the contact area, separation speed and relative
humidity.
(1)

3.1.3 ST EEPROM ESD protection

ST EEPROM devices offer a specific protection circuit against Human Body Model ESDs of up to at least 3000 V in non-operating mode (in accordance with AEC-Q100-002).
During write operations, the EEPROM is much more sensitive to ESDs because of the architecture of its internal high voltage generator. Applications exposed to ESD should avoid writing data in the EEPROM when an ESD is more likely to occur.
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3.2 Electrical overstress and latchup

Electrical overstress (EOS) and latchup are also damaging stresses that are either immediately destructive, or may create latent defects leading to premature failure.

3.2.1 What are EOS and latchup?

In comparison with ESDs, EOS and latchup are lower-intensity events that last much longer (sometimes more than a few seconds). That is why the energy induced by an EOS is higher than the ESD energy. EOS and latchup induce current injections inside the EEPROM when an overvoltage stress is applied on one or more package pins. Latchup occurs when a charge injection triggers the I/O parasitic thyristors (also called SCR) thus generating a very high current between V turned off.

3.2.2 How to prevent EOS and latchup events

Typically power supply cycling leads to EOS situations. During the power-up and power­down phases, the EEPROM I/Os interfaced with other ICs may temporary see voltages greater than V biasing conditions may lead to positive and negative current injections, respectively. This kind of stress cannot always be completely prevented but it can be minimized. The switching sequence of the different interfaced ICs must be carefully determined, and if necessary protection resistor (<1K (<50
Ω) to limit eventual latchup current. Please refer to Section 4: Hardware considerations
for more details.
or lower than VSS. When outside Absolute Maximum Ratings, these
CC
and VSS. This phenomenon lasts until the VCC power supply is
DD
Ω) can be placed on critical pins or sometimes directly on V
CC
pin
Overshoots and undershoots may occur on external device pins when the application is running. They can be generated by radiations, power supply disturbances or even some ICs. The very first protection is provided by the semiconductor manufacturer (ST) which offers the best possible robustness against EOS and latchup. If extra protection is needed, the application designer can add small value resistors (<1kΩ) in series on all interfaced lines
and (<50Ohm) in series on VCC line so that it can be compatible with the communication speed
constraints and power supply range. Please refer to the Hardware considerations section for more details.
Manufacturing and handling devices are also sources of EOS: all voltage levels applied to the device must be checked accurately and regularly. In addition all equipment should be constantly calibrated.
During write operations, an EEPROM device is more sensitive to overvoltages on its power supply pin because the internal high voltage generator is directly fed by the voltage applied to the power supply pin.
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Ai11084b
SCR is switched on by an external
stress coming from an I/O pin.
5V
V
CC
V
SS
Latch up risk minimized
R
P
<50Ω
RP<1KΩ
SRC
5V
V
SS
V
CC
I/O
EEPROM
I or V stress
SRC
I/O
High current(often destructive)
Fail
ai10858
Fail
Current Injection
100mA
−100mA
Good = Class A
Good = Class A
−0.5 x V
CC
max
1.5 x V
CC
max
Overvoltage
Figure 12. Latchup mechanism and protection
1. Protection is only recommended if latchup risk is identified.

3.2.3 ST EEPROM latchup protection

During the qualification process, samples from three different lots are tested for voltage overshoots (positive and negative injections). Figure 13 shows the levels of stress applied to the tested devices.
Figure 13. Latchup test conditions
1. The device does not latch up within the gray areas.
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