ST AN1994 APPLICATION NOTE

AN1994

APPLICATION NOTE

STA50X DIGITAL POWER FAMILY

This applicationnote is related to the STA50X series of DDX high efficiency output stages.

1 PIN DESCRIPTION

Table 1. STA500, STA505, STA506, STA508

Pin N’ Pin Name Description

1 GND_sub Substrate ground

2 OUT2B Output Half Bridge 2B

3 OUT2B Output Half Bridge 2B

4 Vcc 2B Positive Supply

5 GND2B Negative Supply (GND)

6 GND2A Negative Supply (GND)

7 Vcc 2A Positive Supply

8 OUT2A Output Half Bridge 2A

9 OUT2A Output Half Bridge 2A

10 OUT1B Output Half Bridge 1B

11 OUT1B Output Half Bridge 1B

12 Vcc 1B Positive Supply

13 GND1B Negative Supply (GND)

14 GND1A Negative Supply (GND)

15 Vcc 1A Positive Supply

16 OUT1A Output Half Bridge 1A

17 OUT1A Output Half Bridge 1A

18 n.c. Not Connected

19 GND_Clean Logical Ground

20 GND_Reg Ground for regulator Vdd

21 Vdd 5V Regulator referred to Ground

22 Vdd 5V Regulator referred to Ground

23 VL(called in previous docs Ibias) Logic reference voltage

AN1994/0506

Rev. 2

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AN1994 APPLICATION NOTE

24 CONFIG Configuration Pin

25 PWRDN Stand-by pin

26 TRISTATE HI-Impedance pin

27 FAULT Fault pin advisor

28 TH_WAR Thermal Warning Advisor

29 IN1A Input Half Bridge 1B

30 IN1B Input Half Bridge 1B

31 IN2A Input Half Bridge 1B

32 IN2B Input Half Bridge 1B

33 Vss 5V Regulator referred to +Vcc

34 Vss 5V Regulator referred to +Vcc

35 VccSign Signal Positive Supply

36 VccSign Signal Positive Supply

Table 2. STA501A, STA502A, STA503A

Pin N’ Pin Description Pin N’ Pin Description

1 GND_sub 19 GND_Clean

2 OUTB 20 GND_Reg

3OUTB 21 Vdd

4 VccB 22 Vdd

5GNDB 23 VL

6GNDB 24 n.c.

7n.c. 25PWRDN

8OUTA 26TRISTATE

9OUTA 27FAULT

10 n.c. 28 TH_WAR

11 n.c. 29 n.c.

12 VccA 30 n.c.

13 GNDA 31 INA

14 GNDA 32 INB

15 n.c. 33 Vss

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16 n.c. 34 Vss

17 n.c. 35 VccSign

18 n.c. 36 VccSign

Table 3. STA501, STA502, STA503

Pin N’ Pin Description Pin N’ Pin Description

1 GND_sub 19 GND_Clean

2 OUTB 20 GND_Reg

3OUTB 21 Vdd

4 Vcc 22 Vdd

5GNDB 23 VL

6GNDA 24CONFIG

7 Vcc 25 PWRDN

8OUTA 26TRISTATE

9OUTA 27FAULT

10 n.c. 28 TH_WAR

11 n.c. 29 GND

12 Vcc 30 GND

AN1994 APPLICATION NOTE

13 GND 31 INA

14 GND 32 INB

15 Vcc 33 Vss

16 n.c. 34 Vss

17 n.c. 35 VccSign

18 n.c. 36 VccSign

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AN1994 APPLICATION NOTE

2 CONTROL PINS

Table 4.

Pin Name IC-Status Logic Value Notes

TH WAR

FAU LT

TRI-STATE Normal operation 1

PWRDN Normal operation 1

CONFIG Normal operation 0

Normal operation 1 Open collector.

IC temperature = 130°C 0

Normal operation 1 Open collector.

Fault detected (Short
circuit, Thermal…)

All powers in Hi-Z state 0

Low absorption 0

OUT1A=OUT1B;
OUT2A=OUT2B
(If IN1A=IN1B; IN2A=IN2B)

0

1 CONFIG=1 means connect Pin 24 (Config) to

To have high logic value is necessary a pull-up
resistor

To have high logic value is necessary a pull-up
resistor

pins 21, 22 (Vdd)

2.1 INPUT CONTROL PINS

■ PWRDN: pin 25

■ TRI-STATE: pin 26

■ CONFIG: pin 24

Input control pins (PWRDN and TRI-STATE) are connected to the high impedance input of a
CMOS Schmitt trigger.

The PWRDN pin is also connected through an high value (100 KOhm) pull-down resistor to
GND (specified 35/uA@V_pwrdn=3.3V)

The TRISTATE pin has not pull down.

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Figure 1. Figure VL threshold

3.5

3

AN1994 APPLICATION NOTE

Vin with VL = 3.3V

2.5

2

Turn-ON

Vin

1.5

1

0.5

0

The Schmitt triggers thresholds are, for both pins in the range of 1.5V at TURN ON (V

1.3 at TURN OFF (V

), when VL=3.3.V (are VL dependent). Than the hysteresis interval is well

L

inside the standard logic interval for inputs specified in the datasheet (0.8 - 1.7V@V
different V

see table under note 1).

L

Turn- OFF

) and

H

=3.3V; for

L

The CONFIG pin in stereo configuration, should be connected to digital GND, but as general
remark, should be noted that all the GND's on the recommended layout, are connected togeth­er by a wide GND plane.

2.2 OUTPUT CONTROL PINS

■ FAULT: pin 27

■ TH_WAR: pin 28

Outputs control pins (FAULT and TH_WAR) are open drains pin; they need an external pull­up resistor.

2.2.1 FAULT

The FAULT is activated when one of the following conditions occur:
UNDERVOLTAGE: power supply Vcc < 7V (typ.)
OVERTEMPERATURE: junction temperature Tj > 150'C (typ)
LOGIC UNDERVOLTAGE: Logic supply V

< 0.9V

L

OVERCURRENT: Output current

STA500 Iout > Isc = 3.5A(min) - 5 A (typ)
STA501 Iout > Isc = 3.5A(min) - 6 A (typ)
STA502 Iout > Isc = 4A(min) - 6 A (typ)
STA503 Iout > Isc = 4.5A(min) - 6 A (typ)
STA505 Iout > Isc = 3.5A(min) - 6 A (typ)
STA506 Iout > Isc = 4A(min) - 6 A (typ)
STA508 Iout > Isc = 4.5A(min) - 6 A (typ)

OVERVOLTAGE:

in STA50x the circuitry is present but the threshold is intentionally set at a
value higher than the absolute maximum rating (40V), so STA50x is not over-voltage protect­ed.

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AN1994 APPLICATION NOTE

The absolute maximum rating that must not be exceeded (even during commutation spikes)
is 40V: above this value the device could be damaged.

UNDERVOLTAGE:
OVERTEMPERATURE:

teresis (fast oscillations are prevented by the turn on delay). The threshold for FAULT and
TH_WAR are in tracking.

OVERCURRENT:
normal operation the peak value through the load must be less than the overcurrent limit.

An internal delay of about 200nsec prevents the current limiter intervention for current spikes
occurring during normal operation. The device is not protected against the direct short on the
pin before the inductor. It is important that the selected inductor doesn't saturate for the rated
specified current.

2.2.2 THERMAL WARNING

The Thermal Warning pin is activated low (open-drain MOSFET) when the IC junction temper­ature exceeds 130°C.

This allows acting on the input signal in order to decrease the dissipated power. This avoids
the fault intervention (150°C).

the typical is activated threshold is 7V.

the threshold junction temperature is 150°C (±10°C), there is no hys-

the minimum overcurrent value for all IC is shown in the previous table. For

3 POWER SUPPLIES PINS

3.1 GND_SUB

This pin is connected to the substrate of the IC and to the slug

3.2 GND_Clean

This pin is the reference GND for all input logic signals, so it must be as clean as possible.
Is recommended not connect directly this GND with other GNDs (i.e. speaker GND) that are

interested by voltage spikes.

3.3 GND_Reg

This pin is necessary to filter an internal reference voltage (Vdd); it should be connected via a
capacitor to Vdd.

3.4 GND1A - GND1B - GND2A - GND2B

These pins are power grounds interested by high currents generating spikes.
In order to improve EMI and the other problems as false commutations or disturbances is

strongly recommended to connect them to a GND plane star routed to the input electrolytic ca­pacitors.

When the slug down package is used (STA500), the GND plane connected to these pins and
to the slug must be carefully dimensioned in order to dissipate the generating heating.

3.5 Vcc1A - Vcc1B - Vcc2A - Vcc2B

These power pins must be externally filtered via capacitors placed as close as possible.
This to avoid that the high voltage spikes externally generated could affect the operation and

the reliability.

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AN1994 APPLICATION NOTE

3.6 VL (2.7V < VL < 5.5V)

pin must be connected to the logic supply of the modulator in order to guarantee the correct

V

L

the logic thresholds.
To V

are connected:

L

– Resistive dividers (the other side connected to GND_Clean) to fix the threshold of logic

inputs (IN1A, IN1B, IN2A, IN2B) see datasheet High/Low level input voltage = (V

L

/2)

±300mV;

– Supply of input Schmitt triggers for control inputs PWRDN and TRISTATE as in table in

Note1.

– The logic circuits inside the STA50x are powered from Vdd (internally generated from the

power supply Vcc and externally filtered by C58)

3.7 Vdd

These pins (pin 21 and 22) are internally connected to a voltage reference 5V referred to GND.
These pins require a bypass capacitor.

3.8 VccSign

These pins (pin 35 and 36) are signal positive supply.

3.9 Vss

These pins (pin 33 and 34) are internally connected to a voltage reference 5V referred to Vcc.
These pins require a bypass capacitor.

4 INPUT AND OUTPUT PINS

4.1 IN1A, IN1B, IN2A, IN2B

There are four input pins, one for each half bridge (IN1A - 29, IN1B - 30, IN2A - 31, IN2B - 32).
They are high impedance logic inputs, without any pull-up or pull-down resistors. If unused
they MUST be connected either to GND-Clean (pin 19) or to the logic supply V

Each input pin is connected to the input of a comparator (gate of a PMOS differential pair), with
the second input (reference) tied to the central tap of a divider (10KΩ + 10KΩ) connected be­tween the pin V

/2) is provided. Each comparator provides also a small hysteresis.

(V

L

and GND-Clean. So the logic threshold equals to half logic supply voltage

L

The input pins are ESD protected via an internal diodes network.

4.2 OUT1A, OUT1B, OUT2A, OUT2B

There are 8 pins (4 pins for STA501A, STA502A and STA503A) used for output signals.
These pins carry the high voltage PWM signal that once filtered (via the low pass Butterworth)

can be applied to the speakers.
A snubber RC network must be connected as close as possible to the pins in order to improve

EMI performances that could be affected by the ringing generated in the PWM waveform.

(pin 23).

L

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AN1994 APPLICATION NOTE

5VL AND VCC POWER ON SEQUENCE

Figure 2. TURN ON SEQUENCE

Vcc

V

∆V(*)

3.3V

VL
Vcc
Pwdn

time

(*) It is advisable that ∆V>5V

If the sequence turns on V
could flow through the ESD protection diode from V

before Vcc (how shown in next figure) an uncontrolled current

L

(logic supply) to Vcc (high power supply).

L

That can cause:

a) Damage the ESD diode;
b) Switch on some parasitic latch that sustains itself also when both supplies are growing to the

steady value;

Figure 3. WRONG TURN ON SEQUENCE

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In this time VL>Vcc

Vcc

V

3.3V

time

VL
Vcc
Pwdn