ST AN1978 APPLICATION NOTE

AN1978

APPLICATION NOTE

ST8004: SMART CARD INTERFACE

1. INTRODUCTION

The ST8004 is a smart card interface designed to minimize the microprocessor hardware and software complexity in all the applications that need a smart card, such as Set-Top-Boxes, electronic payments, pay TV and identification. The ST8004 is compliant with the NDS requirements. It implements all the blocks and procedures for the card activation/deactivation as shown in the block diagram of figure 1.

Figure 1: ST8004 internal block diagram

DDP

STEP-UP CONVERTER

INTERNAL OSCILLATOR

2.5MHz

En1 CLKUP

En2

GENERATOR

En5

RST BUFFER

En4

CLOCK

BUFFER

THERMAL

PROTECTIO

VCC

7 5

GND

100nF

CGND

RST

CLK

PRES

VTHSEL

OFF

RSTIN

CMDVCC

5/3V

CLKDIV1

CLKDIV2

XTAL1

XTAL2

VDD

SUPPLY

INTERNAL

REFERENCE

VOLTAGE

SUPERVISOR

CLOCK

CIRCUITRY

LARM

CLK

Vre

En4

En3

100nF 100nF100nF

ST8004

SEQUENCER

UX1

I/OUC

GND

I/O TRANSCEIVER

AUX1UC

AUX2UC

June 2004

UX2

I/O

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2. SEQUENCER

Core of the ST8004 is the sequencer (shown in figure 1) that must coordinate the enable signals for the activation and deactivation sequence and check for possible fault conditions. This because the smart card is basically a microcontroller and needs to be activated/deactivated by a correct sequence as required by the ISO/IEC7816 standard. Figure 2 and figure 3 show respectively the ST8004 activation and deactivation sequences.

Figure 2: Activation sequence

As shown in figure 2, when the PRES condition is true (PRES = low or PRES = high) and CMDVCC goes low, the activation sequence starts; the first block to be enabled is the step-up converter (V

), while the

last enabled signal is the RST that allows the start of the card software. Figure 3 shows the deactivation sequence when the CMDVCC goes high. During the deactivation the I/O outputs are deactivated at the time t13 being forced into a three-state condition, following the Vcc slope (see CH 1 in figure 3).

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Figure 3: Deactivation sequence

AN1978 - APPLICATION NOTE

3. CLOCK TO THE CARD

The clock signal to the card is present on the CLK pin when the ST8004 is activated; ; its frequency can be of the same value as one of its ratios compared to the input one (crystal or signal) as shown in the following table (Table 1: CLK division).

Table 1: CLK Division

CLKDIV 1 CLKDIV 2 CLK

0 0 1/8 f

01¼ f

11½ f

10 f

XTAL

According to the EIA/ISO7816 specifications, the CLK duty cycle must be enclosed between 45% and 55% even if the clock division changes. In this case, at CLKDIV change, the ST8004 waits for the first falling edge to ensure the duty cycle accuracy, as shown in Figure 4.

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Figure 4: Clock duty cycle on CLKDIV change

CH1: output CLK waveform.

CH1: output CLK waveform. CH2: CLKDIV1 pin.

CH2: CLKDIV1 pin.

Conditions:

Conditions: VDD=3.3V;

VDD=3.3V; VDDP=5V;

VDDP=5V; 5/3V=H;

5/3V=H; CMDVCC=L.

CMDVCC=L. F

=10MHz;

XTAL1

CLKDIV2=0V;

The output Duty Cycle is 50%±5%

The output Duty Cycle is 50%±5% even if the Clock Division changes.

even if the Clock Division changes.

The clock signal can be obtained by a crystal connected between the XTAL1 and XTAL2 pins or by an external signal applied to the XTAL1 pin; in this case the XTAL2 pin must be left floating. The external signal voltage value must be enclosed between GND and VDD. In the PCB design, in order to reduce the reflections especially for the high frequency, the Xtal should be connected as close as possible to the XTAL pins, as shown in figure 5.

Figure 5: XTAL connection

100 mils

XTAL2

XTAL1

GND

VDD

2MHz to 26MHz XTAL (Y1)

Compensation capacitors

Two compensation capacitors, lower than 22pF, can be used to improve the oscillator performance even if the characterization tests remarked that the CLK Duty Cycle is enclosed between 45% and 55%,

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without additional capacitors, even for a frequency higher than 26MHz. Another recommendation about the CLK output is to keep the CLK wire far from the other signals because inductive or capacitive effects could produce cross conduction on the transceiver lines. Moreover it is better to shield the clock wire with a ground plain or track on the PCB.

4. STEP-UP CONVERTER AND POWER SUPPLY REGULATOR

The ST8004 can drive both 3V and 5V cards through the supply voltage selector 5/3V pin (pin 3) as shown in Figure 6. If the 5/3V pin is to GND, the Vcc voltage is 3V and the internal Vcc regulator is connected directly to the VDDP pin. If the 5/3V pin is connected to VDD, the Vcc regulator is connected to the internal step-up converter, as shown in Figure 6, in order to provide the high Vcc supply voltage (5V) even when the VDDP voltage is lower than 5V.

Figure 6: Step-up converter block diagram.

DDP

100nF

ON/OFF

OUTPUT

7 5

STEP-UP

CONVERTER

GND

100nF

5/3V

ST8004

EN2

VCC

REGULATOR

The step-up converter is supplied by the VDDP pin; S1 and S2 pins are used to duplicate the supply voltage through the 100nF pumping capacitor, while the charge pump output is connected to the VUP pin that requires a 100nF storage capacitor to stabilize the voltage. Due to the switching circuitry, a little noise is introduced so, in order to reduce it and improve the efficiency of the step-up converter, the capacitors must be connected as close as possible to the pins as

shown in Figure 9 and are recommended with ESR lower than 50mΩ @ 100kHz such as MURATA

GRM31M7U1H104JA01B. Anyway, also capacitor with ESR up to 100mΩ @ 100kHz are enough to work in specifications.

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