ST AN1903 Application note

AN1903

APPLICATION NOTE

A First Order Sigma Delta Converter Using ST52x440

1 INTRODUCTION

This application note shows the implementation of a Sigma-Delta (Σ∆) converter using a member of ST52 microcontroller family.

Although many devices of the ST52 family already have a built-in A/D Converter, another kind of converter (precisely a Σ∆ converter) is implemented via sofware.

In this specific case, an ST52x440 is used. This device includes an Analog Comparator among its peripherals, which can also be used as a single slope ADC, thus allowing an easy implementation in firmware of the SD conversion algorithm using few additional external elements.

The Σ∆ conversion algorithm is easily implemented in firmware using few additional external elements. Attached you can find the firmware package.

2 SIGMA-DELTA THEORY

Sigma-Delta modulation has emerged as the architecture of choice for high-resolution analog-to-digital conversion using simple and low-precision analog components. In this kind of converter an increased resolution is obtained reducing the conversion bandwidth or increasing the clock speed, over sampling the signal to convert.

Over sampling has become popular because it avoids many difficulties encountered with conventional methods for A/D and D/A conversion, especially in those applications requiring high-resolution and using relative low-frequency signals. Moreover, sampling at high frequency eliminates the need for abrupt cutoffs in the analog anti-aliasing filters.

Classical Sigma-Delta circuits are composed of a Σ∆ Modulator, which provides a high-speed one-bit dat a string followed by a digital filter and decimator to produce high-resolution data. The lowpass Σ∆ modulator consists of one or more integrators and a one-bit quantizer. The basic con cept underlining Sigma-Delta Converters is the use of feedback in order to improve the effective resolution of the quantizer.

Figure 1 shows a Σ∆ Converter block diagr am. The input signal is added t o the signal coming from the feedback loop. This differentiated signal is then sent to the modulator. The comparator acts like a one-bit quantizer, its output is sent to the D/A converter of the feedback branch and to a digital filter which provides with time the multi-bit Digital Output.

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AN1903 - APPLICATION NOTE

Figure 1. Σ∆ Converter Block Diagram

Modulator

Differentiator

Analog

Signal

Input

Differentiator

+_+_+

+_+_+_+ _

3 IMPLEMENTATION WITH ST52X440 MICROCONTROLLER

In Figure 2 a scheme of how the Σ∆ Converter is implemented with the ST52x440 microcontroller is shown. If compared to a classical Sigma-Delta Converter, the external capacitor C tor; the comparator is built inside; voltage reference V means of two equal resistances R mented by the firmware. By means of the two equal resistances R conversion of signals in the range 0 divided by 5V is allowed.

When pin PC0 is set high by the feedback loop, the voltage at pin PB0 increases in magnitude until it becomes higher than V consequently until the comparator sets PC0 high. In the meantime, the number of zeros occurring at the

. Once this has occurred, pin PC0 is set low and the voltage at pin PB0 decreases

REF

output of the comparator (which means integrated signal higher than reference signal) are count ed. This number is strictly related to the input voltage V

Figure 2. Schematic

Integrator Comparator

+_+

∫

1- Bit D/A Converter

and R4; while the one-bit D/A Converter and the digital filter are imple-

+_+ _

REF

is supplied by partitioning the voltage VSS by

REF

CORE

routine

absolves the role of integra-

INT

Digita l

Digita l Output

Output

and R4 (center scale set to 2.5V) to a

2/8

Vdd

OSCOUT

Serial

OUTPUT

OSCOUT

OSCIN

Vpp

Vpp PC4

PC4

PC4 PC3

PC3

PB7/CS

PB7/CS PB6/BG

PB6/BG

PB5/AC5

PB5/AC5 PB4/AC4

PB4/AC4

PB4/AC4 PB3/AC3

PB3/AC3

PB3/AC3 PB2/AC2

PB2/AC2

PB1AC1

PB0/AC0

GNDA

ST52x440

REF

Firmware

closes loop

_ +

Vdd

Vdd Vss

Vss

Vss RESET

RESET

PC0

PC0 PC1

PC1

PC1 PC2

PC2

PC2 PA7/INT/ACSYNC

PA7/INT/ACSYNC

PA7/INT/ACSYNC PA6/TRES/TOUT

PA6/TRES/TOUT

PA6/TRES/TOUT PA5/TCLK

PA5/TCLK

PA5/TCLK PA4/TSTRT

PA4/TSTRT

PA4/TSTRT PA3/ACSTRT

PA3/ACSTRT

PA3/ACSTRT PA2/MAIN2/TOUTN

PA2/MAIN2/TOUTN

PA2/MAIN2/TOUTN PA1/MAIN1

PA1/MAIN1

PA1/MAIN1 PA0/TROUT

PA0/TROUT

INT

AN1903 - APPLICATION NOTE

When the signal to be converted comes from a high impedance source, a buffer has to be placed between this signal source and the input terminal of R2 in order to decouple impedances.

In Figure 3 a flow chart of the firmware used is shown. When V is higher than the reference signal pin PC0 is set low and the variable result is incremented; otherwise PC0 is set high and padding instructions are executed in order to keep all paths t hrough t he c ode equal. As soon as the variable Counter reaches value 2 result obtained is filtered and then serially shown through pin PB3. Serial communication is implemented by software by means of the internal timer, which fixes the BAUD rate.

Figure 3. Fl o w C hart

-1 (with N = num of bits) the result is stopped and the

Result = 0

Counter = 0

> V

PB0

ref

PB0

ref

(which is the input to the comparator)

PB0

YESNO

PC0=1

Padding

Counter ++

Counter= 1023?

4 FIRMWARE

The implementation used in this application performs the comparison between the integrated signal and the reference signal, the calculation of the result and closes the feedback loop. Moreover, it processes the results and gives them serially to the output pin PB3 so that they can be acquired, displayed and eventually processed by a PC.

The software was developed in Visual FIVE, the visual Development Tool of the ST FIVE Family of micros and it is displayed in the following section.

Figure 4 and 5 are two screens taken from the attached firmware developed in VisualFIVE describing respectively the flow chart of the main program and the result computation algorithm.

PC0=0

Resul ++

YESNO

10 bits Æ 8 bits

Show Value

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