ST AN1903 Application note

AN1903

APPLICATION NOTE

A First Order Sigma Delta Converter Using ST52x440

1 INTRODUCTION

This application note shows the implementation of a Sigma-Delta (Σ∆) converter using a member of ST52 microcontroller family.

Although many devices of the ST52 family already have a built-in A/D Converter, another kind of converter (precisely a Σ∆ converter) is implemented via sofware.

In this specific case, an ST52x440 is used. This device includes an Analog Comparator among its peripherals, which can also be used as a single slope ADC, thus allowing an easy implementation in firmware of the SD conversion algorithm using few additional external elements.

The Σ∆ conversion algorithm is easily implemented in firmware using few additional external elements. Attached you can find the firmware package.

2 SIGMA-DELTA THEORY

Sigma-Delta modulation has emerged as the architecture of choice for high-resolution analog-to-digital conversion using simple and low-precision analog components. In this kind of converter an increased resolution is obtained reducing the conversion bandwidth or increasing the clock speed, over sampling the

signal to convert.	Product(s
Over sampling has become popular because it avoids many difficulties ncountered with conventional
methods for A/D and D/A conversion, especially in those applications r	quiring high-resolution and using
relative low-frequency signals. Moreover, sampling at high frequency	liminates the need for abrupt cut-
offs in the analog anti-aliasing filters.

Classical Sigma-Delta circuits are composed of aObsoleteΣ∆ Modulator, which provides a high-speed one-bit data string followed by a digital filter and decimator to produce high-resolution data. The lowpass Σ∆ modulator

consists of one or more integrators and a one-bit quantizer. The basic concept underlining Sigma-Delta Converters is the use of feedback in order to-improve the effective resolution of the quantizer.

Figure 1 shows a Σ∆ Converter block diagram. The input signal is added to the signal coming from the feedback Product(s)loop. This differentiated signal is then sent to the modulator. The comparator acts like a one-bit quantizer, its output is sent to the D/A converter of the feedback branch and to a digital filter which provides

with time the multi-bit Digital Ou put. olete

March 2004

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VREF

AN1903 - APPLICATION NOTE

Figure 1. Σ∆ Converter Block Diagram

Modulator

	Analog	Differentiator	Integrator	Comparator
		+
			∫
	Signal			+	SW
		_				Digital
	Input
				_	CORE
					routine	Output

If compared to a classical Sigma-Delta Converter, the external capacitor CINT absolvesProduct(sthe role of integrator; the comparator is built inside; voltage reference VREF is supplied by partitioning the voltage VSS by

1- Bit D/A Converter

3 IMPLEMENTATION WITH ST52X440 MICROCONTROLLER

In Figure 2 a scheme of how the Σ∆ Converter is implemented with the ST52x440 microcontroller is shown.

means of two equal resistances R3 and R4; while the one-bit D/A Converter and the digital filter are implemented by the firmware. By means of the two equal resistances R3 and R4 (center scale set to 2.5V) to a conversion of signals in the range 0 divided by 5V is allowed.

When pin PC0 is set high by the feedback loop, the voltage at pin PB0 increases in magnitude until it be-

comes higher than VREF. Once this has occurred, pin PC0 is set low and the voltage at pin PB0 decreases consequently until the comparator sets PC0 high. In the meantime, the number of zeros occurring at the

output of the comparator (which means integrated signal higher than reference signal) are counted. This

number is strictly related to the input voltage VIN.
Figure 2. Schematic				Obsolete
			-
	Vdd	OSCOUT		ST52x440	Vdd
		OSCIN			Vss
		Vpp			RESET	R1	R2
		PC4			PC0			VIN
	R3
		PC3			PC1		CINT
		PB7/CS			PC2
Product(s)				Firmw are	PA7/INT/ACSYNC
olete	R4	PB6/BG
		PB5/AC5		closes loop	PA6/TRES/TOU T
		PB4/AC4			PA5/TCLK
	Serial	PB3/AC3			PA4/TSTRT
	OUTPUT	PB2/AC2	VREF		PA3/ACSTRT
		PB1AC1			PA2/MAIN2/TOU TN
				_
		PB0/AC0			PA1/MAIN1
				+
		GNDA			PA0/TROUT

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AN1903 - APPLICATION NOTE

When the signal to be converted comes from a high impedance source, a buffer has to be placed between this signal source and the input terminal of R2 in order to decouple impedances.

In Figure 3 a flow chart of the firmware used is shown. When VPB0 (which is the input to the comparator) is higher than the reference signal pin PC0 is set low and the variable result is incremented; otherwise PC0 is set high and padding instructions are executed in order to keep all paths through the code equal. As soon as the variable Counter reaches value 2N-1 (with N = num of bits) the result is stopped and the result obtained is filtered and then serially shown through pin PB3. Serial communication is implemented by software by means of the internal timer, which fixes the BAUD rate.

Figure 3. Flow Chart

Result = 0

Counter = 0

NO

YES

Product(s

VP B0

> Vref

?

PC0=1

PC0=0

Padding

Resul ++

Obsolete

Counter= 1023?

Counter ++

NO

-

YES

Product(s)

10 bits Æ 8 bits

Show Value

4 FIRMWARE

oleteally processed by a PC.

The implementation used in this application performs the comparison between the integrated signal and the reference signal, the calculation of the result and closes the feedback loop. Moreover, it processes the results and gives them serially to the output pin PB3 so that they can be acquired, displayed and eventu-

The software was developed in Visual FIVE, the visual Development Tool of the ST FIVE Family of micros and it is displayed in the following section.

Figure 4 and 5 are two screens taken from the attached firmware developed in VisualFIVE describing respectively the flow chart of the main program and the result computation algorithm.

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