ST AN1893 Application note
AN1893
Application note
Designing with L6925D, high-efficiency monolithic
synchronous step-down regulator
Introduction
This application note details the main features and application advantages of
STMicroelectronics’ new synchronous step-down regulator. After describing how the device
works and the main features, a step-by-step design section is provided in order to help with
the selection of the external components and the evaluation of the losses. The device
performances are shown in terms of efficiency and thermal results. In conclusion, some
application ideas are proposed.
This new product, realized in BCDV technology, is a high-efficiency monolithic synchronous
step-down regulator capable of delivering up to 800 mA of continuous output current and
regulating the output voltage from 0.6 V up to V
capability. The input voltage ranges from 2.7 V to 5.5 V. The control loop architecture is
based on a constant frequency peak current mode, while high efficiency at light loads is
achieved by a low consumption functionality. The very low quiescent current (25 µA) and
shutdown current (0.2 µA) make the device very suitable to supply battery-powered
equipment (particularly suitable for 1 Li-ion cell) like PDAs and hand-held terminals, DSCs
(digital still cameras) and cellular phones. The switching frequency is internally set at 600
kHz but the device can be externally synchronized up to 1.4 MHz. An internal reference
voltage of 0.6 V (typ), allows the device to regulate minimum output voltage of the same low
value. The low MOSFETs R
interesting features are: hysteretic UVLO, OVP, constant current short-circuit protection,
PGOOD and thermal shutdown. The MSOP8 package allows saving significant board
space.
ensures high efficiency at high output current. Additional
DS(on)
thanks to the 100% duty cycle operation
IN
Figure 1. Application test circuit
February 2009 Rev 3 1/29
www.st.com
Contents AN1893
Contents
1 Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1 LBI (low battery input)/LBO (low battery output) . . . . . . . . . . . . . . . . . . . . 7
3.2 UVLO (undervoltage lockout) operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.3 Modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.3.1 Low consumption mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.3.2 Low noise mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.4 System stability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.4.1 Current loop compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.4.2 Voltage loop compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4 Short-circuit protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1 Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.2 DROPOUT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.3 Adjustable output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.4 OVP (overvoltage protection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.5 Hysteretic thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1 External component selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1.1 Input capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1.2 Output capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1.3 Inductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.1.4 Compensation network (R
5.2 Losses and efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.2.1 Conduction losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.2.2 Switching losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.2.3 Gate charge losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1C3
6 Thermal considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
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AN1893 Contents
7 Application board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
8 Efficiency results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
9 Application ideas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
9.1 Buck boost topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
9.2 White LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
9.2.1 Driving white LEDs: buck topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
9.2.2 Driving white LEDs: boost topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
9.2.3 Driving white LEDs: buck-boost topology . . . . . . . . . . . . . . . . . . . . . . . 26
10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
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List of figures AN1893
List of figures
Figure 1. Application test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2. Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3. MSOP8 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 4. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 5. Low consumption mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 6. Low noise mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 7. Slope compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 8. Equivalent circuit for the voltage loop analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 9. Equivalent circuits during the ON time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 10. Equivalent circuit during the OFF time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 11. Valley current limit protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 12. Thermal performance results: V
Figure 13. RDS(on) vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 14. Application board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 15. Component placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 16. Top side view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 17. Bottom side view. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 18. Schematic demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 19. Low noises vs. low consumption efficiencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 20. Efficiency vs. output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 21. Efficiency vs. output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 22. Efficiency vs. output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 23. Positive buck boost application. 1 Li-Ion cell to 3.3 V at 0.25 A . . . . . . . . . . . . . . . . . . . . . 24
Figure 24. Buck topology schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 25. Boost topology schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 26. Buck-boost topology schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 27. PWM brightness control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 28. Analog brightness control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
= 3.7 V V
IN
OUT
= 1.8 V I
= 800 mA . . . . . . . . . . . . . . 19
OUT
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AN1893 Pin functions
1 Pin functions
Table 1. Pin description
N. Name Description
Battery low voltage detector input. The internal threshold is set at 0.6 V. The
1 LBI
2 COMP
3 VFB Error amplifier inverting external divider.
4 GND Ground.
5 LX Switches output node. Common point between high side and low side MOSFETs
6
VCC
7 SYNC
8 LBO
external threshold can be adjusted by using an external resistor divider (see
Section 3.1). If not used, the pin can be left floating.
Error amplifier output. A compensation network has to be connected to this pin.
Usually a 220 pF capacitor is enough to guarantee the loop stability (see
Section 3.3.1).
Input voltage. The startup input voltage is 2.8 V (typ) while the operating input
voltage range is from 2.7 V to 5.5 V. An internal UVLO circuit realizes a 200 mV
(typ) hysteresis.
Operating mode selector input. Low consumption mode when connected to a
higher voltage than 1.3 V (up to VCC). Low noise mode when connected to a lower
than 0.5 V (down to GND). Synchronization mode when connected to an external
appropriate clock generator. This pin must not be left floating.
Battery low voltage detector output. If the voltage at the LBI pin drops below the
internal threshold, the LBO pin goes low. The LBO pin is an open drain output. A
pull-up resistor should be connected between the pin and the output voltage. If not
used, the pin can be left floating.
Figure 2. Pin connections
Figure 3. MSOP8 package
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Block diagram AN1893
2 Block diagram
Figure 4. Block diagram
6/29
AN1893 Functional description
3 Functional description
The main loop uses constant frequency peak current mode architecture. Each cycle, the
high side MOSFET is turned on, triggered by the oscillator, so that the current flowing
through it increases with a slope fixed by the operating conditions. When the sensed current
(a part of the high side current) reaches the output value of the error amplifier E/A, COMP
pin, the internal logic turns off the high side MOSFET and turns on the low side one until the
next clock cycle begins or the current flowing through it goes down to zero (ZERO-
CROSSING comparator). During the load transients, the voltage control loop keeps the
output voltage in regulation changing the COMP pin value, fixing a new turnoff threshold.
Moreover, during these dynamic conditions the choke must not saturate and the inductor
peak current must never exceed the maximum value. This value is in function of the internal
slope compensation (see Section 3.4.1).
3.1 LBI (low battery input)/LBO (low battery output)
A low battery input pin is available. The pin is internally connected to a comparator with a
threshold of 0.6 V. By using an external resistor divider connected between the battery
voltage and the ground it is possible to fix a threshold for the battery voltage. When the
voltage at the LBI pin goes lower than 0.6 V, the LBO pin is forced low. This feature can be
useful for example to have a warning signal when the battery is quite discharged.
3.2 UVLO (undervoltage lockout) operation
The device is particularly designed for equipment powered by a Li-ion battery. These types
of batteries are almost fully discharged when their voltage goes lower than approximately 3
V. For this reason, a UVLO is internally set at 2.8 V, with a hysteresis of 200 mV. Thanks to
this feature, when the battery is fully discharged, the device automatically turns off.
3.3 Modes of operation
3.3.1 Low consumption mode
At light load, the device operates in burst mode in order to keep the efficiency very high also
in these conditions.
While the device is not switching the load discharges the output capacitor and the output
voltage goes down. The COMP pin, due to the feedback loop, increases and when a fixed
internal threshold is reached, the device starts to switch again. In this condition the peak
current limit is set approximately in the range of 200 mA-400 mA, depending on the slope
compensation (see Section 3.4.1). Once the device starts to switch the output capacitor is
recharged. The repetition time of the bursts depend on parameters like input and output
voltages, load, inductor and output capacitors.
Between two bursts, most of the internal circuitries are off, thus reducing the device
consumption down to a typical value of 25 µA. During the burst, the frequency of the pulses
is equal to the internal frequency.
7/29
Functional description AN1893
3.3.2 Low noise mode
In case the very low frequencies generated by the low consumption mode are undesirable,
the low noise mode can be selected. The efficiency is a little bit lower compared with the low
consumption mode conditions when working close to zero loads, while the trend is to reach
the efficiency of low consumption mode for intermediate light loads.
The device could skip some cycles in order to keep the output voltage in regulation. In
Figure 5 and 6 the LCM and LNM typical waveforms are shown.
Figure 5. Low consumption mode
Figure 6. Low noise mode
Measurement conditions: V
C
= 22 µF; RC = 40 kΩ; CC = 330 pF
OUT
= 4.2 V; V
IN
= 1.5 V; I
OUT
= 30 mA; L = 6.8 µH; CIN = 10 µF;
OUT
Figure 19 shows a comparison between the efficiency in low noise mode and the efficiency
in low consumption mode.
8/29
AN1893 Functional description
3.4 System stability
Since the device operates with constant frequency peak current mode architecture, the
voltage loop stability is usually not a big issue. For most of the applications a 220 pF
connected between the COMP pin and ground is enough to guarantee the stability. In case
very low ESR capacitors are used for the output filter, such as multilayer ceramic capacitors,
the zero introduced by the capacitor itself can be shifted at a frequency well above the
resonance frequency of the L-C filter and the loop stability could be affected.
Adding a series resistor to the 220 pF capacitor can solve this problem. The right value for
the resistor can be determined by checking the load transient response voltage waveforms.
The current mode stability can be studied in two consecutive steps; first the inner loop is
closed (current loop) and then the second loop stability is considered (voltage loop).
3.4.1 Current loop compensation
The selected control architecture brings many advantages: easy compensation with ceramic
capacitors, fast transient response and intrinsic peak current measurement that simplify the
current limit protection. A known drawback, however, is that the current loop becomes
unstable when the duty cycle exceeds 50%.
This phenomenon is known as "sub-harmonic oscillation" and can be avoided by adding a
slope compensation signal. Due to this fact, the current limit of the device decreases when
the slope compensation signal is applied. The slope compensation is internally implemented
from a duty around 30% and Figure 7 shows how the slope compensation affects the device
current limit.
Figure 7. Slope compensation
The amount of slope compensation depends on the inductor current slope during the OFF
time. This slope, for a given duty cycle, is inversely proportional to the inductor value. Since
the device can be synchronized at a higher frequency, it is reasonable to calculate the
inductor value in terms of it. Finally, the input voltage affects the OFF time slope as well.
This is obvious because, for a given duty cycle, the output voltage (and so the OFF time
inductor current slope) is directly proportional to the input one. In order to better manage
these issues, the amount of slope compensation depends not only on the duty cycle but also
on the switching frequency and the input voltage.
9/29
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