ST AN1882 Application note
AN1882
Application note
Designing with the L6926, high efficiency monolithic
synchronous step-down regulator
Introduction
This application note details the main features and application advantages of this new
synchronous step-down regulator. After describing how the device works and the main
features, a step-by-step design section is provided in order to aid in the selection of the
external components and in the evaluation of the losses. The device performances are
shown in terms of efficiency and thermal results. At the end, some application ideas are
proposed. This new product, designed using BCDV technology, is a high efficiency
monolithic synchronous step-down regulator capable of delivering up to 800 mA of
continuous output current and to regulate the output voltage from 0.6 V up to V
the 100% duty cycle operation capability. The input voltage ranges from 2 V to 5.5 V. The
control loop architecture is based on a constant frequency peak current mode, while high
efficiency at light loads is achieved by a low consumption functionality. The very low
quiescent current (25 µA) and shutdown current (0.2 µA) make the device very suitable to
supply battery-powered equipment like PDAs and hand-held terminals, DSCs (digital still
cameras) and cellular phones. The switching frequency is internally set at 600 kHz, but the
device can be externally synchronized up to 1.4 MHz. An internal reference voltage of 0.6 V
(typ) allows the device to regulate a minimum output voltage of the same low value. The low
MOSFETs R
features are: hysteretic UVLO, OVP, constant current short-circuit protection, Power Good
and thermal shutdown. The MSOP8 package allows significant space savings on the board.
ensures high efficiency at high output current. Additional beneficial
DS(on)
thanks to
IN
Figure 1. Application test circuit
April 2012 Doc ID 10209 Rev 4 1/30
www.st.com
Contents AN1882
Contents
1 Pins function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1 Modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1.1 Low consumption mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1.2 Low noise mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.2 System stability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2.1 Current loop compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2.2 Voltage loop compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4 Short-circuit protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1 Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.2 DROPOUT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.3 PGOOD (Power Good output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.4 Adjustable output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.5 OVP (over-voltage protection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.6 Hysteretic thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1 External components selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1.1 Input capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1.2 Output capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1.3 Inductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.1.4 Compensation network (R1C3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.2 Losses and efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.2.1 Conduction losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.2.2 Switching losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.2.3 Gate charge losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6 Thermal considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7 Application board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2/30 Doc ID 10209 Rev 4
AN1882 Contents
8 Efficiency results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
9 Application ideas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
9.1 Buck boost topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
9.2 White LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
9.2.1 Driving white LEDs: buck topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
9.2.2 Driving white LEDs: boost topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
9.2.3 Driving white LEDs: buck/boost topology . . . . . . . . . . . . . . . . . . . . . . . . 26
10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Doc ID 10209 Rev 4 3/30
List of figures AN1882
List of figures
Figure 1. Application test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2. Pins connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3. MSOP8 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 4. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 5. Low consumption mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 6. Low noise mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 7. Slope compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 8. Equivalent circuit for the voltage loop analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 9. Equivalent circuits during the ON time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 10. Equivalent circuit during the OFF time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 11. Valley current limit protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 12. Thermal performance results: V
Figure 13. RDS(on) vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 14. Application board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 15. Component placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 16. Top side view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 17. Bottom side view. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 18. Schematic demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 19. Low noises vs. low consumption efficiencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 20. Efficiency vs. output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 21. Efficiency vs. output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 22. Efficiency vs. output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 23. Positive buck boost application. 1 Li-Ion cell to 3.3 V@0.25 A . . . . . . . . . . . . . . . . . . . . . . 25
Figure 24. Buck topology schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 25. Boost topology schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 26. Buck boost topology schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 27. PWM brightness control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 28. Analog brightness control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
= 3.7 V V
IN
OUT
= 1.8 V I
= 800 mA . . . . . . . . . . . . . . 20
OUT
4/30 Doc ID 10209 Rev 4
AN1882 Pins function
1 Pins function
Table 1. Pin description
N. Name Description
Shutdown input. When connected to a lower voltage than 0.5 V (down to GND) the device stops
1 RUN
2 COMP
working. When connected to a higher voltage than 1.3 V (up to VCC) the device is enabled. The pin
must not be left floating
Error amplifier output. A compensation network has to be connected from this pin to GND. Usually a
220 pF capacitor is enough to guarantee the loop stability (see related section)
3 VFB
4 GND Ground
5 LX Switch output node. Common point between high side and low side MOSFETs
6
VCC
7 SYNC
8 PGOOD
Error amplifier inverting input, used to adjust the output voltage (from 0.6 V to VIN) by an external
divider.
Input voltage. The operating input voltage range is from 2 V to 5.5 V. An internal UVLO circuit
realizes a 200 mV (typ) hysteresis
Operating mode selector input. Low consumption mode, when connected to a higher voltage than
1.3 V (up to VCC). Low noise mode when connected to a lower than 0.5 V (down to GND).
Synchronization mode when connected to an external appropriate clock generator. This pin must
not be left floating
Power Good comparator output. It is an open drain output. A pull-up resistor should be connected
between Power Good and V
the regulated output voltage and goes high when the output voltage is greater than 90% of the
regulated output voltage. If not used, the pin can be left floating.
. The pin is forced low when the output voltage is lower than 90% of
O
Figure 2. Pins connection
Figure 3. MSOP8 package
Doc ID 10209 Rev 4 5/30
Block diagram AN1882
2 Block diagram
Figure 4. Block diagram
6/30 Doc ID 10209 Rev 4
AN1882 Functional description
3 Functional description
The main loop uses constant frequency peak current mode architecture. Each cycle, the
high side MOSFET is turned on, triggered by the oscillator, so that the current flowing
through it increases with a slope fixed by the operating conditions. When the sensed current
(a part of the high side current) reaches the output value of the error amplifier E/A, COMP
pin, the internal logic turns off the high side MOSFET and turns on the low side one until the
next clock cycle begins or the current flowing through it goes down to zero (ZERO
CROSSING comparator). During the load transients, the voltage control loop keeps the
output voltage in regulation changing the COMP pin value, fixing a new turn off threshold.
Moreover, during these dynamic conditions the choke must not saturate and the inductor
peak current must never exceed the maximum value. This value is function of the internal
slope compensation (see related section).
3.1 Modes of operation
3.1.1 Low consumption mode
At light load, the device operates in burst mode in order to keep the efficiency very high also
in these conditions.
While the device is not switching the load discharges the output capacitor and the output
voltage goes down. The COMP pin, due to the feedback loop, increases and when a fixed
internal threshold is reached, the device starts to switch again. In this condition the peak
current limit is set approximately in the range of 200 mA-400 mA, depending on the slope
compensation (see related section). Once the device starts to switch the output capacitor is
recharged. The repetition time of the bursts depend on parameters like input and output
voltages, load, inductor and output capacitors.
Between two bursts, most of the internal circuitries are off, so reducing the device
consumption down to a typical value of 25 µA. During the burst, the frequency of the pulses
is equal to the internal frequency.
3.1.2 Low noise mode
In case the very low frequencies generated by the low consumption mode are undesirable,
the low noise mode can be selected. The efficiency is a little bit lower compared with the low
consumption mode conditions when working close to zero loads, while the trend is to reach
the efficiency of low consumption mode for intermediate light loads.
The device could skip some cycles in order to keep the output voltage in regulation. In the
Figure 5
and 6 the LCM and LNM typical waveforms are shown.
Doc ID 10209 Rev 4 7/30
Functional description AN1882
Figure 5. Low consumption mode
Figure 6. Low noise mode
Measurement conditions: V
C
= 22 µF; RC = 40 kΩ; CC = 330 pF
OUT
In
Figure 19
is shown a comparison between the efficiency in low noise mode and the
IN
= 4.2 V; V
= 1.5 V; I
OUT
efficiency in low consumption mode.
3.2 System stability
Since the device operates with constant frequency peak current mode architecture, the
voltage loop stability is usually not a big issue. For most of the applications a 220 pF
connected between the COMP pin and ground is enough to guarantee the stability. In case
very low ESR capacitors are used for the output filter, such as multilayer ceramic capacitors,
the zero introduced by the capacitor itself can be shifted at a frequency well above the
resonance frequency of the L-C filter and the loop stability could be affected.
Adding a series resistor to the 220 pF capacitor can solve this problem. The right value for
the resistor can be determined by checking the load transient response voltage waveforms.
8/30 Doc ID 10209 Rev 4
= 30 mA; L = 6.8 µH; CIN = 10 µF;
OUT
AN1882 Functional description
The current mode stability can be studied in two consecutive steps; first the inner loop is
closed (current loop) and then the second loop stability is considered (voltage loop).
3.2.1 Current loop compensation
The selected control architecture brings many advantages: easy compensation with ceramic
capacitors, fast transient response and intrinsic peak current measurement that simplify the
current limit protection. A known drawback, however, is that the current loop becomes
unstable, when the duty cycle exceeds 50%.
This phenomenon is known as "sub-harmonic oscillation" and can be avoided by adding a
slope compensation signal. Due to this fact, the current limit of the device decreases when
the slope compensation signal is applied. The slope compensation is internally implemented
from a duty around 30% and
current limit.
Figure 7. Slope compensation
Figure 7
shows how the slope compensation affects the device
The amount of slope compensation depends on the inductor current slope during the OFF
time. This slope, for a given duty cycle, is inversely proportional to the inductor value. Since
the device can be synchronized at higher frequency, it is reasonable to calculate the inductor
value in terms of it. Finally, the input voltage affects the OFF time slope as well. This is
obvious because, for a given duty cycle, the output voltage (and so the OFF time inductor
current slope) is directly proportional to the input one. In order to better manage these
issues, the amount of slope compensation does not depend only on the duty cycle but also
on the switching frequency and the input voltage.
Table 2. Suggested inductor values for different switching frequencies, at
V
= 3.6 V and V
IN
FSW [kHz] Minimum inductor value [µH]
600 6.8
1000 3.6
1400 2.7
=1.8 V
OUT
Doc ID 10209 Rev 4 9/30
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