ST AN1830 APPLICATION NOTE

AN1830

APPLICATION NOTE

ACHIEVING HIGH ACCURACY AND 13-BIT RESOLUTION

WITH ST7LITE2 ADC

1 INTRODUCTION

The purpose of this application note is to show users of the ST7LITE2 ADC how to achieve 13bit resolution with the internal amplifier. It also explains the software methodology, which can be applied to find and cancel the amplifier offset error. A reference application is shown with implementation of hardware and software filtering techniques (using an averaging algorithm) to minimize the ADC error.

Please note the data provided with this application note is for reference only, measured in a lab under typical conditions (unless specified otherwise) and not tested in production.

2 ST7LITE2 ADC OVERVIEW

The ST7LITE2 features a 10-bit successive approximation converter with internal sample and hold circuitry. The ADC is connected to 7 multiplexed analog input channels which allow 7 pins on Port B to be used as input for the ADC. The ADC can be turned ON/OFF using the ADON bit, which can help to reduce consumption when not in use.

In addition to this it also provides an internal amplifier which can be used for small signal amplification.

2.1 ADC FUNCTIONALITY

The ADC can be connected to any of the analog channels by using the CH[2:0] bits in the ADCCSR Register. This analog input is connected to internal sample and hold circuitry. The output of which is then converted into a 10-bit digital result via successive approximation (refer

Figure 1). The result of the conversion is stored in a 10-bit Data Register (ADCDRH + AD-

to CDRL).

The analog supply pins V

DDA

and V

are the same as VDD and VSS for ST7LITE2.

SSA

Rev. 1.0

AN1753/0405 1/15

ACHIEVING HIGH ACCURACY AND 13-BIT RESOLUTION WITH ST7LITE2 ADC

Figure 1 ADC Block Diagram

AIN0

AIN1

AINx

CPU

DIV 2

ANALOG

MUX

x 1 or x 8

AMPSEL

bit

ADCDRH

DIV 4

ADC

SLOW

bit

CH2 CH1EOC SPEED ADON 0 CH0

HOLD CONTROL

ADC

ADCCSR

ADC

ADCDRL 00 0

ANALOG TO DIGITAL

CONVERTER

D4 D3D5D9 D8 D7 D6 D2

AMP

CAL

SLOW

AMP

SEL

D1 D0

2.1.1 ADC Registers

The ADC functionality is driven using 3 main registers ADCCSR, ADCDRH and ADCDRL.

These are described below.

CONTROL/STATUS REGISTER (ADCCSR)

7 0

EOC SPEED ADON 0 0 CH2 CH1 CH0

This is a read/write register used to:

- Select the analog input channel by using bits CH[2:0]

- Turn the ADC ON / OFF (ADON)

- Select the ADC clock speed (SPEED)

- Obtain the status of conversion complete cycle (EOC)

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ACHIEVING HIGH ACCURACY AND 13-BIT RESOLUTION WITH ST7LITE2 ADC

DATA REGISTER HIGH (ADCDRH)

7 0

D9 D8 D7 D6 D5 D4 D3 D2

This read only register provides MSB D[9:2] of the A/D conversion result.

AMP CONTROL/DATA REGISTER LOW (ADCDRL)

7 0

0 0 0

AMP

CAL

SLOW

AMP-

SEL

D1 D0

The read/write register can be used to:

- Provide LSB D[1:0] of the A/D conversion result.

- Select amplifier functionality: Amplifier select and Calibration (AMPSEL and AMPCAL)

- To configure f

along with the SPEED bit in the ADCCSR register (SLOW)

ADC

For a detailed description of each bit, refer to the ST7LITE2 datasheet.

2.2 UNDERSTANDING THE ADC INTERNAL AMPLIFIER

The purpose of the amplifier is to amplify an input voltage at analog input by a factor of 8. The amplifier output is fed to the ADC. The amplifier introduces an offset at the output (

OFFSET

Thus the output becomes:

(Amplifier) = V

OUT

OFFSET

+ 8 x V

where,

OFFSET

is the output offset voltage of the amplifier.

VIN is the amplifier input voltage (= AINx). Its range depends on the VDD supply voltage.

The amplifier is switched ON by the ADON bit in the ADCCSR register, so no additional startup time is required when the amplifier is selected by the AMPSEL bit.

You can also switch between the direct input and the amplified input i.e. the output of the amplifier can be either equal to its input or equal to the amplified output. This is controlled by the control signal AMPSEL.

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ACHIEVING HIGH ACCURACY AND 13-BIT RESOLUTION WITH ST7LITE2 ADC

2.2.1 AMPLIFIER OUTPUT OFFSET(V

OFFSET

): A Design Factor

A deliberate offset has been introduced in the design of the ST7LITE2 amplifier because in its absence, for the 0V input, the amplifier goes into saturation and the final stage driver transistor inside the amplifier can’t drive the capacitive load inside the ADC within the sampling period.

This phenomenon also leads to nonlinearity in the transfer curve around 0V input. By introducing the offset, the driver transistor is kept in the active region and this problem is avoided. Therefore the amplifier offset is a design factor and not an error.

2.2.1.1 AMPLIFIER OFFSET VARIATION WITH RESPECT TO TEMPERATURE

One more important point is offset variation with respect to temperature. The offset is quite sensitive to temperature variations. In order to ensure a good reliability in measure ments, the offset must be recalibrated periodically i.e. may be after “N” seconds while ap-

plication is running depending on application requirement and temperature variation.

Table 1 Typical offset variation at 5V VDD with respect to temperature (1LSB= 4.88mV)

Temperature in 0C -45 -20 +25 +90

Error in LSB -12 -7 0 +13

2.2.2 AMPLIFIER GAIN

The typical gain of the amplifier is 8 by design, which is a ratio result of 2 on-chip resistors. The mismatch in these 2 resistors can create gain error, depending on the voltage coefficient and

temperature. The measured gain error, including ADC inaccuracies is around 6% at 25

2.2.3 TOTAL UNADJUSTED ERROR (TUE)

The TUE is a maximum deviation between the actual and the ideal transfer curves.

Table 2 below shows the Total Unadjusted Error for different VDD and V

IN (Max)

when the amplifier is ON without applying any software or hardware filtering over the temperature range – 40°C to +90°C. This is a global TUE since it includes ADC, Amplifier gain, Application and Offset Errors. This can be reduced using the method explained in

Section 3.

Table 2 Total Unadjusted Error (Temperature: –40°C to +90°C)

VIN

(Max)

TUE

3.6V 350mV ± 10 LSB

5.0V 500mV ± 10 LSB

2.2.4 TOTAL ERROR IN PERCENTAGE (TE%)

This section presents 2 graphs showing the total precision error with respect to VIN for TUE equal to ±10 LSB. The graphs (

Figure 2 and Figure 3) show the variation in error with respect

to VIN.

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ACHIEVING HIGH ACCURACY AND 13-BIT RESOLUTION WITH ST7LITE2 ADC

The % TE increases for lower voltages, therefore it is recommended that you use the right voltage range depending on the supply voltage V

. The formula used to calculate TE is:

Total Error (TE) in worst case conditions = Global TUE / ((VIN x Typical gain) / 1LSB x100%

Where, Global TUE=±10LSB

Typical Amplifier Gain = 8

1LSB

for 5V VDD = 4.88mV

ideal

for 3.6V VDD= 3.5mV

ideal

Figure 2 Worst Case Total Error % @ 5V

7 6 5 4 3

TE%

2 1 0

0 0.1 0.2 0.3 0.4 0.5 0.6

ideal

)

Figure 3 Worst Case Total Error % @ 3.6V

9 8 7 6 5

TE %

4 3 2 1 0

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4

in Max

Vin

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