ST AN1810 Application note

AN1810

APPLICATION NOTE

STR71x BSPI COMMUNICATION

WITH M25P10-A SERIAL FLASH

INTRODUCTION

The aim of this application note is to present a practical example of communication using the BSPI peripheral of the STR71x.

It shows an easy way of communicating between a STR71x microcontroller and a M25P10-A SPI Serial Flash memory. The purpose is to perform, through BSPI, a write in the memory, followed by a read of the written data.

The software implemented manages write and read operations between the STR71x BSPIinterface and the M25P10-A serial flash memory from STMicroelectronics.

1 APPLICATION OVERVIEW

This section summarizes the main features of the connection between STR71x and the SPI Flash memory.

The Buffered Serial Peripheral Interface (BSPI) allows full-duplex, synchronous, serial communication between devices. A BSPI system may consist of a master and several slaves, or of a system in which devices may be either master or slave. There is only one master at any time.

During BSPI transfer, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). Data is transmitted MSB first. The serial clock is used to synchronize the data transfer during a sequence of eight clock pulses.

The bus signals are:

–The serial clock (SCLK).

–The MOSI (Master Out Slave In).

–The MISO (Master In Slave Out).

Another pin, the SSN pin (slave select), is needed to select Slave or Master Mode for each device.

In this application note, the STR71x is always used as master (S1.SSN pin = high level). The STR71x and SPI Flash interface set-up is shown in Figure 2.

Rev. 2.0

AN1810/0305

1/8

1

STR71x BSPI COMMUNICATION WITH M25P10-A SERIAL FLASH

2 STR71X CONFIGURATION

2.1 I/O CONTROL

Five pins of the STR71x are used:

–The 4 (data and clock) BSPI pins (S1.SCLK, S1.MOSI, S1.MISO, S1.SSN)

–An output (P0.3) pin to select and deselect the M25P10-A

In this application, the P0.3 pin is used to drive the M25P10-A chip select pin. It is configured as output push-pull (refer to the STR71x Reference Manual for more details).

2.2 BSPI PERIPHERAL

2.2.1 Baud Rates

Firstly, you have to choose the BSPI communication speed. As the clock is given by the master, you must configure the baud rate of the STR71x using the function

BSPI_ClockDividerConfig(BSPI1,Divider_factor_bits) or directly with the BSPI1_CLK register (refer to STR71x Reference Manual for more details).

Note: In master mode, the Divider_factor_bits parameter must be an even number greater than five (refer to STR71x Reference Manual for more details).

2.2.2 Clock Phase and Polarity

The next items to configure are the clock polarity and phase. The clock polarity CPOL controls the steady state value of the clock when no data is being transferred.

The clock phase CPHA selects on which clock transition the bit capture is made and consequently on which clock transition data is latched.

You must be careful because some devices do not allow all timing relationships. For instance, the M25P10-A Serial Flash Memory device accepts only CPOL,CPHA = (0,0) or (1,1) configurations.

2/8

2

STR71x BSPI COMMUNICATION WITH M25P10-A SERIAL FLASH

3 M25P10-A SERIAL FLASH MEMORY MANAGEMENT AND CONFIGURATION

3.1 SUMMARY DESCRIPTION

The M25P10-A is a 1 Mbit (128k * 8) Serial Flash Memory, with advanced write protection mechanisms, accessed by a high speed SPI-compatible bus. The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction.

The write protect pin (W) and the hold pin (H) are not used in our application (both are high level).

3.2 STATUS REGISTER

The device has one status register which contains a number of control bits and status bits, as shown in the following figure:

Figure 1. Status Register Control and Status Bits

SRWD 0 0 0 BP1 BP0 WEL WIP

Status Register Write Protect

Block Protect Bit

Write Enable Latch Bit

Write in Progress Bit

The SRWD bit is operated in conjunction with the Write Protect (W) signal.

The BP1 and BP0 bits in the status register can be used to write protect a block of memory. In this application, both bits are cleared, allowing write access to all memory.

The WEL bit indicates the status of the write enable latch.

The WIP bit indicates whether the memory is busy with a Write Status register, Program or Erase cycle.

3.3 INSTRUCTION SET

Prior to any operation, the device must be selected (S pin at low level), then a one-byte instruction code must be sent to the Serial Flash Memory. The device has a set of 11 instructions: (see Table 1, “Instruction Set,” on page 4).

3/8