ST AN1798 Application note

AN1798

Application note

How to use the STR71x A/D converter

and apply a conversion speed-up technique

Introduction

This application note describes how to use the Sigma-Delta Analog to Digital Converter (ADC) in the STR71x microcontroller.

It describes the Sigma-Delta ADC calibration and linearization technique and shows how to apply a conversion speed-up technique to reduce the conversion time.

November 2007 Rev 3 1/16

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Contents AN1798

1 Principle of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 STR71x ADC features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.1 Clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.2 ADC output, Gain and offset features . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.3 Round-Robin and Single channel modes . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.4 Conversion data availability and interrupt generation . . . . . . . . . . . . . . . . . 5

3 Calibration and linearization technique . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.1 Principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.2 Hardware implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.3 Firmware description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4 STR71x ADC conversion speed-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.1 Hardware implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.2 Firmware description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

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AN1798 Principle of operation

1 Principle of operation

Sigma-Delta converters, known also as oversampling converters, sample the input signal many times for each output sample with a frequency rate much greater than the Nyquist frequency (twice the input bandwidth). A Sigma-Delta converter consists of two blocks, the first is the Sigma-Delta modulator which produces the bit stream to the second part which consists of a digital filter and decimator.

Figure 1. A Sigma-Delta converter block diagram

Integrator

Vin

ADC

N bits of DATA

Digital filter

and Decimator

N bits

DAC

N bits

The STR71x ADC is a Sigma-Delta converter which composed of a second-order SigmaDelta modulator followed by a sinc3 digital filter and decimator.

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STR71x ADC features AN1798

2 STR71x ADC features

The STR71x ADC consists of four channels (Ip1 to Ip4 or AIN0 to AIN3) to convert signals with an input range of 0 to 2.5 V into 12-bit format. The following figure shows the ADC module of STR71x.

Figure 2. ADC STR71x block diagram

Ip1

Ip2

Ip3

Ip4

Bandgap Voltage Reference

2.1 Clock timing

Each channel supports up to 1 kHz for sampling frequency (fs), consequently the signal frequency can not exceed 500 Hz (to respect the

(oversampling frequency) is the clock frequency which clocks the Sigma-Delta

Mod

modulator. This frequency can not exceed 2.1 MHz and therefore the maximum sampling frequency is equal to 1 kHz (fs = 2.1 MHz / 512 * 4 = 1 kHz).

VCM VRef

Σ∆

Modulator

fs = f

Mod

Sinc3 Filter

VCM

VRef

/ 512 * 4

Registers

Ch0 Data

Ch1 Data

Ch2 Data

Ch3 Data

Control/ Status

Prescaler

Output Data Bus

IRQ

Nyquist frequency condition).

is generated by PCLK2 and divided down by the prescaler factors configured in the

Mod

ADC_CPR register. The prescaler output frequency must be not greater than 2.1 MHz.

= f

Mod

Example: if f

= fs * 512 * 4 = 1 kHz * 512 * 4 ~ 2 MHz

Mod

The Prescaling factor = f

= 16 MHz and the desired sampling frequency fs= 1 kHz.

PCLK2

/ f

= 16 MHz / 2 MHz = 8

Mod

This value being twice the prescaler register value: so, the value to be configured in the ADC_CPR register is equal to 0x4. (see STR71x Reference Manual, ADC section: ADC prescaler setting table)

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/ Prescaling factor

AN1798 STR71x ADC features

2.2 ADC output, Gain and offset features

The converted values stored in ADC_DATA[n] 16-bit register are signed two’s complement values and only the 12 most significant bits are used.

The following figure gives the ADC output versus the input voltage.

Figure 3. ADC output

ADC_DATA(0V) and ADC_DATA(2.5V) are the conversion of 0V and 2.5V respectively. The gain of the ADC is given by:

G = [0xFFF - ADC_DATA(0V) + ADC_DATA(2.5V)] / 2.5

The quantum is calculated by the following equation:

q = 2.5V / [0xFFF - ADC_DATA(0V) + ADC_DATA(2.5V)]

The offset is the digital unsigned value of 0V (ADC_DATA(0V)) and the application should subtract this offset when reading all the conversion results.

2.3 Round-Robin and Single channel modes

These modes are provided to simplify the use of the ADC.

● Single channel mode selects one channel that is the only channel input to the Sigma-

Delta modulator. To use single channel mode, bit 6 in the ADC_CSR register must be set to 1. A valid sample in this mode is produced every 2048 modulator clock cycles.

● Round-Robin mode (which is the normal mode) allows you to simplify your software

code and avoid using an endless loop (while (1)) to get the converted values of all channels continuously. This process is repeated for each of the channels continually in a round-robin fashion. A valid sample in this mode is produced every 512 modulator clock cycles for each channel.

2.4 Conversion data availability and interrupt generation

The End of Conversion is indicated by four flags or by interrupt generation. The four flags are the Data Available flags (DA[n]) in the Control Status register. They allow the application software to determine which channel data register has a new sample ready to be read. Each DA[n] flag corresponds to ADC channel n. They are set by hardware as soon as a new sample on the corresponding channel is available and they are automatically cleared when the corresponding data register is read.

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