ST AN1787 Application note
Conversion Guide, uPSD3200 to uPSD3400 series
1 Introduction
The uPSD family currently consists of three series , uPSD3200, uPSD3300, and uPSD3400.
All three series are available in the same kind of packages (52-pin and 80-pin TQFP), but
there are a few differences in pin definitions. This document describes the differences and
suggests methods to easily migrate designs from the uPSD3200 series to uPSD3400. You
can implement simple techniques on y our printed circuit b oard to accept either a uPSD3200
or a uPSD3400 during manufacturing. Please see Application Note AN1724 for similar
information regarding migrating d esigns from the uPSD3200 series to the uPSD3300 series ,
and see AN1773 for migrating from uPSD3300 to uPSD3400 designs.
Pin differences will be presented two categories:
■ Mandatory pin function changes for all applications, and
■ Conditional pin function changes depending on the application.
AN1787
Application note
There are also differences in SFRs and interrupt vectors, which may impact firmware
depending on the application. These differences are identified to help you migrate your
firmware.
For simplicity, the uPSD3200 series will be referred in this document as 3200, and the
uPSD3400 series will be referred to as 3400.
May 2007 Rev 2 1/27
www.st.com
Contents AN1787
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Summary of differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1.1 MCU Core Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1.2 MCU Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1.3 PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1.4 ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1.5 LVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1.6 Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1.7 I/O characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1.8 USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1.9 UART and I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1.10 DDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2 Summary of new uPSD3400 functions . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2.1 USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2.2 MCU Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2.3 MCU core timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2.4 MCU core data pointers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2.5 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2.6 ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2.7 IrDA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2.8 PCA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2.9 JTAG debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2.10 Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2.11 MCU clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2.12 MCU clock division . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2.13 Cross-Bar I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2.14 High Current I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2.15 5V-tolerant I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2 Pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3 Mandatory pin changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1 52-pin Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2 80-pin devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
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AN1787 Contents
4 PC layout suggestions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5 Conditional pin changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.1 PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.2 52-pin devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.3 80-pin devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.4 PC Layout Suggestion for PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.5 ADC, reassigned ADC channel numbers . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.6 ADC voltage scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.7 ADC reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.8 LVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6 Special function register (SFR) differences . . . . . . . . . . . . . . . . . . . . . 22
7 Interrupt vector differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
8 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
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1.1 Summary of differences
1.1.1 MCU Core Voltage
The 3400 MCU core requires a 3.3V supply, even when used in a 5V system. This means
two separate supplies (5V V
supply (3.3V V
V
supply, which is 5V VCC for 5V devices, or 3.3V VCC for 3.3V devices.
CC
1.1.2 MCU Core
The 3200 MCU requires 12 clocks per instruction but t he 3400 uses just 4 clocks. The 3400
does not have an optional 12-clock operation mode. No modifications are needed to 3200
firmware for standard 8032 functions unless timing was established with software loops.
Modifications ARE required for firmware controlling some peripherals when migrating to
3400.
1.1.3 PWM
The five 8-bit PWM channels of the 32 00 are implemented with the Programmable Counter
Array (PCA) in the 3400, which has six 16-bit timer/counter modules. There are new SFRs,
and some PWM pin number assignments have changed on the 3400.
) is required for a 3.3V system. In contrast, 3200 devices use only a single
CC
and 3.3V VCC) are required in a 5V system, but just one
DD
AN1787
1.1.4 ADC
The four 8-bit ADC channels of the 3200 are imple mented using f our of the eigh t 10-bit ADC
channels on the 3400. There are new SFRs, but there are no ADC input pin number
changes. The ADC reference voltage (V
devices and V
have an ADC V
voltage on any 3400 ADC input or reference is V
is shared internally with the 3.3V VCC core supply . 80-pin 3400 devices do
REF
pin, and its maximum input voltage is V
REF
1.1.5 LVD
Both 5V and 3.3V 3400 devices have Low-Voltage Detect (LVD) trip point set for the 3.3V
V
supply level (2.5V). This must be considered when designing 5V systems.
CC
1.1.6 Watchdog
The watchdog timer is enabled after reset on 3200 devices, but it is disabled after reset on
3400 devices.
1.1.7 I/O characteristics
The 3.3V 3400 devices have 5V tolerant I/O on ports 3, and 4, but ports A,B,C, and D are
not 5V tolerant. The 3.3V 3200 devices do not have any 5V tolerant I/O ports.
1.1.8 USB
) input pin is not available on 52-pin 3400
REF
(3.3V). The maximum input
(3.3V) even in a 5V system.
CC
CC
The 3200 supports low-speed USB 1.1 (1.5Mbps), the 3400 supports full-speed USB 2.0
(12Mbps). The 3400 has all new SFRs for the USB channel. Some USB bus pin numbers
have changed between the 3200 and 3400.
4/27
AN1787
1.1.9 UART and I2C
Minor changes to SFR definitions.
1.1.10 DDC
No DDC interface is on the 3400.
1.2 Summary of new uPSD3400 functions
Listed below are new functions on the 3400 that were no t available on the 3300:
1.2.1 USB
The 3400 supports USB 2.0 Full-Speed (12Mbps) and includes the USB physical interface.
There are a total of 5 pair of endpoints (each pair consists of In and Out ). One endpoint pa ir
is for USB Control transfer types, the remaining four endpoint pairs can be used for any
combination of USB Interrupt or USB Bulk transfer types . Each individual e ndpoint has a 64byte FIFO (10 FIFOs total) to maintain USB data throughput.
1.2.2 MCU Core
The 8032 MCU core of the 3400 operates on 4-clo cks per in struction, with a maximum cloc k
rate of 40MHz, yielding 10 MIPS (Million Instructions Per Second) maximum performance
for single-byte instructions. The 3400 MCU core has a 16-bit internal path from memory to
enhance performance, meaning that double-byte instructions are fetched in a single MCU
cycle, which pushes average performance close to the peak performance. No firmware
changes are required to take advantage of this enhancement. In summary, 3400 has 10
MIPS peak performance, but you can e xpect about 9 MIPS a ver age perf ormance, compared
to 3.3 MIPS peak and 3.0 MIPS average performance from the 3200.
1.2.3 MCU core timing
The 3400 Turbo MCU core has a six-deep instruction prefetch queue and a four-way
branching address cache to increase performance. Code in smaller localities operate very
fast. No special firmware is required to take advantage of the prefetch queue or branching
cache. Be aware that firmware timing loops will not be accurate because of the nondeterministic nature of pipeline and cache architecture. Please use one of the many
hardware timer modules to create timing functions, not firmware loops.
1.2.4 MCU core data pointers
The 3400 Turbo MCU core includes dual data pointers to speed data transfers of XDATA.
The pointers can auto-increment and auto-decrement, providing rapid data movement from
source to destination locations. The 3200 has one only data pointer.
1.2.5 SPI
An SPI bus master interface is provided on the 3400.
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1.2.6 ADC
Eight 10-bit ADC inputs are provided, compared to only four 8-bit ADC inputs on the 3200.
1.2.7 IrDA
The 2nd UART channel supports IrDA protocol, which be connected directly to an IR
transceiver.
1.2.8 PCA
The Programmable Co unter Arra y unit has six 16-bit tim er/counter (TC) modules that can be
used for PWM, Capture/Compare, Timers, or Counters. Three of the six TC modules can
operate from one time base , and the ot her three TC modules can oper ate from another time
base if desired. These six TC modules are in addition to the standard th ree 16-bit time r units
inside the 8032 MCU core, bringing a total of nine 16-bit timer/counters. The 3200 provides
only the three standard 16-bit 8032 timers.
1.2.9 JTAG debug
The JTAG port now functions as a debug port in addition to In-System Programming (ISP).
This eliminates the need for conventional hardware In-Circuit Emulation (ICE) tools.
AN1787
1.2.10 Debug
The 3400 has a dedicated debug input/ output pin. As an output, it ca n signal that a specified
debug ev en t has occurred, as an input it can t rigger a debu g e v ent to begin (e .g., bre akpoint
or trace)
1.2.11 MCU clock
3.3V 3400 devices can be clocked up to 40MHz, unlike 3.3V 3200 with 24MHz maximum.
1.2.12 MCU clock division
The 8032 MCU clock can be divided internally for lower power operation. The MCU may
change the clock divider ratio on-the-fly using SFRs. This affects the MCU only, not
peripheral clocks.
1.2.13 Cross-Bar I/O
Peripheral functions on Port 1 are also av ailab le on P ort 4 (cross-bar s witch), pro viding more
flexibility. There is no need to sacrifice one peripheral function when two functions are
available on a single pin, just use the other port.
1.2.14 High Current I/O
Eight I/O pins on Port 4 are each capable of sinking or sourcing 10mA for both, 3.3V and
5.0V 3400. In contrast, 3.3V 3200 pins ar e cap able of sinking 4mA each, while the 5V 3200
can sink 8mA each.
6/27
AN1787
1.2.15 5V-tolerant I/O
The following pins are 5V tolerant on 3.3V, 52-pin 3400 devices: P1.1 through P1.7, P3.1
through P3.7, P4.1 through P4.7, and RESET_IN_.
On 3.3V, 80-pin 3400 devices, the following pins are also 5V tolerant: MCU_AD0 through
MCU_AD7, RD_, WR_, and _PSEN. In contrast, 3.3V 3200 devices had no 5V tolerant I/O
pins.
Note: PSD functions have NOT changed from the 3200 to 3400. These funct ions include PLD,
memory mapping, memory management (code space vs. data space, and pagin g), Flash
memories, SRAM memory, and PSD I/O. The wider 16-bit internal data path on the 3400
(compared to 8-bit path on 3200) is transparent to the user.
Please note the SRAM on the 3400 can not be configured to reside in code space.
7/27
Pin definitions AN1787
2 Pin definitions
Figure 1 and Figure 2 show pin assignments of the 3200 and 3400 devices in both 52-pin
and 80-pin TQFP packages. Please see the 3200 and 3400 data sheets for detailed pin
function descriptions and physical dimensions of packages. Pins requiring mandatory
changes during migration are darkened in the figur es, this assume s that USB will be used in
both the 3200 and 3400 applications.
Note: 5V 3200 devices support USB while the 3.3V 3200 devices do NOT support USB.
Figure 1. uPSD3200 52-pin TQFP pin definition
REF
GND
RESET
PB6
PB7
P1.7/ADC3
PB0
PB1
PB2
PB3
PB4
PB5
V
52515049484746454443424140
P1.6/ADC2
PD1/CLKIN
PC7
JTAG TDO
JTAG TDI
USB–
PC4/TERR
USB+
V
GND
PC3/TSTAT
PC2/V
STBY
JTAG TCK
JTAG TMS
1
2
3
4
5
6
7
8
CC
9
10
11
12
13
14151617181920212223242526
P4.7/PWM4
P4.6/PWM3
P4.5/PWM2
P4.4/PWM1
uPSD32XX
52-pin TQFP
SYNC
GND
P4.3/PWM0
P4.1/DDC SCL
P4.2/DDC V
P3.1/TXD
P3.0/RXD
P4.0/DDC SDA
P3.2/EXINT0
P3.3/EXINT1
39 P1.5/ADC1
38 P1.4/ADC0
37 P1.3/TXD1
36 P1.2/RXD1
35 P1.1/T2X
34 P1.0/T2
33 V
CC
32 XTAL2
31 XTAL1
30 P3.7/SCL1
29 P3.6/SDA1
28 P3.5/T1
27 P3.4/T0
AI08885
8/27
AN1787 Pin definitions
Figure 2. uPSD3400 52-pin TQFP pin definition
/ADC6
/ADC7
(2)
RESET_IN_
PB6
PB7
(2)
P1.6/SPITXD
P1.7/SPISEL
(3)
REF
/V
CC
PB5
PB0
PB1
PB2
PB3
PB4
AV
GND
52515049484746454443424140
(1)
(2)
2
CSCL
2
CSDA
(2)
/ADC1
/ADC0
(2)
(2)
/ADC5
/ADC4
(2)
(2)
/ADC3
/ADC2
PD1/CLKIN
PC7
JTAG TDO
JTAG TDI
DEBUG
3.3V V
USB+
V
DD
GND
USB–
PC2/V
STBY
JTAG TCK
JTAG TMS
1
2
3
4
5
6
CC
7
(1)
8
uPSD34XX
52-pin TQFP
9
10
11
12
13
39 P1.5/SPIRXD
38 P1.4/SPICLK
37 P1.3/TXD1(IrDA)
36 P1.2/RXD1(IrDA)
35 P1.1/T2X
34 P1.0/T2
33 V
DD
32 XTAL2
31 XTAL1
30 P3.7/I
29 P3.6/I
28 P3.5/C1
27 P3.4/C0
14151617181920212223242526
GND
/TCM5/P4.6
/TCM4/P4.5
/TCM3/P4.4
(2)
(2)
(2)
/PCACLK1/P4.7
(2)
SPICLK
SPITXD
SPIRXD
SPISEL_
1. For 5V applications, VDD must be connected to 5.0V source. For 3.3V applications, VDD must be
connected to a 3.3V source.
/TCM2/P4.2
/TCM1/P4.1
(2)
(2)
/PCACLK0/P4.3
(2)
T2X
RXD1(IrDA)
TXD1(IrDA)
/TCM0/P4.0
(2)
T2
EXTINT0/TG0/P3.2
EXTINT1/TG1/P3.3
AI08887
TXD0/P3.1
RXD0/P3.0
2. These signals can be used on one of two different ports (Port 1 or Port 4) for flexibility. Default is Port 1.
3. V
and 3.3V AVCC are shared. ADC channels must use 3.3V as V
REF
for 52-pin package.
REF
9/27
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