ST AN1782 Application note

AN1782

APPLICATION NOTE

STR71X I2C

COMMUNICATION WITH M24CXX EEPROM

INTRODUCTION

This application note gives an example of how to use the STR71x I2C peripheral to communi­cate with an I2C Protocol-Compatible Electrically Erasable Programmable Read Only Mem­ory (EEPROM). The example uses the M24C08 EEPROM from STMicroelectronics.
The implemented software manages read and write operations between the STR71x I2C
interface and the M24C08.

1 STR71X I2C PERIPHERAL

The STR71x I2C peripheral provides both multi master and slave functions, and controls all
I2C bus-specific sequencing, protocol, arbitration and timing. It also provides the transfer
problem detection feature. The speed of the I2C interface may be selected between standard
(0-100KHz) and fast I2C (100-400KHz).

The STR71x provides two I2C interfaces I2C0 and I2C1.

Only the master characteristics of the STR71x I2C are needed to manage the communication
sequencing with EEPROM, which acts as a slave.

In this application, only the single master mode is used without error management.

To implement the I2C protocol, only 2 bidirectional lines are required, SCL (Serial Clock Line),
which carries the synchronization clock and SDA (Serial Data Line), which carries the bit to be
transmitted. This line is driven by the device that sends the data.

The corresponding port pins have to be configured as alternate function open drain.

Please refer to the STR71x reference manual for more details.

2 M24CXX EEPROM

The M24Cxx families of EEPROM are compatible with the I2C protocol. This EEPROM family
includes a range of different devices. Table 1 displays the size, the number of devices that can
be connected to the I2C bus and the number of blocks in each device.

Table 1. M24Cxx EEPROMs family characteristics

Device Size (Kbit) Devices per Bus Number of Blocks

M24C01 1 8 1

Rev. 2.0

AN1782/0905 1/7

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I2C COMMUNICATION BETWEEN STR71X AND M24CXX EEPROM

Device Size (Kbit) Devices per Bus Number of Blocks

M24C02 2 8 1

M24C04 4 4 2

M24C08 8 2 4

M24C016 16 1 8

3 STR71X/M24C08 COMMUNICATION APPLICATION

3.1 HARDWARE CONFIGURATION

Two M24C08 memory chips can be addressed by a microcontroller on the same two wire bus
by configuring the M24C08 input E2. In this application the M24C08 E0, E1 and E2 inputs are
tied to V3.3 via 10K resistor. The M24C08 is divided into four blocks defined by the two LSB
bits of the memory address defined on the following:

■ M24C08_Block0 ==> ADDRESS 0xA8

■ M24C08_Block1 ==> ADDRESS 0xAA

■ M24C08_Block2 ==> ADDRESS 0xAC

■ M24C08_Block3 ==> ADDRESS 0xAE

Figure 1. STR71x/M24C08 configuration

STR71x

SDA

SCL

V3.3

4K7

4K7

100

100

SDA

SCL

M24C08

E2

E1

E0

V3.3

10K

10K

10K

3.2 SOFTWARE IMPLEMENTATION

In this application note the software modules are developed in C language, with RVDK envi-

ronment.

The software implemented to manage read and write operations between the STR71x I2C

interface and the M24C08 is divided in three parts:
– Write: first, the program writes the contents of a predefined buffer to the memory starting

from address 0x00 of Block3,

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I2C COMMUNICATION BETWEEN STR71X AND M24CXX EEPROM

– Wait: then, it waits until the write operation is finished,

– Read: finally it reads the data already written.

3.2.1 Write Operation

Before starting the communication, the I2C bus must be in the free state (SCL and SDA must
be HIGH). The write sequence is started by getting control of the bus. This action, which puts
the bus in busy state, is performed by setting the START bit in the Control Register (CR) in
order to generate a START Condition. Then the slave address is written in the Data Register
(DR) with the R/Wbit=0. This causes the address to be sent to the slave. The address trans­mission check is done by looping on the ENDAD flag in Status Register2 (SR2). This flag is
cleared by writing 0x20 in the Control Register (CR).

Then the master starts sending the data byte by writing it in the Data Register (DR). To
transmit a new data byte, the address or the data byte previously transmitted has to be com­pleted correctly. The previous transmission check is done by looping on the BTF flag in Status
Register 1 (SR1). This flag is cleared by writing the next byte to be sent in the Data Register.
The first byte to be sent is the start address of the destination of the data.

A maximum of 16 bytes can be written to the M24C08 in a single write cycle.

The write sequence is ended by generating a STOP condition, by setting the STOP bit in the
Control Register (CR). This action releases the bus.

The following flowchart shows the different steps of the write cycle.

Figure 2. Write Operation Flowchart

Begin

Generate START Condition

Send Slave Address((R/W)bit=0)

Send the EEPROM’s internal

address to write to

Send String

Generate STOP Condition

End

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