ST AN1775 Application note

AN1775

APPLICATION NOTE

STR71x Hardware Development

Getting Started

Introduction

This application note is intended for system designers who require a hardware implementation overview of the development board features such as the power supply, the clock management, the reset control, the boot mode settings and the debug management. It shows how to use the STR71x product family and describes the minimum hardware resources required to develop an STR71x application.

Detailed reference design schematics are also contained in this document with descriptions of the main components, interfaces and modes.

Rev 3

October 2005 1/27

www.st.com

AN1775

Contents

1 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.2 Power management block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.1 Clock control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.2 Real Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.3 USB clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.3.1 Hardware implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3 Reset management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4 Boot management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

5 Debug management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

5.1 ICE debug tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

5.2 JTAG / ICE connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

6 Reference Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.1 Main . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.1.1 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.1.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.1.3 Boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.1.4 Wake-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.2 Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.3 USB full speed interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.4 CAN interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6.5 RS232 serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6.6 Serial ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6.6.1 SPI Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6.6.2 I2C EEPROM: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6.7 JTAG interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6.8 SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

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AN1775

6.9 Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6.10 LCD interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6.11 Conclusions and recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

7 Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

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1 Power management AN1775

1 Power management

1.1 Overview

The chip is powered by an external 3V3 supply(V33: 2.7 to 3.6 V, AVDD: 3.0 to 3.6 V).

All I/Os are 3V3-capable. An internal Voltage Regulator generates the supply voltage for core logic (~=1.8V). The two V following figure indicates the recommended configuration for the power supply pins:

Figure 1. STR71x power supply pins

pins must be connected to external stabilization capacitors. The

3V3

10µF

33nF

GND

1µF

GND

1.2 Power management block

The following figure describes the power management block implemented on the STR71x devices.

Figure 2. Power Management Block

3V3

33nF

10µF

Main Voltage

Regulator (MVR)

1.8 V

33IO-PLL

18BKP

3.3 V

STR71x

SSIO-PLL

SSBKP

Low Power Voltage

Regulator (LPVR)

GND

I/O circuitry

CORE

GND

18BKP

1µF

switch

see note 1

GND

The STR71x power management block has two regulators:

● The Main Voltage Regulator MVR.

● The Low Power Voltage Regulator LPVR.

Note the following remarks about the two regulators:

● Both regulators can be switched-off by software

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Backup block

AN1775 1 Power management

● V18 can be used to supply an externally regulated 1.8V, but V33 must supply the IOs

● V18BKP pin can be used to externally supply the backup logic, but V33 must supply the

IOs

● The switch in Figure 2, opened only during STANDBY mode, disconnects the V

from the V

18BKP

domain

It is possible to switch-off the MVR and keep LPVR on when the device is in low-power mode (SLOW, WFI, LPWFI, STOP or STANDBY). The LPVR has a different design from the main VR and generates a non-stabilized and non-thermally-compensated voltage of approximately 1.6V.

In STANDBY mode the Low Power VR can be switched off when an external regulator provides a 1.8V supply to the chip through the V

18BKP pin for use by RTC and Wake-Up block.

In this case we must to keep the 3.3V on pin V33 even if the two regulators are switch off to keep stable state on the I/Os.

Remark:The PLL is automatically disabled (PLL off) when the MVR is switched off and the maximum allowed operating frequency is 1 MHz. This is due to the limitation imposed by the LPVR which is not able to generate sufficient current to operate in run mode.

domain

The MAIN DEVICE CORE is powered from an external 3V3 power supply pin (V main regulator.

For more details on the power regulators, refer to the STR71x Reference Manual.

) through the

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2 Clock management AN1775

2 Clock management

The STR71x offers a flexible way for selecting core and peripherals clocks, the devices have up to 3 external clock sources:

● The PRCCU generates the internal clocks for the CPU and for the on-chip peripherals.

The PRCCU may be driven by an external pulse generator, connected to the CK pin.

● The Real time Clock 32kHz oscillator is connected to the internal CK_AF signal (if present

on the application), and this clock source may be selected when low power operation is required.

● USB clock source available only with devices with USB feature.

2.1 Clock control unit

The STR71x clock control unit must be driven by an external oscillator, connected to the CK pin, at a frequency of up to 16 MHz. It generates the clocks for the CPU and for the on-chip peripherals. A range of available multiplication and division factors allows for a large number of operating clock frequencies to be driven from the input frequency. However, great care must be taken to respect the recommendations for allowed frequency limits. For more details on allowed operating frequencies for each clock, refer to the Reference Manual.

The following diagram shows the basic implementation of the main external clock.

Figure 3. Main clock oscillator

10K

3V3

The following table gives frequency range examples of the Main clock for some input clock values:

Input Clock MCLK (Main Clock) Range

4 MHz [15625 Hz, 50 MHz]

8 MHz [31250 Hz, 50 MHz]

16 MHz [62500 Hz, 50MHz]

2.2 Real Time Clock

The Real Time Clock operates at a speed of 32 kHz. This clock must be provided by an external resonator circuitry.

OSCILLATOR

GND

STR71x

VSS

GND

The RTC is used to generate a time base, and can be selected when low power operation is needed. Refer to the Reference Manual for more details.

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AN1775 2 Clock management

Figure 4. RTC oscillator

STR71x

32kHz CRYSTAL

15pF*

GND

* these values are given only as examples, refer to the crystal manufacturer for more details

15pF*

GND

RTCXTI RTCXTO

2.3 USB clock

STR710 and STR711 series microcontrollers contain a USB 2.0 Full Speed device module interface that operates at a precise frequency of 48 MHz. This clock is usually provided by an external oscillator connected to the USB clock pin USBCLK. However, to save the board’s space and cost, the 48MHz USB clock can also be generated by the internal PLL2 using one single external oscillator for both system and USB module.

This part of the application note describes the hardware and software reference implementation. USB Full Speed signal quality and jitter results can be measured using a single external oscillator to generate not only the System PLL clock and Peripheral’s clocks, but also the 48MHz USB clock.

2.3.1 Hardware implementation

The hardware implementation guidelines are described in the figure below.

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2 Clock management AN1775

Figure 5. USB clock and pins implementation

47K

USB Indicate

56K

BC547E

GND

USB connector

STR710/STR711

GPIO

USB CLK

1K5

0 Ohm

GND

15pF

GND

56K

GND

Vbus

D+

D-

56K

48MHz Oscillator

GND

USB full speed interface device supported via type B connector. The USB clock uses a separate 48 MHz oscillator.

Transistor circuit used to indicate the cable status (Cable connected USB/IND pin = 0 logic, Cable deconnected = USB/IND pin = 1 logic).

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AN1775 3 Reset management

3 Reset management

Both the Main Voltage Regulator and the Low Power Voltage Regulator contain an LVD.

They keep the device under reset when the corresponding controlled voltage value (V V

falls below 1.35V±10%).

18BKP

The LVDs do not monitor V33 which supplies the I/O and analog parts of the device.

Note: During power-on, a reset must be provided externally.

At power on, the nRSTIN pin must be held low by an external reset circuit until V

Figure 6 gives an example of the hardware implementation of the RESET circuit for STR71x

devices.

● The STM1001 low-power CMOS microprocessor supervisory circuit is used to assert a

reset signal whenever the V

voltage falls below a preset threshold or a manual reset is

asserted.

Figure 6. Hardware reset implementation

STR71x

nRSTIN

* these values are given only as typical example

+3V3

GND

+3V3

Reset_PB

GND

2K2

not Reset VCC

1nF

+3V08

STM1001T

GND

+3V3

GND

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