ST AN1762 APPLICATION NOTE
AN1762
APPLICATION NOTE
L6205, L6206, L6207 DUAL FULL BRIDGE DRIVERS
by Vincenzo Marano
Modern motion control applications need more flexibility that can be addressed only with specialized IC
products. The L6205, L6206, L6207 are dual full bridge drivers ICs specifically developed to drive a wide
range of motors. These ICs are one-chip cost effective solutions that include several unique circuit design
features. These features allow the devices to be used in many applications including DC and stepper motor
driving. The principal aim of this development project was to produce easy to use, ful ly protected pow er ICs.
In addition several k ey functi ons s uch as pr otection circuit and PW M current c ontrol drastic ally r educe external components count to meet requirements for many different applications.
1 INTRODUCTION
The L6205, L6206, L6207 are highly integrated, mixed-signal power ICs that allow the user to easily design a
control system for two-phase bipolar stepper motors, multiple DC motors and a wide range of inductive loads.
Figure 1 to Figure 3 show the L6205, L6206, L6207 block di agrams. Each IC integrates eight Power DMOS pl us
other added features for safe operation and flexibility. The L6207 also features a constant t
control technique (
Synchronous mode
) for each of the two full bridges.
PWM current
OFF
Figure 1. L6205 block diagram.
VBOOT
VCP
EN
IN1
IN2
EN
IN1
IN2
A
A
A
B
B
B
V
BOOT
CHARGE
PUMP
VOLTAGE
REGULA TOR
OCD
THERMAL
PROTECTION
10V
5V
OCD
A
B
OVER
CURRENT
DETECTION
GA TE
LOGIC
OVER
CURRENT
DETECTION
GA TE
LOGIC
V
BOOT
10V 10V
V
BOOT
BRIDGE A
BRIDGE B
D99IN1091A
VS
A
OUT1
OUT2
SENSE
V
S
B
OUT1
OUT2
SENSE
A
A
A
B
B
B
December 2003
1/53
AN1762 APPLICATION NOTE
Figure 2. L6206 block diagram.
VBOOT
VCP
PROGCL
OCD
EN
IN1
IN2
OCD
A
A
A
A
A
B
V
BOOT
CHARGE
PUMP
VOLTAGE
REGULA TOR
OCD
THERMAL
PROTECTION
10V
5V
OCD
PROGCL
B
EN
B
IN1
B
IN2
B
Figure 3. L6207 block diagram.
VS
V
BOOT
OVER
A
CURRENT
DETECTION
V
BOOT
10V 10V
GA TE
LOGIC
A
OUT1
OUT2
SENSE
A
A
A
BRIDGE A
OVER
B
CURRENT
DETECTION
GA TE
LOGIC
V
S
B
OUT1
OUT2
SENSE
B
B
B
BRIDGE B
D99IN1088A
VBOOT
VCP
EN
IN1
IN2
EN
IN1
IN2
A
A
A
B
B
B
V
BOOT
CHARGE
PUMP
PROTECTION
VOLTAGE
REGULATOR
5V10V
THERMAL
OCD
OCD
VS
V
BOOT
A
OVER
CURRENT
DETECTION
V
BOOT
10V 10V
GATE
LOGIC
A
OUT1
OUT2
SENSE
A
A
A
PWM
BRIDGE A
+
-
VREF
RC
A
V
S
B
OUT1
OUT2
SENSE
VREF
RC
B
A
B
B
B
B
ONE SHOT
MONOSTABLE
OVER
CURRENT
B
DETECTION
GATE
LOGIC
MASKING
TIME
SENSE
COMPARATOR
BRIDGE B
D99IN1085A
2/53
AN1762 APPLICATION NOTE
Table of Contents
1 INTRODUCTION................................................................................................................................ 1
2 MAIN DIFFERENCES BETWEEN L6205, L6206 , L6207 ..................................................................4
3 DESIGNING AN AP PLICATI ON WITH L6205, L6206, L6207 ...........................................................4
3.1 Current Ratings........................................................................................................................4
3.2 Voltage Rating s and Operating Range ....................................................................................4
3.3 Choosing th e Bulk Capacitor....................................................................................................6
3.4 Layout Considerations.............................................................................................................7
3.5 Sensing Resisto r s.............................. ......................................................... ..................... ....... .9
3.6 Charge pump external components.......................................................................................10
3.7 Sharing the Charge Pump Circuitry .......................................................................................11
3.8 Reference Voltage for PWM Current Control (L6207 ONLY).................................................12
3.9 Input Logic pins......................................................................................................................13
3.10 EN pins...................................................................................................................................13
3.11 Program mab le off-time Monost able (L6207 ON LY)..............................................................14
3.11.1 Off-time Selection and minimum on-time (L6207 ONLY) ................................................16
3.11.2 Slow Decay Mode (L6207 ONLY) ...................................................................................17
3.12 Over Current Protection........................................................................................................18
3.13 Adjusting the Over Current Detection trip point (L6206 ONLY)............................................21
3.14 Paralleling two Full Bridges...................................................................................................23
3.14.1 Paralleling two Full Bridges to get a single Full Bridge ....................................................23
3.14.2Paralleling the four Half Bridges to get a single Half Bridge.............................................26
3.15 Power Managem ent..............................................................................................................27
3.15.1 Maximum output current vs. selectable devices..............................................................27
3.15.2 Power Dissipation Formulae for different sequences......................................................28
4 APPLICATION EXAMPLE (L6207)..................................................................................................32
4.1 Decay mode, sensing resistors and reference voltage..........................................................32
5 APPENDIX - EVALUATI ON BO ARD S...................................................................... .......................33
5.1 PractiSPIN............................................................................. .................................................33
5.2 EVAL6205N ...........................................................................................................................34
5.2.1 Important Not e s......... ................................... ......................................................... ....... ....35
5.3 EVAL6206N ...........................................................................................................................39
5.3.1 Important Not e s......... ................................... ......................................................... ....... ....40
5.4 EVAL6206PD.........................................................................................................................44
5.4.1 Important Not e s......... ................................... ......................................................... ....... ....45
5.5 EVAL6207N ...........................................................................................................................49
5.5.1 Important Not e s......... ................................... ......................................................... ....... ....50
6 REFERENCES....................................................................................... ..........................................53
3/53
AN1762 APPLICATION NOTE
2 MAIN DIFFERENCES BETWEEN L6205 , L6206, L6207
L6205, L6206 and L6207 are DMOS Dual Full Bridge ICs.
L6205 (see Figure 1) includes logic for CMOS/TTL interface, a charge pump that provide auxiliary voltage to
drive the high-side DMOS, non dissipative over current protection circuitry on the high-side DMOS, with fixed
trip point set at 5.6 A (see
Out for reliable start-up.
In addition, L6206 gives the possibility of adjusting the trip point of the over current protection for each of the
two full-bridges (through two external resistors), and its internal open-drain mosfets (see
tion
Section) are not internally connected to EN pins but to separate
tics and overcurrent management.
L6207 has Over Current protection function with fixed trip point set at 5.6 A and internal open-drain mosfets
connected to
bridges (see
EN
pins, as the L6205, but it also integrates two PWM current controller for each of the two full-
Programmable off-time Monostable
3 DESIGNING AN APPLICATION WITH L6205, L6206, L6207
3.1 Current Ratings
With MOSFET (DMOS) devices, unlike bipolar transistors, current under short circuit conditions is, at first approximation, limited by the R
L6207
Out
pins and the two VSA and VSB pins are rated for a maximum of 2.8A r.m.s. and 5.6A peak (typical
values), corresponding to a total (for the whole IC) 5.6A rms (11.2A peak). These values are meant to avoid
damaging metal structures, including the metallization on the die and bond wires. In practical applications,
though, maximum allowable current is less than these values, due to power dissipation limits (
Management
section
against short circuits between the outputs and between an output and ground (
sect ion
).
Over Current Protection
Section), over temperature protection, Under Voltage Lock-
Over Current Protec-
OCD
pins,
allowing eas ier external dia gnos-
section).
of the DMOS themselves and could reach very high values. L6205, L6206,
DS(ON)
see
Powe r
). The devices have a built-in Over Current Detection (OCD) that provides protection
see
Over Current Protection
3.2 Voltage Ratings and Operating Range
The L6205, L6206, L6207 requires a si ngle supply voltage (VS), for the motor supply. Internal voltag e regulators
provide the 5V and 10V required for the internal circuitry. The operating range for V
working into undesirable low supply volt age an
when supply voltage falls below 6V; to resume normal oper ating condi tions, V
Under Vol tage Lock Out
(
UVLO
must then exceed 7V. The hys-
S
teresis is provided to avoid false intervention of the UVLO function during fast V
however, that DMOS's R
R
is adversely affected, and this is particularly true for the High Side DMOS that are driven from V
DS(ON)
is a function of the VS supply voltage. Actually, when VS is less than 10V,
DS(ON)
is 8 to 52V. To prevent
S
) circuit shuts down the device
ringings. It should be noted,
S
BOOT
supply. This supply is obtained through a charge pump from the internal 10V supply, which will tend to reduce
its output voltage when V
(V
4/53
- VS) versus the supply voltage (VS).
BOOT
goes below 10V. Figure 4 shows the supply voltage of the high side gate drivers
S
AN1762 APPLICATION NOTE
Figure 4. High side gate drivers supply voltage versus supply volta ge.
8
7.6
V
- V
BOOT
[V]
Note that VS must be connected to both VSA and VSB since the bootstrap voltage (at V
7.2
S
6.8
6.4
6
8 8.5 9 9.5 10 10.5
[V]
V
S
pin) is the same for
BOOT
the two H-bridges. The integrated DMOS have a rated Drain-Source breakdown voltage of 60V. However V
should be kept below 52V, since in normal working conditions the DMOS see a Vds voltage that will exceed V
supply. In particular, during a phase change ( when each output of the same H-bridge sw itches from VS to GND
or vice versa, for example to reverse the current in the load) at the beginning of the dead-time (when all the
DMOS are off) the
path from the pin to GND. This spike is followed by a stable negative voltage due to the drop on R
of the two
OUT
SENSE
pin sees a negative spike due to a not negligible parasitic inductance of the PCB
. One
SENSE
pins of the bridge sees a similar behavior, but with a slightly larger voltage due to the forward
recovery time of the integrated freewheeling di ode and the forward voltage drop ac ross it (see Figure 5). Typical
duration of this spike is 30ns . At the same time, the other
OUT
pin of the same bridge sees a vol tage above VS,
due to the PCB in ductance and v oltage drop across the h igh-side ( integrated) freewheeling diode, as the current
reverses direction and flows into the bulk capacitor. It turns out that the highest differential voltage can be observed between the two
OUT
pins of the same bridge, during the dead-time at a phase change, and this must
always be kept below 60V [3].
S
S
Figure 5. Currents and voltages during the
PCB Parasitic
Inductance
R
*I+V
SENSE
R
SENSE
Bulk Capacitor
Equivalent Circuit
ESR
ESL
dead time
F(Diode)
*I
SENSE
at a phase change.
V
S
OUT
OUT
Dangerous
High Differential Voltage
PCB Par a s i ti c
R
SENSE
Inductan ce
2
1
VS+V
F(Diode)
5/53
AN1762 APPLICATION NOTE
Figure 6 shows the voltage waveform s at the two OUT pins referring to a pos sible pr actical situ ation, with a peak
output current of 2.8A, V
ground spike amplitude is -2.65V for one output; the other
differential voltage reaches almost 60V, which is the a bsolute max imum rating for the DMOS. Keepi ng differential voltage between two Output pins belonging to the same Full Bridge within rated values is a must that can
be accomplished with proper selection of Bulk capacitor value and equivalent series resistance (ESR), according to current peaks and chopping style and adopting good layout practices to minimize PCB parasitic inductances (see below) [3].
= 52V, R
S
= 0.33Ω, TJ = 25°C (approximately) and a good PCB layout. Below
SENSE
OUT
pin is at about 57V . In these conditions, total
Figure 6. Vol ta ge a t th e tw o outputs duri ng the
Out 1
Out 2
dead time
at a phase change.
3.3 Choosing the Bulk Capacitor
Since the bulk capacitor, placed between VS and
AC current capability
must be greater than the r.m.s. value of the charge/discharge current. In the case of a
PWM current regulation, the current flows from the capacitor to the IC during the on-time (t
GND
pins, is charged and discharged during IC operation, its
) and from the IC
ON
(implementing a fast decay current recirculation technique) or from the power supply (implementing a slow decay current recirculation technique) to the capacitor during the off-time (t
). The r.m.s. value of the current
OFF
flowing into the bulk capacito r depends on peak output curr ent, outp ut current r ippl e, switchin g fr equency, dutycycle and chopping style. It also depends on power supply characteristics. A power supply with poor high frequency performances (or long, inductive connections to the IC) will cause the bulk capacitor to be recharged
slowly: the higher the current control switching frequency, the higher the current ripple in the capacitor; r.m.s.
current in the capacitor, however, does not exceed the r.m.s. output current. Bulk capacitor value (
ESR
determine the amount of voltage ripple on the capacitor itself and on the IC. In slow decay, neglecting the
dead-time
power supply, the voltage at the end of the
and output current ripple, and assumin g that during the
on-time
is:
on-time
the capacitor is not recharged by the
C
) and the
so the supply voltage ripple is:
6/53
VSI
– ESR
OUT
I
⋅
OUT
t
t
---------+
ON
C
-------- -+
ON
C
,
,
⋅
ESR
AN1762 APPLICATION NOTE
where I
is the output current. With fast decay, i nstead, recirculating curr ent recharges the capacitor , causing
OUT
the supply voltage to exceed the nominal voltage. This can be very dangerous if the nominal supply voltage is
close to the maximum recommended supply voltage (52V). In fast decay the supply voltage ripple is about:
t
+
I
OUT
2 ESR⋅
⋅
ONtOFF
--------------------------- -+
C
,
always assuming that the power supply does not recharge the capacitor, and neglecting the output current ripple
and the dead-time. Usually (if C > 100 µF) the capacitance role is much less than the ESR, then supply v oltage
ripple can be estimated as:
I
· ESR in slow decay
OUT
2 · I
For Example, if a maximum ri pple of 500mV is all owed and I
0.5V
ESR
------------
< 250mΩ=
1
---
2
Actually, current sunk by V
ESR
and VSB pins of the device is subject to higher peaks due to reverse recovery
SA
· ESR in fast decay
OUT
2A
0.5V
------------
⋅< 125mΩ=
2A
= 2A, the capacitor ESR should be lower than:
OUT
in slow decay, and
in fast decay.
charge of internal freewheeling diodes. Duration of these peaks is, tough, very short, and can be filtered using
a small value (100÷200 nF), good quality ceramic capacitor, connected as close as possible to the V
and GND pins of the IC. Bulk capacitor will be chosen with
maximum operating voltage
25% greater than the
SA
, V
SB
maximum supply voltage, considering also power supply tolerances. For example, with a 48V nominal power
supply, with 5% tol erance, maximum voltage is 50.4V, then operati ng voltage for the capacitor should be at least
63V.
3.4 Layout Considerations
Working with devices that combine high power switches and control logic in the same IC, careful attention has
to be paid to the PCB lay out. In extreme cases, Power DMOS commutation can i nduce nois es that could c ause
improper operation in the logic section of the device. Noise can be radiated by high dv/dt nodes or high di/dt
paths, or conducted through G ND or Supply connectio ns. Logic connec tions, es pecial ly hi gh-i mpedance nodes
(actually all logic inputs, see furt her), must be kept far from switching nodes and paths. With the L6205, L6206,
L6207, in particular, external components for the charge pump circuitry should be connected together through
short paths, since these components are subject to voltage and current switching at relatively high frequency
(600kHz). Primary mean in minimizing conducted noise is working on a good GND layout (see Figure 7).
7/53
AN1762 APPLICATION NOTE
Figure 7. Typ ic a l App li ca ti on and Layout suggest io ns.
Motors or
other loads
D1
D2
C1
R1
C4
OUT
OUT
OUT
1A
2A
V
OUT
1B
2B
BOOT
CP
L6205, L6206, L6207
V
SA VSB
SENSE
A
SENSE
B
RS1 RS2
C2
+
C3
VS = 8 ÷ 52 V
-
GND
GND
Logic
GND
High current GND tracks (i.e. the tracks connected to the sensing resistors) must be connected directly to the
negative terminal of the bulk capacitor. A good quality, high-frequency bypass capacitor is also required (typically a 100nF÷200nF ceramic would suffice), since electrolytic capacitors show a poor high frequency performance. Both bulk electrolytic and high frequency bypass capacitors have to be connected with short tracks to
V
, VSB and GND. On the L6205, L6206, L6207 GND pins are the
SA
flows through them. Logic GND and Power GND should be connected together in a
pacitor, to keep noise in the Power GND from affecting Logic GND. Specific care should be paid layouting the
path from the
SENSE
pins through the sensing resistors to the negative terminal of the bulk capacitor (Power
Ground). These tracks must be as short as possible in order to minimize parasitic inductances that can cause
dangerous voltage spikes on
for the same reason the capacitors on V
SENSE
and
OUT
, VSB and GND should be very close to the GND and supply pins.
SA
Refer to the Sensing Resistors section for information on selecting the sense resistors. Traces that connect to
, VSB, SENSEA, SENSEB, and the four
V
SA
OUT
are flowing through these traces, and layer changes should be avoided. Should a layer change prove necessary, multiple and large via holes have to be used. A wide GND copper area can be used to improve power
dissipation for the device.
Figure 8 shows two typical situations that must be avoided. An important consideration about the location of the
bulk capacitors is the abi lity to abs orb the inductiv e ener gy from the load, without all owing the s upply v oltage to
exceed the maximum rating. The diode shown in Figure 8 prevents the recirculation current from reaching the
capacitors and will res ult in a high voltage on the IC pins th at can destroy the device. H aving a switch or a power
connection that can dis connect the c apacitors from the IC, w hile there is stil l c ur rent in the motor, will a lso result
in a high voltage transient since there is no capacitance to absorb the recirculation current.
GND
GND
pins (see the
Logic
GND, since only the quies cent current
single point
Voltage Ratings and Operating Range
, the bulk ca-
section);
pins must be designed with adequate width, since high currents
8/53
Figure 8. Two situations that must be avoided.
V
SA VSB
SENSE
A
SENSE
B
L6205, L6206, L6207
GND
GND
GND
GND
R5
C6
DON’T conne ct the Logic GND here
Voltage drop due to current in s ense
path can disturb lo gic GND.
AN1762 APPLICATION NOTE
DON’T put a di ode here!
Recircul at ing current cannot flow into t he
bulk cap ac itor and causes a high voltage
spike that c an des troy the I C .
+
C7
VS = 8 ÷ 52 V
-
3.5 S en sing Resistors
Each motor winding current is flowing through the corresponding sensing resistor, causing a voltage drop that
can be used, by the logic (integrated in the L6207; an external logic can be used with L6205 and L6206), to
control the peak value of the load current. Two issues must be taken into account when choosing the R
SENSE
value:
– The sensing resistor dissipates energy and provides dangerous negative voltages on the
SENSE
pin
during the current recirculation. For this reason the resistance of this component should be kept low.
– The voltage drop across R
parator (L6207 only). The lo wer is the R
on Vref pin and to the input offset of the current sense comparator: too small values of R
is compared with a reference voltage (on V
SENSE
value, the higher is the peak current error due to noise
SENSE
pin) by the internal com-
ref
must be
SENSE
avoided.
A good compromise is calculating the sensi ng resistor value so that the voltage drop , corresponding to the peak
current in the load (I
), is about 0.5 V: R
peak
SENSE
= 0.5 V / I
peak
.
It should be clear that sensing resistor must absolutely be non-inductive type in order to avoid dangerous negative spikes on
SENSE
pins. Wire-wounded resistors c annot be used here, whi le Metall ic film res istor s are recommended for their high peak current capability and low inductance. For the same reason the connections
between the
(see also the
SENSE
pins, C6, C7, VSA, VSB and
Layout Considerations
section).
GND
pins (see Figure 7) must be taken as short as possible
The average power dissipated by the sensing resistor is:
Fast Decay Recirculation: P
R
Slow Decay Recirculation: PR ≈ I
≈ I
rms
rms
2
2
· R
· R
SENSE
SEN SE
· D,
D is the duty-cycle of the PWM current control, I
is the r.m.s. value of the load current.
rms
9/53
AN1762 APPLICATION NOTE
Nevertheless, sensing resistor power rating should be chosen taking into account the peak value of the dissipated power:
where I
is the peak value of the load current.
pk
PRI
pk
2
R
⋅≈
SENSE
,
Using multiple resistors in parallel will help obtaining the required power rating with standard resistors, and reduce the inductance.
R
The following table shows R
tolerance reflects on the peak current error: 1% resistors should be preferred.
SENSE
recommended values (to have 0.5V drop on it) and power ratings for typical
SENSE
examples of current peak values.
I
pk
0.5 1 0.25
1 0.5 0.5 2 X 1Ω, 0.25W paralleled
1.5 0.33 0.75 3 X 1Ω, 0.25W paralleled
2 0.25 1 4 X 1Ω, 0.25W paralleled
R
SENSE
Value
[Ω]
R
SENSE
Power Rating
[W]
Alternatives
3.6 Charge pump external components
An internal oscillator, with its output at CP pin, switches from GND to 10V with a typical frequency of 600kHz
(see Figure 9).
Figure 9. Charge Pump .
VS + 10 V - VD1 - V
D2
f = 600 kHz
VS + 10 V - VD1
V
- VD1
S
C8
= 70Ω
= 70Ω
Charge Pump
Oscillator
10 V
5 V
10 V
f = 600 kHz
D1
V
BOOT CP
To High-Side
Gate Drivers
C5
R4
D2
V
10 V
SA VSB
R
DS(ON)
R
DS(ON)
L6205, L6206, L6207
When the oscillator output is at ground, C5 is charged by VS through D2. When it rises to 10V, D2 is r eve rse
biased and the charge flows from C
imum voltage of V
+ 10V - VD1 - VD2, which supplies the high-side gate drivers.
S
With a differential vol tage betw een V
ical current drawn by the V
BOOT
to C8 through D1, so the V
5
and V
S
of about 9V and both the bridges switching at 50kHz, the typ-
BOOT
pin is 1.85 mA.
pin, after a few cycles, reaches the max-
BOOT
10/53
AN1762 APPLICATION NOTE
Resistor R4 is added to reduce the maxi mum current i n the exter nal components and to reduce the slew rate of
the rising and falling edges of the voltage at the
circuit. For the same reason car e must be taken in realiz ing the PC B layout of
also the
Layout Considerations
section). Recommended values for the charge pump circuitry are:
D1, D2 : 1N4148
R4 : 100
Ω (1/8 W)
C5 : 10nF 100V ceramic
C8 : 220nF 25V ceramic
Due to the high charge pump frequency, fast diodes are required. Connecting the cold side of the bulk capacitor
(C8) to V
R4 = 100
instead of GND the average current in the external diodes during operation is less than 10 mA (with
S
Ω
); at startup (when VS is provided to the IC) is less than 200 mA while the reverse voltage is about
10 V in all condi tions. 1N4148 diodes withstand about 200 mA DC (1 A peak), and the maximum rever se voltage
is 75 V, so they should fit for the majority of applications.
3.7 S ha ring the Charge Pump Circuitry
If more than one device is used in the application, it's possible to use the charge pump from one L6205, L6206
or L6207 to supply the V
pins of several ICs. The unused CP pins on the slaved devices are left uncon-
BOOT
nected, as shown in Figure 10. A 100nF capacitor (C8) should be connected to the V
Supply voltage pins (V
) of the devices sharing the charge pump must be connected together.
S
The higher the number of devices sharing the same charge pump, the lower will be the differential volt age available for gate drive (V
- VS), causing a higher R
BOOT
In this case it's recommended to omit the resistor on the
charge pump circuitry.
Better performance can als o be obtained using a 33nF capacitor for C5 and using s chottky diodes (for ex ample
BAT47 are recommended).
Sharing the same charge pump ci rcuitr y fo r mor e than 3÷4 devi ces is not recommended, sinc e it wil l reduce the
V
voltage increasing the high-side MOS on-resistance and thus power dissipation.
BOOT
CP
pin, in order to minimize interferences with the rest of the
R4, C5, D1, D2
for the high side DMOS, so higher dissipating po wer.
DS(ON)
CP
pin, obtaining a higher current capability of the
connections (see
pin of each device.
BOOT
Figure 10. Sha ring the char ge pu m p c ir cui t ry .
To other Devices
V
BO OT
To High-Side
Gate Drivers
C18 = 100 nF
V
V
SA
CP
SB
L6205, L6206, L6207
D2 = BAT47
V
BOOT
To High-Side
Gate Drivers
D1 = BAT47
C5 = 33nF
CP
V
SA VSB
C8 = 100nF
L6205, L6206, L6207
11/53
AN1762 APPLICATION NOTE
3.8 Reference Voltage for PWM Current Control (L6207 ONLY)
The L6207 has two analog inputs, V
peak value of the motor curr ent through th e integrated PWM circuitry . In typical applications these p ins ar e connected together, in order to obtain the same cur rent i n the two m otor windings. A fixed reference vol t age can be
easily obtained through a resistive divider from an available 5 V voltage rail (maybe the one supplying the µC
or the rest of the application) and GND.
A very simple way to obtain a variable voltage without using a DAC is to low-pass filter a PWM output of a µC
(see Figure 11).
Assuming that the PWM output swings from 0 to 5V, the resulting voltage will be:
refA
and V
V
ref
, connected to the internal sense comparators, to control the
refB
5V DµCR
⋅⋅
-----------------------------------------=
R
LPRDIV
DIV
+
where D
Assuming that the µC output impedance is lower than 1k
is the duty-cycle of the PWM output of the µC.
µC
Ω,
with RLP = 56kΩ, R
= 15kΩ, CLP = 10nF and a
DIV
µC PWM switching fr om 0 to 5V at 100kHz , the l ow pass fi lter tim e consta nt is about 0.12 ms an d the remai ning
ripple on the V
voltage will be about 20 mV. Using higher values for RLP, R
ref
and CLP will reduce the ripple,
DIV
but the reference voltage will tak e more time to vary after changing the duty -cycle of the µC PWM, an d too high
values of R
As sensing resistor values are typically kept small, a small noise on V
will also increase the im pedance of the V
LP
net at low frequencies, causing a poor nois e immunity.
ref
input pins might cause a considerable
ref
error in the output current. It's then recommended to decouple these pins with cerami c capaci tors of some tens
of nF, placed very close to V
and GND pins. Note that V
ref
pins cannot be l eft unconnected, while, if connected
ref
to GND, zero current is not guaranteed due to voltage offset in the sense comparator. The best way to cut down
(IC) power consumption and clear the load current is pulling down the
age, PWM integrated circuitry can loose control of the current due to the minimum allowed duration of t
the
Programmable off-time Monostable
section).
EN
pins. With very small reference volt-
ON
(see
Figure 11. Obtaining a variable voltage through a PWM outpu t of a µC.
PWM Output
of a µC
R
LP
R
DIV
V
ref
C
LP
12/53
GND
AN1762 APPLICATION NOTE
3.9 Input Logi c pin s
IN1A, IN2A, IN1B, IN2
teresis to ensu re the r equire d noise i mmuni ty. Typic al val ues for tur n-on and t urn-off thresh olds ar e V
V
= 1.3V. Pins are ESD prote cted (see Figur e 12) (2kV h uman-body ele ctro-static discharge), a nd can be d irectly
th,OFF
connected to t he logic o utp uts of a µC; a series resis tor is gen erall y not recom mende d, as it co uld hel p induct ed nois e
to disturb the inp uts. All logic pins enforce a speci fi c behavior and cannot be left unconnected.
Figure 12. Logic input pins.
3.10 EN pi ns
The
ENA, EN
pins are, actuall y, bi-directiona l: as an input, with a comparator si milar to the other logi c input pins (TTL/
B
CMOS with hysteresis), they control the state of the PowerDMOS. When each of the two pins is at a low logic level,
all the PowerDMOS of the corresponding H-bridge (A or B) are turned off. In L6205 and L6207 the EN pins are also
connected to the two corresponding open drain outputs of the protection circuits that will pull the pins to GND if over
current in the corresponding H-bridge or over temperature conditions exist. In L6206 the open drain outputs are on
separate pi ns, OCD
with L6205 and L6207 (and L6206 if EN pins are connected to DIAG pins) EN pins must be driven through a series
resistor of 2.2k
A capacitor (C
Ω
EN
value of the output current when overcurrent conditions persist (see
not be left unconnected.
are CMOS/TTL com patible logic i nput pins. The input compara tor has been realized with hys-
B
= 1.8V and
th,O N
5V
ESD
PROTECTION
D01IN1329
and OCDB, allowing easier external di agnostics an d overcurrent ma nagement. For this reason,
A
minimum (for 5V logic), to al low the voltage at the pin to be pulled below th e tur n-off threshold.
in Figure 13) connected between each EN pin and GND is also recommended, to reduc e the r.m.s.
Over Current Protection
section). EN pin must
Figure 13. ENA and ENB input pins .
L6205, L6207 L6206
PUSH-PULL
OUTPUT
R
EN
ENA or EN
ENA or EN
B
B
C
EN
EN
C
EN
OCDA or OCD
5V
PUSH-PULL
OUTPUT
R
ENA or EN
B
5V
B
13/53
AN1762 APPLICATION NOTE
3.11 Programmable off-time Monostab le (L6207 ONL Y)
The L6207 includes a constant off time PWM current controller for each of the two bridges. The current control
circuit senses the bridge current by sensing the voltage drop across an external sense resistor connected between the source of the two lower power MOS transistors and ground, as shown in Figure 14. As the current in
the load builds up the voltag e across the sens e r esistor incr eases proportionally . W hen the vo ltage drop ac ross
the sense resistor becomes greater than the voltage at the reference input (VREF
parator triggers the monostable switching the low-side MOS off. The low-side MOS remain off for the time set
by the monostable and the motor current recirculates in the upper path. When the monostable times out the
bridge will again turn on. Since the internal dead time, used to prevent cross conduction in the bridge, delays
the turn on of the power MOS, the effective off time is the sum of the monostable time plus the dead time.
Figure 14. PWM Current Control Circuitry (L6207 ONLY).
VS
TO GATE LOGIC
BLANKING TIME
MONOST ABLE
1µs
FROM THE
LOW-SIDE
GATE DRIVERS
or VREFB) the sense com-
A
(or B)
A
5mA
MONOSTABLE
S
(0) (1)
5V
RC
C
OFF
R
Q
R
-
+
2.5V
A(or B)
OFF
RESET
BLANKER
SENSE
COMPARATOR
COMPARATOR
OUTPUT
DRIVERS
+
DEAD TIME
+
-
VREF
A(or B)
2H 1H
DRIVERS
+
DEAD TIME
2L 1L
SENSE
A(or B)
R
SENSE
OUT2
OUT1
I
OUT
A(or B)
A(or B)
D02IN1352
LOAD
(or B)
A
Figure 15 shows the typical operating waveforms of the output current, the voltage drop across the sensing resistor, the RC pin voltage and the status of the bridge. Immediately after the low-side Power MOS turns on, a
high peak current flow s through the sen sing resistor due to the rev erse recovery of the freewheeling diodes . The
L6207 provides a 1
µs
Blanking Time t
that inhibits the comparator output so that this current spike cannot
BLANK
prematurely re-trigger the monostable.
14/53
AN1762 APPLICATION NOTE
Figure 15. PWM Output Current Regulation Waveforms (L6207 ONLY).
I
OUT
V
REF
R
SENSE
V
SENSE
V
REF
0
V
RC
5V
2.5V
ON
OFF
SYNCHRONOUS RECTIFICATION
D02IN1351
t
OFF
1µs t
BLANK
Slow Decay Slow Decay
t
RCRISE
t
RCFALL
1µs t
DT
BC
t
ON
t
RCFALL
DDA
BC
t
OFF
1µs t
t
RCRISE
1µs t
BLANK
DT
Figure 16 shows the magnitude of the Off Time t
calculated from the equations:
t
RCFALL
t
OFF
where R
20K
0.47nF ≤ C
t
DT
= 0.6 · R
= t
RCFALL
and C
OFF
Ω ≤
R
OFF
OFF
OFF
= 1µs (typical value)
· C
OFF
· C
OFF
+ t
OFF
OFF
+ tDT = 0.6 · R
are the external component values and tDT is the internally generated Dead Time with:
≤ 100K
Ω
≤ 100nF
Therefore:
t
OFF(MIN)
t
OFF(MAX)
These values allow a sufficient range of t
The capacitor value chosen for C
The Rise Time t
= 6.6µs
= 6ms
RCRISE
to implement the drive circuit for most motors.
OFF
also affects the Rise Time t
OFF
will only be an issue if the capacitor is not completely charged before the next time the
monostable is triggered. Therefore, the on time t
versu s C
OFF
DT
, which depends by motors and supply parameters, has to
ON
OFF
RCRISE
and R
values. It can be approximately
OFF
of the voltage at the pin RCA (or RCB).
15/53
AN1762 APPLICATION NOTE
Ω
be bigger than t
can not be smaller than the minimum on time t
t
>1.5µs (typ. value)=
ONtON MIN()
t
ONtRCRISEtDT
RCRISE
= 600 · C
t
for allowing a good current regulation by the PWM stage. Furthermore, the on time t
RCRISE
ON(MIN)
.
–>
OFF
ON
3.11.1 Off-time Selection and mini mum on-time (L6207 ON LY)
Figure 16 also shows the lower limit for the on time tON for having a good PWM current regulation capacity. It
has to be said that t
smaller than t
RCRISE
is always bigger than t
ON
because the device imposes this condition, but it can be
ON(MIN)
- tDT. In this last case the device continues to work but the off time t
is not more con-
OFF
stant.
So, small C
switching frequency), but, the smaller is the value for C
value gives more flexibility for the applications (allows smaller on time and, therefore, higher
OFF
, the more influential will be the noises on the circuit
OFF
performance.
Figure 16. Off-time selection and minimum on-time (L6207 ONLY).
4
1.10
1.10
3
R = 100 kΩ
R = 47 k
R = 20 kΩ
10 0
to f f [ u s]
10
1
0.1 1 10 100
Coff [nF]
100
10
to n ( m in ) [ u s ]
1
0.1 1 10 100
Coff [nF]
16/53
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