ST AN1751 Application note

	AN1751
®	APPLICATION NOTE

EMI Filters: Recommendations and measurements

P. MERCERON AND P. RABIER

With the development of wireless telecommunications, consumer products and cellular phones are subjected to Radio Frequency Interference and may generate ElectroMagnetic Interference. This is in addition to ElectroStatic Discharge the user can apply when touching a connector like a bottom connector on a cellular phone.

In the past, filtering was achieved by discrete devices (capacitors, resistors) and ESD protection was done by discretes diodes. Cellular phone size drop and enhanced features require faster signals and more and more integrated devices which are becoming very sensitive to ESD or EMI/RFI.

Discretes devices impose a well designed layout to minimize parasitic effect of PCB inductances while Integrated Passive and Active Devices suppress most of these inductances due to very short tracks between passives on the die itself.

Fig. 1: Frequency response comparison between discrete and IPAD™ filter.

dB

IPAD

DISCRETES

10 MHz

100 MHz

1 GHz

Discrete filter will behave like a rejection filter but the rejection frequency will be depending on parasitic inductances while the IPAD filter will act like a low pass filter.

EMIF filters have three main functions, the first is of course to filter EMI/RFI, the second is to protect inputs and outputs against ESD and the third one is to transmit data from inputs to outputs. EMIF datasheets provide data and curve measured in specific conditions. The goal of this note is to explain test conditions for EMIF devices.

1-Frequency response

EMIF target is to pass low frequency signals and to reject frequency higher than 800MHz especially 900MHz, 1.8 and 2.4GHz.

Attenuation curve provided in specification shows :

nSimulation thanks to the Aplac (or P-Spice) tool. This is done before the die design to be sure the device will fit customer requirements

nMeasurement done on demonstration board.

September 2003 - Ed: 1

1/7

AN1751 - APPLICATION NOTE

Aplac models take into account of die, bumps and via for the ground connections. It does not consider PCB track in the application.

Figure 2 represents an example of Aplac model for one filtering cell.

Fig. 2: Aplac model for die, bumps and PCB via.

I1		O1
	Rs
Cin	MODEL = D01
		Cout
Rsubump	MODEL = D02	Rsubump	Die model
		gnd
		Bump model
	Lbump
	Rbump
	Cgnd	Lgnd
		Via model
		Rgnd

P-Spice is probably the most wellknown simulation software in electronic industry. Limits of P-Spice is reached when trying to simulate RF signals because of the time it takes for each simulation. It is also impossible to simulate crosstalk phenomena. Aplac has been developed to avoid all these P-Spice limitations.

Concerning measurements, the first step is to calibrate the equipment. This is why demoboards are delivered with a calibration kit shown in figure 3 while the IPAD™ device is on another board ( figure 4).

Fig. 3: Calibration board.

Fig. 4: Measurement condition on demoboard.

50 Ω

50 Ω

Vg

If test equipment is not calibrated, non negligible error can occur as the attenuation measurement will correspond to the one of the IPAD™ + board + connections. Furthermore measurement is done with a 50 Ω load while some applications may have other impedances.

2/7

AN1751 - APPLICATION NOTE

2- ESD and latch-up measurements

I/O lines of a cellular phone must be protected against ESD. Most popular ESD standard is the IEC61000-4-2 having a surge generator defined in figure 5.

Fig. 5: IEC61000-4-2 generator and the result on a non protected integrated circuit die.

			R1	L1			R2	L2
+								To pin
						+
			C1				C2
-						-
			GND				GND

IEC61000-4-2 specifies C1 charged up to 8kV (contact) and 15kV (air discharge). The MIL-STD 883E Method 3015.7 is also a reference.

All external pins (bottom connectors, microphone jack…) may be subjected to these kinds of surges. If no protection is used, result will be the destruction of the internal silicon chip. Destroyed I/O is generally a short circuit as silicon melt on a very small area as shown in figure 5.

If ESD protection device is the minimun to prevent failure, layout is also very important as very high dI/dt of surge will generate a high LdI/dt.

This means even with a protection device, an integrated circuit can be destroyed because of layout problem. Figure 6 explains differences between 2 layouts.

Fig. 6: Two layouts for two very different results.

		L6	L2	L1			L6	L1
IC to be	protected				protected
		VIC VCL		VIN		V	V	V
				IC tobe		IC	CL	IN
			L3
		L5		L4			L3	L2
		Wrong layout				Correct layout

Knowing all PCB tracks are equivalent to an inductance, in the first case the IC will see a voltage: VIC = (L1+L2+L3+L4) x dI/dt + VCL

With a track lengh, for protection device connection, of 2 cm (1cm from side to side), 35µ thickness, 0.5mm wide (microstrip track) then L2+L3 = 8nH

Considering a 15kV ESD surge surge having dI/dt = 50A/0.7ns

The result is VIC = 570V

3/7