ST AN1722 Application note

AN1722 APPLICATION NOTE

Design and Realization of a CCFL Application Using TSM108, STN790A, or STS3DPFS30, and STSA1805

1. ABSTRACT

This technical document shows how to use the integrated circuit TSM108, the PNP power bipolar transistor STN790A, or the P channel power MOSFET STS3DPFS30, the NPN power bipolar transistor STSA1805 and the diode 1N5821 in order to design and realize a CCFL application. Such work allows STMicroelectronics’ customers to choose an alternative design and STMicroelectronics itself to supply all devices concerning the power transistor part and also the control and driver part for these applications (KIT approach).

In the application block diagram below, the several STMicroelectronics’ power devices are inserted in the related block.

Figure 1: Block diagram of the application

	BUCK SECTION
+12V	STN790A
	1N5821
	STS3DPFS30

PUSH-PULL SECTION

STSA1805

OUTPUT SECTION

PWM SECTION

TSM108

LAMPS

2. TSM108 DESCRIPTION

TSM108 is a PNP power bipolar or P channel power MOSFET controller. TSM108 includes a PWM generator (AMP3 in fig. 2), voltage and current control loops (AMP1 and AMP2 respectively in fig. 2) and it also includes safety functions that lock the PNP power bipolar or P channel power MOSFET in off state. The TSM108 can sustain 60V on Vcc and the Isink (base or gate drive sink current to switch on the device) and Isource (base or gate drive source current to switch off the device) are respectively 15 mA (min value) and 30 mA (max value).

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Figure 2: TSM108 schematic circuit

As exposed above, the safety functions UV and OV can switch off the power transistor (PNP power bipolar or P channel power MOSFET) when the Vcc is under a definite min voltage or when the Vcc overcomes a

definite max voltage. In fact, in these cases the output signal of the AMP 5, or the AMP 6, is low and the NAND output is high. Considering the UV function, fig. 3 shows the circuit part concerning it.

Figure 3: UV schematic circuit detail

					184kΩ
		76.5kΩ
		2.52V
The V+ voltage (the one in the non-inverting pin of the AMP5) is:
		76.5						(1.1)
V+ = 184 +76.5 Vcc
and considering:
						V-=2.52V		(1.2)
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the minimum Vcc under which the application will switch off is:

V = 2.52 (184 +76.5) ≈ 8.5V

(1.3)

cc	76.5

Considering the OV function, fig. 4 shows the circuit part concerning it.

Figure 4: OV schematic circuit detail

275kΩ

23.2kΩ

2.52V

The V- voltage (the voltage in the inverting pin of the AMP6) is:

V− =	23.2		Vcc	(1.4)
	275 +23.2
and considering:
		V+ = 2.52V			(1.5)

the maximum Vcc over which the board will switch off is:

Vcc =	2.52	(275 +23.2) ≈ 32.4V	(1.6)
	23.2

In order to adjust the UV and OV voltages it is necessary to insert suitable resistances as showed later in this paper.

It is important to highlight that, normally, the max δ (duty cycle) of the base drive, or gate drive, is around 95 %.

3. STN790A DESCRIPTION

The STMicroelectronics’ power bipolar transistor device STN790A is housed in the SOT-223 package. Such device is manufactured in PNP planar technology using a 'Base Island' layout that involves a very high gain performance and a very low saturation voltage.

The main characteristics of the STN790A device are:

1)Veco ≥ 30V

2)Vecs ≥ 40V

3)Vbeo ≥ 5V

4)Ic = -3 A (continuous current)

5)Ib = 1 A (continuous current)

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6)Vec(sat) = 1.2 mV (typ) @ Ib = -20 mA @ Ic = -2 A (typical conditions)

7)Hfe = 100 (min) @ Ic = -2.5 A @ Vec = 3V (typical conditions)

4. 1N5821 DESCRIPTION

The STMicroelectronics’ SCHOTTKY diode is integrated in the package DO-201AD and has very small conduction losses, negligible switching losses and extremely fast switching.

The main characteristics of the 1N5821 device are:

1)VRRM ≥ 30V

2)IF = 3A

5. STS3DPFS30 DESCRIPTION

The STS3DPFS30 device is mounted inside a P channel power MOSFET, using the STripFET layout that allows a lower Rds(on) and a SCHOTTKY diode. It is housed in the SO-8 package.

The main characteristics of the STS3DPFS30L device are:

1)Vsd ≥ 30V

2)Vsg ≥ 20V

3)Rds(on)_max = 0.09 Ohm @ Id = 1.5 A @ Vsg=10V

4)IF = 3A (integrated diode);

5)VF_max = 0.51 V (integrated diode)

6)VRRM = 30V (integrated diode)

6. STSA1805 DESCRIPTION

The STMicroelectronics’ power bipolar transistor device STSA1805 is housed in the TO-92 package. Such device is manufactured in NPN planar technology using a 'Base Island' layout that involves a very high gain performance and a very low saturation voltage.

The main characteristics of the STSA1805 device are:

1)Vceo ≥ 60V

2)Vces ≥ 150V

3)Vebo ≥ 7V

4)Ic = 5A (continuous current)

5)Ib = 1A (continuuous current)

6)Vce(sat) = 140 mV (typ) @ Ib = 50 mA @ Ic = 2A (typical conditions)

7) Hfe = 270 (typ) @ Ic = 2A @ Vce = 1V (typical conditions)

7. APPLICATION INTRODUCTION

The CCFL applications (Cold Cathode Fluorescent Lamp) are generally used for the monitor back lighting which is often used to illuminate the signs.

The part of the circuit driving the CCFL lamps is composed of a DC-AC converter. The CCFL applications use special compact fluorescent lamps. The lamps number can be 1, 2, 4, or 6 and the output power can be in the range of 2-24W. The DC-AC converters transform the low DC in input voltage in necessary high AC output voltage for the fluorescent tubes. The CCFL are usually powered with a 12 Vdc voltage.

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Today, two topologies are available for driving the above-mentioned special tubes: the 'ROYER' and the FULL BRIDGE solutions.

The 'ROYER' solution uses a Push-Pull current fed converter where the current source is due to an inductor and where it is possible to regulate the lamps brightness. Such a regulation is carried out by means of the inductor current controls, through a PNP power bipolar or P channel power MOSFET transistors (STN790A or STS3DPFS30 respectively), working in PWM mode, and a free wheeling diode. The diode, the transistor and the inductor make a BUCK converter stage before of the PUSH-PULL converter stage. The PUSH-PULL converter uses two NPN power bipolar transistors (STSA1805). The other solution, the FULL BRIDGE topology, uses four power MOSFET transistors, two pair of complementary power MOSFET transistors, driven by a suitable IC.

The design described in this paper uses the 'ROYER' topology, thus, only such topology will be studied.

In the graph below a schematic circuit of a CCFL application, using two paralleled 6W lamps and only one transformer, is shown (this is one of the several possible output stage configurations).

Figure 5: 'ROYER' converter schematic circuit

8. FLUORESCENT TUBES CHARACTERISTICS

Fluorescent lamps are generally made with tubes filled with a gas mixture at low pressure. The inner sides of the tubes are covered with fluorescent elements. During the start-up, before the tube lights on, the lamp has a very high resistance. Usually, in the common fluorescent lamps, the electrodes voltage increases up to around 500V and starts to warm up and emit ions, but in the CCFL tubes the voltage between the lamp electrodes reaches up to 1300V. Fig. 6 shows CCFL lamp characteristics before the striking.

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Figure 6: Lamp voltage before striking

When the fluorescent lamp lights on, the gas mixture inside is fully ionized, and an arc across the two electrodes occurs. In this new condition, the lamp resistance drops to 60 KOhm and the voltage across the lamps drops to about 800V (Fig. 7 and Fig. 8 show the lamp characteristics and the V-I characteristic respectively after the striking).

Figure 7: Voltage and current Lamp after striking

Figure 8: V-I Characteristic after striking

After the striking, the gas mixture emits radiations able to excite the fluorescent elements inside the tube producing the light in the visible spectrum. In this example, after the striking, the maximum electrodes voltage falls from 1300V down to 770V with a peak current of 12 mA. In the common fluorescent lamp

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the voltage between the tube terminals drops from about 500V, before the striking, to about 220V after the striking.

Usually, after the striking, in order to increase the light efficiency, the tube works with a frequency around 25-50KHz, in fact, in this frequency range, the light output can increase up to 15 % for the same input energy.

Generally, the common fluorescent lamps can be considered only as a resistive load. In the CCFL lamps, instead, even if the tubes show a resistive behavior, a small but evident capacitive behavior is observed as it is shown in fig.7. In fig. 7 it is evident that the V-I Characteristic is linear until the established voltage value is reached (in this case about 500V). After reaching this voltage value, the characteristic starts to become flat because no ion can emit other radiations.

9. TRANSFORMER DESCRIPTION

The transformer named T1 shown in fig. 5 has three windings. The primary winding terminals are connected to the collectors of the Q2 and Q3 NPN power bipolar transistors. The same primary winding has a central terminal where the inductor L1 output is connected. The secondary winding terminals are connected to the loads.

The third winding terminals are connected to the base of the transistors Q2 and Q3 so that the first is on while the second is off and vice versa. During the Q2 on state the current flows through the device and the related half primary winding, instead, when Q3 is on the current passes through this second device and the other half primary winding. Usually the LT primary inductance of the transformer T1 is much lower compared to the inductance L1. The resonance frequency of the PUSH-PULL converter is also due to the LT inductance. In the design, N2 (number of secondary turns) and N1/2 (number of half primary turns) ratio is around 80-90 while, N1/2 and N3 (number of third turns) ratio, is around 4-5. In fact, considering a

12 Vdc input voltage, the v1/2max voltage (the max voltage between the terminal of the central point of the primary winding and the reference when the PNP power bipolar or the P channel power MOSFET transistors are always on) is:

v1/ 2max =	π	Vdc	(9.1)
	2

as then demonstrated around 19V, the v2max (the max voltage between the secondary terminals of the transformer) is:

v2max =	π	Vdc	N2
	2		(N1	2	) (9.2)

around 1500-1700V and the v3max (the max voltage between the terminals of the third transformer winding) is:

v3max =	π	Vdc	(N3 )		(9.3)
	2		N1	2

As exposed above, the N1/2 value and not N1 is highlighted. In order to understand the reason of it, it is

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necessary to consider the graph below.

Figure 9: Detail of the transformer T1

As already exposed, when the Q2 transistor is on, the other is off and vice versa. Now, considering fig. 9 where the T2 switch is on, the I current passes through the 'b' half primary winding of the transformer T1 and generates a magnetic force (Hopkinson law):

N1	I = Φ	(9.4)
2

where Φ is the magnetic flux and is the magnetic reluctance of the T1 core, thus Φ is:

		N1 I
	Φ =	2		(9.5)
	The magnetic reluctance is:
	=	l		(9.6)
		µ	A

where µ is the core permeability, A is the core section and l is the core length. When T2 switches off and T1 switches on, the current flows through the other half primary winding 'a' of the transformer T1 and the flux Φ inverts its direction. Such a flux flows in the magnetic core T1 creating a link respectively with the windings N2 and N3, and also with the other half of the primary windings N1/2, and generating the voltages v2 and v3 (magnetic law-Lenz law):

v2 = −N2

∆Φ;v3 = −N3

∆Φ

;v1/ 2

= −N1 ∆Φ

(9.7)

∆t

∆t

2 ∆t

thus:

v2

=

N2

,

v3

=

N3

,

v1

= 2

v1/ 2

v1/ 2

N1

2

v1/ 2

N1

2

(9.8)

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Furthermore, the current i2 (the current flowing through the secondary winding of T1) is:

		i2 = I			N1 2		(9.9)
					N2
in fact, the apparent input power is:
		Ain	=V1/ 2I				(9.10)
while the apparent output power is:
		Aout	=V2i2				(9.11)
and considering an ideal transformer:
		V2i2	=V1/ 2I				(9.12)
and thus:
i2		V1/ 2			N1 2		1 (9.13)
I	=	V2 =				= k
				N2

10. THE 'ROYER' CONVERTER TOPOLOGY

As previously exposed, the topology solution for CCFL applications used in this paper is the 'ROYER' topology. This topology solution has a current feed PUSH-PULL switching converter stage and also an inductor that together with a PNP power bipolar, or P channel power MOSFET transistor and a free wheeling diode, makes a BUCK converter stage before the PUSH-PULL stage. The PNP power bipolar, or the P channel power MOSFET transistor fixes the output power and thus the lamps brightness. All this is performed through a PWM signal able to drive either the PNP bipolar transistor or P channel MOSFET depending on the kind of device used. In order to implement the PWM of the transistor it is necessary to make an output current sensing (the lamps current) and to compare such a signal to the reference voltage in the AMP1 (see fig. 10 and fig.11 for the schematic circuit designed in this paper using the PNP power bipolar transistor STN790 and the power MOSFET transistor STS3DPFS30 respecticvely). The reference is fixed to 2.52V by the TSM108 internal voltage generator.

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Figure 10: CCFL schematic circuit using the PNP power bipolar transistor

Figure 11: CCFL schematic circuit using the P channel power MOSFET transistor

Such a sensing net fixes also the right output power during the voltage net fluctuations.

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The component values for capacitors, resistors, and inductors are selected based on the load power, the operation frequency of the lamp before and after the striking (the operation lamp frequency must be in the range of 25-50Khz), and the current ripple. The PNP power bipolar, or the P channel power MOSFET operation frequency is fixed by means of the 220 pF capacitor C14 (around 90KHz).

Before the lamps strike the operation frequency is due to the resonance between the capacitor C9 and the primary transformer windings inductance LT of the T1 transformer (see fig. 12):

f =		1
		(10.1)
2	π	LTC9

Figure 12: Resonant schematic circuit before lamps striking

C9

When the lamps are connected, the transformer circuit, considering the ideal transformer, can be represented as in the following graph.

Figure 13: Resonant circuit of the transformer after lamps striking

In this condition, the apparent input power is:

Ain = v1I (10.2)

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Now it is possible to consider a new equivalent transformer circuit as shown in the graph below and where the apparent power is the same as before.

Figure 14: Equivalent resonant circuit of the transformer after lamps striking

In this equivalent transformer circuit the output impedance is transferred from the secondary winding to the primary winding of the transformer T1. In fact, considering that C3 and C4 have the same value

(C3=C4=C) and that Rlamp is the same for both lamps, considering also that the C3-Rlamp net and the C4-Rlamp net are in parallel configuration, the output impedance can be written as:

							RLamp								− j						1									(10.3)
									2										2		ω C
but:
			V I =V i				2	= i					2		(	RLamp							− j						1			)			(10.4)
				1		2						2							2							2 ω C
thus:
V I		RLamp					1										V				I			V					N		2				V
1	= (				− j								)		=				1				=		1						2			=	1 k 2	(10.5)
																													N1
i22		2				2 ω			C								i2 i2								I			(			2 )		2		I
and thus:
		V	= zeq1			=	1			(		RLamp								− j					1					)					(10.6)
		1
							k 2								2									2 ω C
		I
where:
											RLamp												(10.7)
												2k 2
is the primary equivalent resistance, while:
												2Ck 2											(10.8)

is the primary equivalent capacitance.

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Now, the equivalent primary admittance (Yeq1) is:

		RLamp −2Ck 2				(10.11)
		2k 2
			RLamp
Yeq1		− j	+ jω C9	k 2		k 2 j2ωC
	=	ω LT		+	(1	+ jωCRLamp )	(10.9)

where:

		k 2 j2ω C		(10.10)
	(1+ jCRLampω)
is the admittance of the series net:
Considering the impedance of the

negligible compared to Ck2 , deriving the Yeq1 with respect to the pulsation ω and equaling to zero, it is possible to find the frequency that maximizes the Yeq1 and, thus, minimizes the Zeq1 impedance (such frequency is the resonance frequency of the application during the lamps on state):

	ω2		1		(10.12)
			LT (C9 +2k 2C)
	and thus:
	f		1		(10.13)
		2 π	LT (C +2k 2C)
			9

When the board is powered, the resistances R10 and R11 (see fig. 15) enable the power bipolar devices Q2 and Q3 and the lamps turn on. After the start-up, during the Q2 on state, the current flowing through the inductance L1, through the half primary winding of the transformer T1 and through the transistor Q2, increases with an angular coefficient given by:

tgα =	vL1 * ∆t	(10.14)
	L1

After a first instant, the current curve becomes flat and its average value depends on the impedance Zeq1

and on the output power. However, when the PNP power bipolar, or P channel power MOSFET is on, after the lamps start-up, the current oscillates around the average value because the ripple on it depends only on the inductance L1. In PWM mode, instead, it depends also, linearly, on the duty cycle of the

transistor.

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Figure 15 shows the 'ROYER' converter schematic circuit during the start-up considering the current I graph through the inductor.

Figure 15: 'ROYER' converter schematic circuit with	inductor	current	theoretical
behavior at starup

After the striking, the primary current ‘I’ generates the current i2 into the secondary winding of the transformer T1. At the beginning, the current i2 can be written as:

	i2 =	v2		(10.15)
		RLamp	2

because the capacitors C3 and C4 are discharged. Immediately after, these capacitors get charged and the current i2 drops to zero, while vc3 and vc4 reach the maximum voltage. At this time, the current i2 inverts its direction and the capacitors C3 and C4 start discharging until the charge inside them becomes zero and the current i2 reaches its maximum negative value. Furthermore, when the current i2 inverts the

direction also the voltage vt1b2 reverts the polarities so that Q2 switches off, Q3 switches on, and the current ‘I’ starts flowing into the other half winding of the transformer T1 (see fig. 16).

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Figure 16: 'ROYER' converter schematic circuit with theoretical behavior of v1, v2, and i2

The main output electrical parameters v2 (t), ILamp(t), VLamp(t), vc3(t) and vc4(t) (these last two are the voltages across the capacitors C3 and C4) are shown in the following graph under a vectorial

representation.

Figure 17: Vectorial representation of v2, i2, vlamp, vc3 and vc4

In fact, assuming that, the lamps have only resistive behavior, the ILamp currents flowing through them and the Vlamp (the voltage across them) can be written as:

VLamp =ILamp * RLamp (10.16)

The graph also assumes that the vectors VLamp and ILamp are on the real axis at the time taken into consideration. The ILamp currents flow also through the capacitors C3 and C4 and, thus, the voltages vc3

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and vc4 can be represented as -90 º phase shifted vectors compared to the ILamp vectors. The voltage v2

is the vectorial sum between the VLamp and vc3, or vc4. Before the striking, the resistance lamps Rlamp are very high compared to reactance of C3 and C4, the currents ILamp are low and the voltages Vlamp are very much comparable to the voltage v2 across the secondary winding of the transformer T1. After the

striking, Rlamp drops to about 60 KOhm and the reactance C3-C4 becomes higher compared to the first one, thus making the voltages vc3 and vc4 comparable to v2. However, in order to keep the lamps on,

after the striking, the max Vlamp must be about 700V across the tubes.

The voltage vl1 (voltage across the inductor L1) is the difference between the Vdc and the v1/2 voltages considering the PNP power bipolar in on-state, or the P channel power MOSFET transistor (see fig. 18).

Figure 18: 'ROYER' converter schematic circuit with the theoretical behavior of v1, v1/2, vL1, and Vdc

During the off state of the transistor Q1, the diode D1 turns on and the voltage vL1 becomes:

vL1 = −v1/ 2

(10.17)

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Figure 19: v1, v1/2,vL1, and Vdc theoretical behavior when the P channel power MOSFET switches off and the diode D1 freewheels

In fact, supposing Q1 always in on state, focusing the attention only on one half-period of the periodic voltage v1/2, as showed in fig. 20, the area A2 must be equal to the area A1 because the half-sine wave

voltage v1/2 and the voltage Vdc must have the same average value.

Figure 20: v1/2 half-sine wave and Vdc graphs

So writing A1 as:

	T	(10.18)
	A1 = Vdc 2
and considering A2:
T
A2 = ∫2	V1/ 2max sen(	2πt)dt = (10.19)
0		T

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