ST AN1709 Application note
AN1709
APPLICATION NOTE
EMC DESIGN GUIDE
FOR ST MICROCONTROLLERS
by Cyril Troise - Microcontroller Division Applications
INTRODUCTION
The continuing demand for more performance, complexity and cost reduction require the semiconductor industry to develop Microcontrollers with both high density design technology and
higher clock frequencies. This has intrinsically increased the noise emission and noise sensitivity. Applic ation dev elope rs therefor e, must no w app ly EMC “h ardening” te chniqu es in the
design of firmware, PCB layout and at system level. This note aims to explain ST Microcontroller EMC features and compliance standards to help application designers reach the optimum level of EMC performance.
1.0
AN1709/1003 1/38
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Table of Contents
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1 EMC DEFINITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1 EMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2 EMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.3 EMI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 EMC CHARACTERIZATION OF ST MICROCONTROLLERS . . . . . . . . . . . . . . . . . . 5
2.1 ELECTROMAGNETIC SU SCEPTIBILITY (EM S) . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1.1 Functional EMS test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1.1.1 Functional ElectroStatic Discharge Test (F_ESD Test) . . . . . . . . . 5
2.1.1.2 Fast Transient Burst (FTB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1.1.3 ST Severity Level & Behavior Class . . . . . . . . . . . . . . . . . . . . . . . 8
2.1.2 Latch-Up (LU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1.2.1 Static Latch-Up (LU) test: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1.2.2 Dynamic Latch-Up (DLU) test: . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1.3 Absolute Electrical Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1.3.1 Human Body Model Test Sequence . . . . . . . . . . . . . . . . . . . . . . 12
2.1.3.2 Machine Model Test Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2 ELECTROMAGNETIC INTERFERENCE (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2.1 EMI radiated test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2.2 EMI level classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3 ST MCU DESIGN STR ATEGY & EMC SPECIFIC FEATURE . . . . . . . . . . . . . . . . . . 17
3.1 SUSCEPTIBILITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1.1 Low Voltage Detector (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1.2 Auxiliary Voltage Detector (AVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1.3 I/O Features & properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.1.3.1 Electrostatic Discharge and Latch-up . . . . . . . . . . . . . . . . . . . . . 21
3.1.3.2 Protective Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.1.3.3 Internal Circuitry: Digital I/O pin . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.1.3.4 Internal Circuitry: Analog Input pin . . . . . . . . . . . . . . . . . . . . . . . . 25
3.1.4 Multiple VDD & VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.2 EMISSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.2.1 Internal PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.2.2 Global low power approach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.2.2.1 Low powered oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
38
3.2.2.2 Internal Voltage Regulators (for MCUs with low power core). . . . 29
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Table of Contents
3.2.3 Output I/O Current limitation & edge timing control . . . . . . . . . . . . . . . . . . . . . . . . . 29
4 EMC GUIDELINES FOR MCU BASED APPLICATIO NS . . . . . . . . . . . . . . . . . . . . . 30
4.1 HARDWARE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.2 HANDLING PRECAUTIONS FOR ESD PROTECTION. . . . . . . . . . . . . . . . . . . 34
4.3 FIRMWARE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.4 WEB LINKS TO EMC RELATE D ORGANIS AT IONS . . . . . . . . . . . . . . . . . . . . 36
5 CONCLUSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
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EMC DESIGN GUIDE FOR ST MICROCONTROLLERS
1 EMC DEFIN ITI ONS
1.1 EMC
ElectroMagnetic Comp atibility (EMC) is the cap ability of a system to work prop erly, undisturbed by the electromagnetic phenomena present in its normal environment, and not to
create electrical disturbances that would interfere with other equipment.
1.2 EMS
The ElectroMagnetic Susceptibility (EMS) l evel of a device is the resistance to electrical disturbances and conducted electrical noise. ElectroStat ic Discharge (ESD ) and Fast Transient
Burst (FTB) tests determine the reliability level of a device operating in an undesirable electromagnetic environment.
1.3 EMI
The ElectroMagnetic Interference (EMI) is the level of conducted or radiated electrical noise
sourced by the equipment. Conducted emission propagates along a cable or any interconnection line. Radiated emission propagates through free space.
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EMC DESIGN GUIDE FOR ST MICROCONTROLLERS
2 EMC CHARA CTERIZATION OF ST MICROC ONTROLLERS
2.1 ELECTROMAGNETIC SUSCEPTIBILITY (EMS)
Two different type of tests are performed:
■ Tests with device power-supplied (Functional EMS tests & Latch-up): The device behaviour
is monitored during the stress.
■ One test with device not powered supplied (Absolute Electrical Sensitivity): The device
functionality and integrity is checked on tester after stress.
2.1.1 Functional EMS test
Functional Tests are performed to measure the robustnes s of ST Microcontrollers running in
an application. Based on a simple program (toggling 2 LEDs through I/O ports), the product is
stressed by 2 different EMC events until a run-away condition (failure) occurs.
2.1.1.1 Functional ElectroStatic Discharge Test (F_ESD Test)
This test is performed on any new microcontroller devices.Each pin is tested individually with
a single positive or negative electrical discharge.This allows failures investigations inside the
chip and further application recommendations to protect the concerned Microcontroller sensitive pins against ESD.
High static voltage has both natural and man m ade origins. Some specific equipment can reproduce t his phenom e non i n orde r to te st t he devi ce un der r eal con di tions. Eq ui pmen t, test
sequence and standards are described here below.
ST Microcontroller F_ESD qualification test uses standards given in Table 1 as reference.
Table 1. ESD standards
EUROPEAN NORM INTERNATIONAL NORM DESCRIPTION
EN 61000-4-2 IEC 1000-4-2 Conducted ESD test
AEC-Q100-REUE is the Automotive controlling document.
F_ESD tests uses a signal source and a power amplifi er to generate a hi gh l evel fi eld into The
Microcontroller. The insulator is using a conical tip. This tip is placed on the Device or Equipment Under Test (DUT or EUT) and an electrostatic discharge is applied (see Figure 1.).
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EMC DESIGN GUIDE FOR ST MICROCONTROLLERS
Figure 1. ESD test equipment
ground plane
ESD generator
insulation
EUT
mains
connections
The equipment used to perform F_ESD test is a Generator NSG 435 (SCHAFFNER) compliant with the norm IEC 1000-4-2. The discharges are directly applied on ea ch pin of the
MCU.
Figure 2. Typical ESD Current Waveform in Contact -mode discharge
(EN 61000-4-2)
Current
100%
90%
I(30ns)
I(60ns)
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10%
30ns
tr=0.7 to 1.0 ns
60ns
time
EMC DESIGN GUIDE FOR ST MICROCONTROLLERS
Figure 3. Simplified diagram of the ESD generator
Discharge
tip
Discharge return
connection
ESD
generator
Rch
Rd
HV relay
Cs = 150 pF
(Rch = 50MΩ; Rd = 330Ω)
2.1.1.2 Fast Transient Burst (FTB)
More complex than functional ESD, this test which su bmits the dev ice to a large quant ity of
emitted disturbances in a short time, is useful for detecting infrequent and unrecoverable
(Class B or C) Microcontroller states. FTB disturbances (see Figure 4.) are applied to the Mi-
crocontroller power lines through a capacitive coupling network.
ST Microcontroller FTB test correlates with the standards given in Table 2
Table 2. FTB standards
EUROPEAN NORM INTERNATIONAL NORM DESCRIPTION
EN61000-4-4 IEC 1000-4-4 Fast Transient Burst
Figure 4. FTB Waveform Diagram
Voltage
Burst
Time
Burst Length
15ms
Repetition Frequency: 5kHz; Bursts will
be repeated for at least 1 minute.
Burst Period
300ms
Voltage
Pulse
Bur
s
t
Time Time
Rising and Durat ion time (±3 0%) are referred to a 50Ω load
Volt age
0.9Vpk
0.1Vpk
5ns
Vpk
0.5Vpk
50ns
The spike frequency is 5 kHz. The generator produces bursts of spikes that last 15 ms every
300 ms (75 spikes).
The fast transients are coupled to the device DUT with capacitors C
(See Figure 5.).
C
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EMC DESIGN GUIDE FOR ST MICROCONTROLLERS
Figure 5. Coupling Network
NSG 2025
+V
POWER
SUPPLY
GND
DD
L
Cc
Cc
+V
DD
TO THE DEVICE
UNDER TEST
GND
Measurements are performed on a ground plane. The generator is connected to ground plane
by a short wire. The supply wires are 10 cm from the ground pl ane. The DU T is on the insulator 10 cm from the ground plane. The FTB voltage level is increased until the device failure.
Severity Levels and Class help application designers to determine which ST microcontrollers
are suitable for their target application, based on the susceptibility level (Severity level) and
type of behavior (Class) indicated in the datasheet.
2.1.1.3 ST Severity Level & Behavior Class
The 1000-4-2 and 1000-4-4 standards do not refer specifically to semiconductor components
such as microcontrollers. Us ually electromagne tic stress is app lied on other pa rts of the
system such a s connec tors, m ains , supp lies... Th e en ergy le vel o f th e F_E SD and FTB test
decreases before reaching the microcontroller, governed by the laws of physics. A large
amount of statistical data collected by ST on the behaviour of MCUs in various application environments has been used to develop a correlation chart between ST F_ESD or FTB test
voltage and 1000-4-2/1000-4-4 severity levels (See Table 3).
Table 3. ST ESD Severity levels
Severity Level
120.50-0.5
2410.5-1
3621-1.5
484>1.5
ESD (1000-4-2)
Equipment standard
(kV)
FTB (1000-4-4)
Equipment standard
(kV)
ST Testing Voltage
ST internal EMC test
(kV)
In addition to th is severity le vel, MCU beh aviour under ESD stress can be grouped into different Behaviour Classes (See Table 4) according to EN 50082-2 norm:
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EMC DESIGN GUIDE FOR ST MICROCONTROLLERS
Table 4. ST Behavior Classes
Class A Class B Class C Class D
Needs an external user
action to recover normal
functionality
Normal functionality
cannot be recovered
No failure detected
Failure detected but self
recovery after disturbance
Any ST Microcontroller under the “acc eptance limits” is rejected as a fail. The “target level” is
the level used by ST to define good EMS performance.
Class B could be caused by:
– a parasitic reset correctly managed by the firmware (preferable case).
– deprogramming of a peripheral register or memory recovered by the application.
– a blocked status, recovered by a Watchdog or other firmware implementation.
Class C could be caused by:
– deprogramming of a peripheral register or memory not recovered by the application.
– a blocked application status requiring an external user action.
Table 5 shows ST target and acceptance limits.
Table 5. F_ESD / FTB target level & acceptance limit
Acceptance limit Target Level
F_ESD 0.5kV >1kV
FTB 0.5kV >1.5kV
Between “Acce ptance limit” and “T arget Level”, the dev ice is relatively suscep tible to noise.
Special care during system design should be taken to avoid susceptibility issues.
Table 6 shows how F_ESD / FTB test results are presented in ST datasheets.
Table 6. Example of F_ESD / FTB test results
Symbol Ratings Conditions Severity/Criteria
V
F_ESD
V
FTB
Voltage limits to be applied on any I/O
pin to induce a functional disturbance
Fast transient voltage burst limits to
be applied through 100pF on VSS and
VDD pins to induce a functional disturbance
T
=+25°C 2/A, 3/B
A
T
=+25°C 3/B
A
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EMC DESIGN GUIDE FOR ST MICROCONTROLLERS
2.1.2 Latch-Up (LU)
2.1.2.1 Static Latch-Up (LU) test:
The Latch-up is a phenomenon which is defined by a high current consumption resulting from
an overstress that triggers a parasitic thyristor structure and need a disconnection of the
power supply to recover the initial state.
NOTES
1 The overstress can be a voltage or current surge, an excessive rate of change of current or
voltage , or any other abno rmal conditi on th at caus es the paras itic th yrist or str ucture t o become self-sustaining.
2 Latch-up will not damage the device if the current through the low-impedance path is sufficiently limited in magnitude or duration.
This test conforms to the EIA/JESD 78 IC latch-up standard.
True LU is self-sustaining and once triggered, the h igh current c ondition w ill remain unt il the
power supply voltage is removed from the device. A temporary LU condition is considered to
have been induced if the high current condition stops when only the trigger voltage is removed.
Two complementary static tests are required on 10 parts to assess the latch-up performance:
■ Power supply overvoltage (applied to each power supply pin) simulates a user induced
situation where a transient over-voltage is applied on the power supply.
■ Current injection (applied to each input, output and configurable I/O pin) simulates an
application induced situation where the applied v oltage to a pin is greater than the maximum
rated conditions, such as sev ere overshoot abov e V
or undershoot below ground on an
DD
input due to ringing.
Table 7 shows how LU test result is presented in ST datasheets.
Table 7. Example of the LU test result on ST72F521
Symbol Parameter Conditions Class
T
=+25°C
A
=+85°C, TA=+125°C (de-
T
LU Static latch-up class
1. Class description: “A” class is an STMicroelectronics internal specification. All its limits are higher
than the JEDEC specifications, that means when a device belongs to Class A it exceeds the JEDEC
standard. “B” Class strictly covers all the JEDEC criteria (international standard).
A
pending on the temperature
range of the device)
1)
A
2.1.2.2 Dynamic Latch-Up (DLU) test:
The product is evaluated for its LU susceptibility to ES D discharges when the microcontroller
is “running.”
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EMC DESIGN GUIDE FOR ST MICROCONTROLLERS
Increasing electrostatic discharges are supplied to every pin of the component until a Latch-up
occurs. Result is the maximum tolerated voltage without Latch-up.
DLU Test methodology and characterization: Electro-Static Discharges (one positive then one
negative test) are applied to each pin of 3 samples when the microcontroller is running to assess the latch-up performance in dynamic mode. Power supplies are set to the typical values,
the oscillator is connected as near as possible to the pins of the microcontroller and the component is put in reset mode.
Table 8 shows how the DLU test result is presented in ST datasheets.
Table 8. Example of DLU test Result on ST72F521
Symbol Parameter Conditions Class
=5V
V
DD
DLU Dynamic latch-up class
1. Class description: “A” class is an STMicroelectronics internal specification. All its limits are higher
than the JEDEC specifications, that means when a device belongs to Class A it exceeds the JEDEC
standard. “B” Class strictly covers all the JEDEC criteria (international standard).
f
OSC
T
=+25°C
A
=4MHz,
1)
A
LU/DLU test equipment is same as the one used for the functional EMS (see Figure 1.).
2.1.3 Absolute Electrical Sensitivity
This test is performed to assess the components immunity against destruction caused by
ESD.
Any devices that fails this electrical test program is classified as a failure.
Using automatic ESD tester, Electro-Static D ischarges (a positive then a negative pulse sep-
arated by 1 second) are applied to the pins of each sample according to each pin combination.
The sample size depends of the number of supply pi ns of the device (3 parts*(n+ 1): n= supply
pins). Two models are usually simulated: Human Body Model (HBM) and Machine Model
(MM). All parts are re-test ed on the production tester to veri fy the static and dynamic parameters still comply with the device datasheet (See Figure 6.).
This test co nforms to th e JES D22-A11 4A/A 115A s tandar d. See Figure 6. and the following
test sequences.
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EMC DESIGN GUIDE FOR ST MICROCONTROLLERS
Figure 6. Absolute Electrical Sensitivity test models
HIGH VOLTAGE
PULSE
GENERATOR
S1
R=1500W
CL=100pF
HUMAN BODY MODEL MACHINE MODEL
µC
HIGH VOLTAGE
S2
PULSE
GENERATOR
S1
CL=200pF
R=10k~10MW
µC
S2
2.1.3.1 Human Body Model Test Sequence
The HBM ESD pulse simulates the direct transfer of electrostatic charge, from the Human
Body, to a test device. A 100pF capacitor is discharged through a switching component and a
1.5 Kohm series resistor. This is currently the m ost reques ted industry model, for classifying
device sensitivity to ESD.
– C
is loaded through S1 by the HV pulse generator.
L
– S1 switches position from generator to R.
– A discharge from C
through R (body resistance) to the µC occurs.
L
– S2 must be closed 10 to 100ms after the pulse delivery period to ensure the µC is not left in
charge state. S2 must be opened at least 10ms prior to the delivery of the next pulse.
2.1.3.2 Machine Model Test Sequence
The MM ESD pulse em ulates the rapid direct transfer of electrostatic charge, from a charged
conductive object, such as a metallic tool or fixture, to a test device. This model consists of a
discharged 200pF capacitor, with no series resistor. The demand for MM ESD testing has increased, with the replacement of individual packaging by automated systems.
is loaded through S1 by the HV pulse generator.
– C
L
– S1 switches position from generator to the µC.
– A discharge from C
to the µC occurs.
L
– S2 must be closed 10 to 100ms after the pulse delivery period to ensure the µC is not left in
charge state. S2 must be opened at least 10ms prior to the delivery of the next pulse.
R (machine resistance), in series with S2, ensures a slow discharge of the µC.
Table 9 shows how HBM/MM ESD test results are presented in ST datas heets.
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