ST AN1645 Application note

AN1645

APPLICATION NOTE

STSR2P/STSR2PM SIMPLIFIES IMPLEMENTATION OF SYNCHRONOUS RECTIFIERS IN FORWARD CONVERTER

F. Librizzi - F. Lentini

1. ABSTRACT

This paper describes the functionality and the operation of the STSR2P device used as the secondary synchronous rectifier driver in Forward topology switched mode power supplies. A schematic and layout description of a demo board, able to replace diode rectification with synchronous rectification in Forward converters, is shown below.

Figure 1: Typical Application Schematic

Feedback
Loop
TRANSFORMER			INDUCTOR
Vin				Vout
	MosfetN		Cout		Product(s)
	Q2
MosfetN			100nF			+5V
Q1
PWM
1	8	7	2
OUTGate1	PWRGND	OUTGate2	Vcc		100nF	R1
			SGLGND	6
	Obsolete
	-
STSR2P			SETANT	3		R2
Product(s)		INHIBIT		4		R3
			Ck
					D3	R4
		5				+5V
			R5
		D1	D2
option
Obsolete2. GENERAL DEVICE DESCRIPTION			+5V

The STSR2P Smart Driver IC provides two complementary high current outputs to drive Power Mosfets. The IC is dedicated to properly drive secondary Synchronous Rectifiers in medium power, low output voltage, high efficiency Forward Converters. From a synchronizing clock input, the IC generates two driving signals with a certain dead time between complementary pulses. The adopted transitions

December 2003 (rev.1)	1/22

AN1645 - APPLICATION NOTE

revelation mechanism makes circuit operation independent by the forward magnetic reset technique used, avoiding most of the common problems inherent in self-driven synchronous rectifiers. The IC operation prevents secondary side shoot-through conditions providing proper timing at the outputs turnoff transition. This smart function operates through a fast cycle-after-cycle control logic mechanism based on an internal high frequency oscillator, synchronized by the clock signal. The IC provides a fixed anticipation in turning-off the OUTGate1 with respect to the clock signal transition, while the anticipation in turning-off the OUTGate2 can be set through external components. A special Inhibit function allows the shut-off of one of the two outputs allowing operation during discontinuous conduction mode and preventing the freewheeling mosfet from sinking current from the output.

The STSR2P automatically turns off the outputs when duty-cycle is lower than 13%, while STSR2PM works even at very low duty-cycle values.

.

3. PIN CONNECTIONS AND DESCRIPTIONS

The STSR2P is housed in a SO-8 package for SMD assembly. Device pin out is shown in figure 2 and table 1 briefly summarizes the device pin functionality.

Figure 2: Pin Configuration

Product(s)

			-
		Product(s)
	Table 1: Pin Configuration
	Pin Number	Pin Name	Pin Function
	1	OUTGate1	Output for Forward MOSFET Gate Drive
	2	Vcc	Supply input from 4V to 5.5V
	3	SETANT2	Sets the anticipation in turning-off the OUTGATE2
	Obsolete	CK	Synchronization for IC’s operation
	4
	5	INHIBIT	Discontinuous Mode Detector
	6	SGLGND	Reference for all the control logic signals
	7	OUTGate2	Output for Freewheeling MOSFET Gate Drive
	8	PWRGND	Reference for power signals

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AN1645 - APPLICATION NOTE

Figure 3: Block Schematic

4. SUPPLY VOLTAGE AND UNDER VOLTAGEObsoleteLOCK-OUT

The supply input range is from 4V to 5.5V. An internal zener diode limits the maximum voltage to 5.7V. -

necessary between Vcc and PWRGND.

A 100nF ceramic Product(s)capacitor must be connected to Vcc and SGLGND pin in order to assure a stable supply voltage. This capacitor must be placed very close to the device. Another 100nF capacitor is

Under Voltage Lock Out feature guarantees proper start-up while it avoids undesirable driving during eventual dropping of the supply voltage.

As shown in the Block Diagram, the Vcc voltage also supplies the two output drivers, consequently the

maximum driving voltage is 5.5V, so the use of logic gate threshold mosfets is recommended.

Obsolete5. SYNCHRONIZATION

An innovative feature of the STSR2P is the capability to operate in the secondary side without any synchronization signal coming from the primary side. The IC synchronization is obtained directly from the secondary side using the voltage across the free wheeling mosfet as the information for the switching transitions. The Ck pin is the input for the synchronization signal; the internal threshold is set at 2.8V. As can be seen in figure 3, a Peak Detector is present at the Ck pin. This block is able to distinguish between the primary mosfet switching transitions and the eventual sinusoidal waveform caused by discontinuous mode operation (see figure 4). A wrong synchronization causes wrong driving of the synchronous rectifiers.

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5.1 Continuous Conduction Mode

Peak Detector Output

AN1645 - APPLICATION NOTE

Figure 4: DCM waveform

V1

Peak

Detector

Input

On	Off Time	Dead Time
Time

Product(s) When the converter is working in continuous modeObsoletethe voltage across the source and drain of the free wheeling mosfet has a square shape. This-voltage can be applied to the Ck pin using two different

configurations: with a resistor divider (figure 6) or with a diode and pull-up resistor (figure 7). In most cases a spike is presentProduct(s)during turn-off of the synchronous mosfet; this spike must be eliminated at the Ck pin in order to avoid false synchronization.

Using the resistor divider, the spike is eliminated by adding a small capacitor (C1) as shown in figure 6. Obsolete

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Figure 5: CCM waveform and Ck circuit

Turn-Off

Spike

AN1645 - APPLICATION NOTE

On Time Off Time

In a typical Forward converter for telecom application, the DC input voltage has a 1:2 variability range

(typically 36V-72V). Consequently the secondary winding voltage has also 1:2 variability. The resistor

Product(s)

divider can be calculated in order to have about 2.8V at the Ck pin at 36V input; at 72V input, the Ck pin

reaches 5.6V. Even if this value is higher than the maximum voltage on the CK pin, it can be accepted

limiting the current flowing into the pin to 10mA.

Figure 6: Synchronization with a resistor divider

Obsolete

-

FORWARD

FREE WHEEL

Product(s)

1

7

8

OUTGate2

PWRGND

OUTGate1

2

+5V

Vcc

Obsolete

+5V D1

R1

4

Ck

3

SETANT

C1

STSR2P

R2

6

SGLGND

INHIBIT

5

In case the Forward converter has a higher variability range 1:3 or 1:4, at minimum input voltage, 2.8V must be guaranteed at the Ck pin. At maximum input voltage, the voltage at the Ck pin will be 7.5V or 10V. This voltage exceeds the absolute maximum ratings of the device. If R2 limits the current flowing into the Ck pin to a value below the maximum Ck current value indicated in the datasheet (10mA), the

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AN1645 - APPLICATION NOTE

device can still working properly; otherwise a diode D1 connected to Vcc or a zener diode must be added to protect the device.

Figure 7: Synchronization with a diode and pull-up resistor

FREE WHEEL

FORWARD

+5V R1

D1

4

7		8		1
OUTGate2		PWRGND		OUTGate1

Ck

STSR2P

2

Vcc

3

SETANT

+5V

		6					INHIBIT	5
		SGLGND
Figure 7 shows the synchronization circuit with diode and pull-up resistor.Product(s)In this case there is no
problem with the turn-off spike and maximum CK pin voltage. This circuit cannot work properly in
Discontinuous Mode due to the ringing present in the					voltage drain of the synchronous rectifier.
Figure 8: Shut-down circuit			Obsolete
		-
		FREE WHEEL					FORWARD
			7	8		1
			OUTGate2	PWRGND		OUTGate1		+5V
		D1					Vcc	2
		R1
Obsolete	Product(s)+5V
		4	Ck					3
							SETANT
	OFF				STSR2P
		Q1
		NPN
	R2	6	SGLGND				INHIBIT	5

The STSR2P can be easily turned off adding a NPN transistor between Ck and SGLGND. This transistor forces the CK pin to GND when the signal OFF is high. In this condition OUTGate1 and OUTGate2 will be in a low state turning off the Synchronous Mosfets.

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AN1645 - APPLICATION NOTE

Figure 8 shows the turn-off circuit when using a diode and pull-up resistor to synchronize the STSR2P, the same configuration of Q1 and R2 can be used with a resistor divider circuit.

5.2 Discontinuous Conduction Mode

As shown in figure 4, in discontinuous mode operation there can be some problems in detecting the primary switching transitions. The internal peak detector is only able to determine the peak value reached by the signal at the Ck pin, neglecting all signals that have a lower value. A minimum voltage difference V1=400mV between the switching transition waveform and the sinusoidal waveform must be assured in order to allow the Peak Detector to work properly. If the ringing presents almost the same value as the square waveform, it is possible to add a filter circuit to the CK pin in order to obtain a better operation. This circuit is showed in figure 9. R1-R2 and C2 form a low pass filter, which allows a reduction of the ringing amplitude. But R1-R2 and C2 also cause an undesired delay, so the R3 and C1 group reduce this delay during fast switching transitions.

Figure 9: Filter to CK input

	FREE WHEEL					FORWARD		Product(s)
R3			7	8	1
			Obsolete
			OUTGate2	PWRGND	OUTGate1			+5V
C1	R1						Vcc	2
		4	Ck					3
							SETANT
C2				STSR2P
	R2
		6-
							INHIBIT	5
Product(s)			SGLGND
As mentioned in the previous paragraph, if the input voltage variability range is higher than 1:2, at high
voltage the signal at the CK pin will be clamped. In these conditions, both switching transition waveform
and the sinusoidal waveform are clamped and the peak detector is unable to operate correctly (see figure
Obsolete

10). In this case it is possible to use an external signal, which turns off completely the device in no load or light load conditions (figure 8).

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