ST AN1645 Application note

AN1645

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APPLICATION NOTE

STSR2P/STS R2PM SIMPLIFIES IMPLEMENTATION OF

SYNCHRONOUS RECTIFIE RS IN FORWARD CON VERTER

F. Librizzi - F. Lentini

1. ABSTRACT

This paper describes t he functionality and the operation of t he STSR2P devi ce used as the s econdary
synchronous rectifier driver in Forward t opolog y switched mo de powe r su pplies. A s chem at ic and l ayout
description of a demo board, able to replace d iode rectification with s ynchronous rectification in Forward
converters, is shown below.

Figure 1: Typical Application Schematic

Feedback

Loop

TRANSFORMER

PWM

2. GENERAL DEVICE DESCRIPTION

MosfetN
Q1

MosfetN
Q2

1

8

OUTGate1

PWRGND

STSR2

option

P

D1

7

OUTGate2

5

INDUCTOR

Cout

100nF

INHIBIT

2

Vcc

SGLGND

SETANT

D2

+5V

VoutVin

+5V

100nF

6

3

4

Ck

D3

R5

+5V

R1

R2

R3

R4

The STSR2P Sm art Driver IC provi des two compl ementary high current ou tputs to drive Po wer Mosfets.
The IC is dedicated t o properly drive secondary Synchronous Rectifiers in medium power, low output
voltage, high efficiency Forward Converters. From a synchronizing clock input, the IC generates two
driving signals with a certain dead time between complementary pulses. The adopted transitions

December 2003 (rev.1)

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revelation mechanism makes circuit operation independent by the forward magnetic reset technique
used, avoiding most of the common problems inherent in self-driven synchronous rectifiers. The IC
operation prevents secondary side shoot-th rough conditions providing proper timing at the ou tputs turn­off transition. This smart function operates through a fast cycle-after-cycle control logic mechanism
based on an intern al hig h fre quenc y os cillator, synchronized by the clock signal. The I C prov ides a fixed
anticipation in turning-off the OUTGate1 with respe ct to the clock signal transition, while the anticipation
in turning-off the OUTGate2 can be set through external components. A speci al Inhibit function allows
the shut-off of one of the two outputs allowing operation during discontinuous conduction mode and
preventing the freewheeling mosfet from sinking current from the output.
The STSR2P automatically turns off the outputs when duty-cycle is lower than 13%, while STSR2PM
works even at very low duty-cycle values.
.

3. PIN CONNECTIONS AND DESCRIPTIONS

The STSR2P is housed in a SO-8 package for SMD assembly. Device pin out is shown in figure 2 and
table 1 briefly summarizes the device pin functionality.

Figure 2: Pin Configuration

Table 1: Pin Configuration

Pin Number Pin Name Pin Function

1 OUTGate1 Output for Forward MOSFET Gate Drive
2 Vcc Supply input from 4V to 5.5V

3 SETANT
4 CK Synchronization for IC’s operation

5 INHIBIT Discontinuous Mode Detector
6 SGLGND Reference for all the control logic signals
7 OUTGate2 Output for Freewheeling MOSFET Gate Drive
8 PWRGND Reference for power signals

2

Sets the anticipation in turning-off the OUT

GAT E2

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Figure 3: Block Schematic

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4. SUPPLY VOLTAGE AND UNDER VOLTAGE LOCK-OUT

The supply input range is from 4V to 5.5V. An internal zener diode limits the maximum voltage to 5.7V .
A 100nF ceramic capacitor must be connected to Vcc and SGLGND pin in order to assure a stable
supply voltage. This capacitor must be placed very close to the device. Another 100nF capacitor is
necessary between Vcc and PWRGND.
Under Voltage Lock Out feature guarantees p ro per start-up while it avoid s undesirable driving during
eventual dropping of the supply voltage.
As shown in the Block Diagram, the V cc voltage also supplies the two out put drivers, consequent ly the
maximum driving voltage is 5.5V, so the use of logic gate threshold mosfets is recommended.

5. SYNCHRONIZATION

An innovative feature of the STSR2P is the capability to operate in the secondary side without any
synchronization signal coming from the primary side. The IC synchronization is obtained directly from the
secondary side using the voltage across the free wheeling mosfet as the information f or the switching
transitions. The Ck pin is the input for the synchronization signal; t he internal thresho ld is set at 2.8V. As
can be seen in figure 3, a Peak Detector is present at the Ck pin. This block is able to distinguish
between the primary mosfet switching transitions and the eventual sinusoidal waveform caused by
discontinuous mode operation (see figure 4). A wrong synchronization causes wrong driving of the
synchronous rectifiers.

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Figure 4: DCM waveform

V

V

1

1

Peak

Peak
Detector

Detector
Input

Input

Peak

Peak
Detector

Detector
Output

Output

On

On
Time

Time

Off Time Dead Time

Off Time Dead Time

5.1 Continuous Conduction Mode

When the converter is working in continuous mode the voltage ac ross the source and drain of t he free
wheeling mosfet has a square shape. This voltage can be applied to the Ck pin using two different
configurations: with a resistor divider (figure 6) or with a diode and pull-up resistor (figure 7). In most
cases a spike is present during turn-off of the synchronous m osfet; this spike m ust be eli minated at t he
Ck pin in order to avoid false synchronization.
Using the resistor divider , the spike is eliminated by adding a small capacitor (C1) as shown in figure 6.

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Figure 5: CCM waveform and Ck circuit

Turn-Off

Turn-Off
Spike

Spike

On Time Off Time

On Time Off Time

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In a typical Forward converter for telecom application, the DC input voltage has a 1:2 va riability range
(typically 36V-72V). Consequently the secondary winding voltage has also 1:2 variability. The resistor
divider can be calculated in order t o have about 2.8V at the Ck pin at 36V inp ut; at 72V in put, t he Ck pi n
reaches 5.6V. Even if this value is higher than the maximum voltage on the CK pi n, it can be accepted
limiting the current flowing into the pin to 10mA.

Figure 6: Synchronization with a resistor divider

FREE WHEEL FORWARD

1

+5V

2

PWRGND

OUTGate1

SETANT

INHIBIT

Vcc

3

5

+5V

D1

C1

R1

R2

4

6

7

OUTGate2

Ck

SGLGND

8

STSR2P

In case the Forward converter has a higher variability range 1:3 or 1:4, at minimum input voltage, 2.8V
must be guaranteed at the Ck pin. At maximum input voltage, the voltage at the Ck pin will be 7.5V or
10V. This voltage exceeds the absolute maximum ratings of the device. If R2 limits the current flowing
into the Ck pin to a va lue below the maximum Ck current value indicated in t he datasheet (10mA), the

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device can still working properly; otherwise a diode D1 connected to Vcc or a zener diode must be added
to protect the device.

Figure 7: Synchronization with a diode and pull-up resistor

+5V

FREE WHEEL

D1

R1

4

6

7

OUTGate2

Ck

SGLGND

8

PWRGND

STSR2P

1

OUTGate1

SETANT

INHIBIT

FORWARD

Vcc

+5V

2

3

5

Figure 7 shows the synchronization circuit with diode and pull-up resistor. In this case there is no
problem with the turn-off spike and maximum CK pin voltage. This circuit cannot work properly in
Discontinuous Mode due to the ringing present in the voltage drain of the synchronous rectifier.

Figure 8: Shut-down circuit

FREE WHEEL FORWARD

1

8

7

D1

R1

+5V

OFF

R2

The STSR2P can be easily turned off adding a NPN transistor between Ck and SGLGND. This transistor

Q1
NPN

4

6

Ck

SGLGND

PWRGND

OUTGate2

STSR2P

OUTGate1

SETANT

INHIBIT

Vcc

+5V

2

3

5

forces the CK pin to GND wh en the sign al OFF is high . In this condition O UTGate1 and O UTGate2 wil l
be in a low state turning off the Synchronous Mosfets.

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Figure 8 shows the turn-off circuit when using a diode and pull-up resistor to synchronize the STS R2P,
the same configuration of Q1 and R2 can be used with a resistor divider circuit.

5.2 Discontinuous Conduction Mode

As shown in figure 4, in d iscontinuous mode operation there can be some proble ms in detecting the
primary switching transitions. The internal peak detector is only able to determine the peak value
reached by the signal at the Ck pin, neglecting all signals that have a lower value. A minimum voltage
difference V1=400mV between the switching transition waveform and the sinusoidal waveform must be
assured in order to allow the Peak Dete ctor to work properly. If the ringing presents almo st the same
value as the square w aveform, it is pos sibl e to add a filter circuit to the CK pin in order to obtain a be tter
operation. This circuit is showed in figure 9. R1-R2 and C2 form a low pass filter, which allows a reduction
of the ringing am plitude. But R1-R2 and C2 also cause an undesired delay, so the R3 and C1 group
reduce this delay during fast switching transitions.

Figure 9: Fi lter to C K input

FREE WHEEL FORWARD

PWRGND

STSR2P

1

OUTGate1

SETANT

INHIBIT

Vcc

+5V

2

3

5

R3

C1

C2

R1

R2

4

6

7

OUTGate2

Ck

SGLGND

8

As mentioned in the previous paragraph, if the input voltage variability range is higher than 1:2, at high
voltage the signal at the CK pin will be clamped. In these conditions, both switching transition waveform
and the sinusoidal waveform are clamped and the peak detector is unable to operate correctly (see figure

10). In this case it is possible to use an external signal, which turns off completely the device in no load or
light load conditions (figure 8).

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