ST AN1636 Application note

AN1636

APPLICATION NOTE

UNDERSTANDING AND MINIMISING ADC CONVERSION ERRORS

By Microcontroller Division Applications

1 INTRODUCTION

The purpose of this document is to explain the different ADC errors and the techniques that application developers can use to minimise them. The ADC (Analog to Digital Converter) is an important peripheral that connects the analog world to the digital world of microcontrollers.

In this application note the ADC embedded in the ST7 microcontroller is used as an example, however the same principles to apply to other ADCs.

The accuracy of analog to digital conversion has an impact on overall system quality and efficiency. To be able to improve accuracy you need to understand the errors associated with the ADC and the parameters affecting them.

The ADC itself, cannot ensure the accuracy of results, It depends on your overall system design. For this reason, you need to do some careful preparation before starting your development.

Lots of parameters affect the ADC accuracy depending on the application. Some of these factors are: PCB layout, voltage source, I/O switching and analog source impedance.

AN1636/0603

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1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 WHAT IS AN ADC? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 ADC BLOCK DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 ANALOG INPUT PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 ANALOG MULTIPLEXER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 SAMPLE AND HOLD CIRCUIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4 CONTROL BLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.5 ANALOG SUPPLY AND REFERENCE . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3 ADC TERMINOLOGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1 REFERENCE VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2 RESOLUTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.3 QUANTIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.4 MONOTONICITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.5 BIPOLAR AND UNIPOLAR ADC INPUT . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.6 HARDWARE AVERAGING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.7 SAMPLING THEOREM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4 SOURCES OF ERROR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.1 POWER SUPPLY NOISE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.2 POWER SUPPLY REGULATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.3 ANALOG INPUT SIGNAL NOISE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.4 EFFECT OF ANALOG SOURCE RESISTANCE . . . . . . . . . . . . . . . . . . . 19 4.5 EFFECT OF SOURCE CAPACITANCE . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.6 EFFECT OF INJECTION CURRENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.7 I/O PIN CROSS-TALK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.8 EMI-INDUCED NOISE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

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5 DIFFERENT TYPES OF A/D CONVERTER ERRORS . . . . . . . . . . . . . . . . . . 27 5.1 OFFSET ERROR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.2 GAIN ERROR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.3 DIFFERENTIAL LINEARITY ERROR . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.4 INTEGRAL LINEARITY ERROR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.5 TOTAL UNADJUSTED ERROR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

6 PCB LAYOUT RECOMMENDATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7 HOW POWER SAVING MODES AFFECT THE ADC . . . . . . . . . . . . . . . . . . . 39 8 RELATED DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

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1 WHAT IS AN ADC?

An analog to digital converter is a peripheral which converts analog signals in a defined range to the digital outputs.

In the real world, signals are mostly available in analog form. To use a microcontroller in this type of system, an ADC is required, so that the signals can be converted to the digital values. The application software can then process the digital outputs and take decisions depending on the application or system requirements.

The limitation imposed by the finite number of digital outputs decides how close the output is to the analog input. The more bits there are in the output, the closer the digital result will be to the analog signal. In other words, the resolution of the ADC is defined by the number of bits in the digital result (8 bits, 10 bits etc) and the input voltage range.

Successive Approximation Method

Different techniques are available for converting analog signals to digital outputs. The Successive approximation method is the most popular technique. It is also known as Successive approximation Register (SAR) technique. This technique uses binary search method. It consists of a high speed comparator, DAC (digital to analog converter), and control logic. Refer to Figure 1.

Figure 1. Successive Approximation Block Diagram

VIN	+
	+		Control
			Control
From Sample	-	VAREF	Logic
From Sample		VAREF
and Hold		Comparator
		DAC	n bit register
			Digital Output

The SAR starts by forcing the MSB (Most Significant bit) high (for example in an 8 bit ADC it becomes 1000 0000), the DAC converts it to VAREF/2. The analog comparator compares the input voltage with VAREF/2. If the input voltage is greater than the voltage corresponding to the MSB, the bit is left set, otherwise it is reset.

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VAREF is the reference voltage used by ADC for conversions. The details are mentioned in Section 2.5

After this comparison is done, the next significant bit is set (=VAREF/4) and a comparison is done again with the input voltage. The procedure is followed till all the bit positions are com-

pared.

At the end of all the bit comparisons we get the corresponding digital output for the analog input.

The successive approximation steps are shown in Table 1. As you can see, the digital output obtained from the ADC is B2h when the analog input is 3.5V.

Table 1. 8-bit ADC successive approximation steps

Steps			Vin = 3.5v, VAREF= 5V
	Digital code	DAC output		Comparator	digital output
	Digital code	DAC output		output	(for steps)
				output	(for steps)

1	1000 0000	2.5v		1	1000 0000

2	1100 0000	3.76v		0	1000 0000

3	1010 0000	3.13v		1	1010 0000

4	1011 0000	3.45		1	1011 0000

5	1011 1000	3.6		0	1011 0000

6	1011 0100	3.52		0	1011 0000

7	1011 0010	3.49		1	1011 0010

8	1011 0011	3.509		0	1011 0010

Final output = B2h

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2 ADC BLOCK DESCRIPTION

Figure 2. ADC Block diagram

fCPU

DIV 4

fADC

DIV 2

(e)

VAREF

VSSA

EOC SPEEDADON

CH3

CH2

CH1

CH0

ADCCSR

(f)

AIN0

AIN1

Sample and

Successive

ANALOG

Hold circuit

Approximation

MUX

Block

(c)

(d)

AINx

(a)

(b)

ADCDRH

ADCDRL

The ADC can be divided into the following blocks.

a.Analog input pins

b.Analog multiplexer

c.Sample and Hold circuit

d.Successive approximation block

e.Control block

f.Analog supply/ reference

2.1 ANALOG INPUT PINS

Several analog input pins are available to connect different analog signals. These are internally multiplexed to use same sample and hold circuit and SAR logic.

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Figure 3. Electrical diagram of typical ADC application

		VDD
		VT
RAIN		0.6V
RAIN	AINx		RADC	10-Bit A/D
VAIN				Conversion
	CAIN	VT	IL	CADC
		0.6V	IL	CADC
			±1μA

Configuring the analog pin

Choose any I/O port that has analog input capability (AIN alternate function) and configure it as floating input. You can do this by writing ‘0’ in the DDR and OR register bits of the corresponding port. At reset, most of the ST7 IOs are configured by default as floating input.

The pin should NOT be configured as floating input with pull-up. This configuration reduces the ADC accuracy. The reason being the potential divider formed between the pull-up resistance and RADC. Also some current flows from VDD to the analog source. This current is drawn

from the VDD supply. Also there is a potential divider formed between VDD, RPU and RAIN, where RAIN is the series impedance of the voltage source.

Figure 4. Analog input with pull-up

NOT RECOMMENDED

RPU should not be enabled.		VDD

Current

from VDD

\/\/\/\/\/

RAIN

VIN

\/\/\/\/\/\	RPU

RADC

\/\/\/\/\/\/

CADC

VSSA (Analog Ground)

Configuring the analog input as floating input with pull-up ( instead of floating input ) will cause more current to be drawn from the VDD supply.There is also an affect on the accuracy of the ADC and the digital output converted by ADC may not be accurate.

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Analog Pin Input Impedance

RADC and CADC (hold capacitor) define the input impedance of the analog pins. RADC is also called as Rss (Resistance of sampling switch and internal trace/resistance). Please refer to the Sample and Hold circuit explanation in Section 2.3.

If the hold capacitor is fully discharged, the minimum input impedance is RADC. As the hold capacitor starts to charge, the current flowing into the pin will reduce. If the hold capacitor is charged to a level equal to the external voltage there will be only minimal charging current flowing into the analog input.

Figure 5. Analog input pin Impedance

\/\/\/\/\/\/

RADC

Input

CADC

impedance

Zi = RADC + CADC

VSSA (Analog Ground)

The minimum input impedance of the analog pin is thus RADC. In the datasheet the maximum value of RADC is specified instead of a typical value, so that the user can calculate the affect of external resistance on sampling. This is explained in Section 4.4.

2.2 ANALOG MULTIPLEXER

The ADC can have several analog input pins. These pins are connected internally to the Analog to Digital converter using the analog multiplexer. You can select each pin simply by writing in the appropriate control register. This allows a single Sample and Hold circuit and Analog to Digital Converter block to be used to convert several analog input sources.

This allows you to switch the analog channels and convert them one by one through software control.

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Figure 6. Analog multiplexer

AIN0

AIN1

AIN2

To Sample and Hold

Circuit

Analog Input AIN7

Channels

Channel selection bits = 010 selects

AIN2

CH[2:0] = 010

2.3 SAMPLE AND HOLD CIRCUIT

The sample and hold circuit samples the input signal and charges the internal hold capacitor

CADC to the voltage equal to VIN through RADC. The analog pin is then disconnected and the voltage across the capacitor is then converted to digital code using successive approximation.

Figure 7. Sample and Hold circuit

Electrically operated

switch

VIN

\/\/\/\/\/\/

RADC

From Analog

CADC

Multiplexer

VSSA (Analog Ground)

The sample and hold circuit consists of an electrically operated analog switch, internal charging resistance and hold capacitor.

As soon as the ADC conversion starts, the electrically operated switch is closed, connecting the hold capacitor to the analog input through the internal ADC resistance RADC. This causes a charging current to flow into the analog input and the capacitor starts to charge. The time the switch remains closed is decided by the fADC. It is called sampling time. The sampling time is generally indicated in the datasheet as a multiple of fADC clock periods.

Time period tAD = 1/fADC

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Figure 8. Sample and Hold timing and electrical diagram

Sampling

Hold Time

Time

Conversion time

tAD

= 1/fADC

Vc = Voltage developed

Sampling

across capacitor.

Electrically operated

Vc = VIN

Switch = Closed

VIN

RADC

\/\/\/\/\/\/

Charging

CADC

+ leakage current

SSA

Hold and Conversion

Capacitor

time

Sampling

Electrically operated

charged=VIN

time

Switch = Open

VIN

RADC

SAR

\/\/\/\/\/\/

Leakage

CADC

Current

VSSA

Note: Please refer to product datasheet for Sample and Hold timing for ADC. SAR = Successive Approximation Register block.

After the sampling time, the input capacitor has the same voltage as the input, the analog switch is then disconnected from the input and successive approximation conversion is started, to convert the voltage stored in the hold capacitor. This time is known as Hold time. It is also expressed in multiples of tAD (1/fADC).

The total conversion time of the ADC is the addition of sampling time and hold time. The sample and hold circuit is also known as track and hold.

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2.4 CONTROL BLOCK

This block consists of logic which controls the sample and hold circuit, starts the SAR and then generates the conversion of the ‘conversion complete’ signal for the microcontroller.

2.5 ANALOG SUPPLY AND REFERENCE

Depending on microcontroller and packaging, the analog supply pins are generally available on the package.

VDDA - analog supply ( or, VAREF - reference voltage)

VSSA- analog ground.

If these pins are not available the VDDA (analog supply) is shorted to VDD and VSSA is shorted to VSS internally.

Separate analog power supply pins are available to the user to improve the ADC performance. It is recommended to put the filtering capacitor between VDDA and VSSA so that power supply noise ( or ripples) on VDDA are filtered and do not affect the ADC accuracy.

The VAREF pins are available instead of VDDA when the analog supply voltage can be different from the VDD. You may choose to keep VAREF shorted to VDD if a dual supply is to be avoided.

Figure 9. Analog Supply block

	1 to 10μF	10pF	ST72XXX		ST72xx
	1 to 10μF	(if needed) 0.1μF	VSS
		(if needed) 0.1μF	VSS
	ST7
	DIGITAL NOISE
	FILTERING		VDD		VDD
VDD			VDD		VDD
VDD				/\/\/\/\/\/\
POWER		10pF		/\/\/\/\/\/\
SUPPLY		10pF
SUPPLY		(if needed) 0.1μF	VDDA		VAREF
SOURCE		(if needed) 0.1μF	VDDA		VAREF
SOURCE
		EXTERNAL		/\/\/\/\/\/\
		NOISE
		FILTERING	VSSA		VSSA
			VSSA		VSSA
	RECOMMENDED				NOT RECOMMENDED

As these pins provide power supply to the analog block, you should not connect a resistor in

series with VAREF. This will cause the voltage to drop due to the current flowing through the resistor and hence will affect the accuracy of the ADC.

Do not leave the VDDA/VAREF, VSS pins unconnected. If your application does not use the ADC, you must connect these pins as follows: VDDA must be connected to VDD, and VSSA

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must be connected to the VSS of the microcontroller. VSSA cannot have any voltage other than VSS.

Make sure that VAREF is not greater than VDD. There is a protection diode from VAREF to VDD. Similarly VSSA should not be less than or greater than VSS. There are protection diodes con-

nected back-to-back between VSSA and VSS.

Figure 10. Multisupply Configuration

VDD	VAREF
	VAREF
VAREF
VSS
	BACK TO BACK DIODE
	BETWEEN GROUNDS
VSSA	VSSA

3 ADC TERMINOLOGY

There are some terms associated with the ADC which we should understand before we move further.

3.1 REFERENCE VOLTAGE

The ADC requires a reference voltage to which the analog input is compared to produce the digital output. The digital output is the ratio of the analog input with respect to this reference voltage.

digital value =((Analog input voltage)/(reference voltage highreference voltage low)) * (2n-1)

where n = number of bits of ADC digital output.

The reference voltage is the maximum input voltage that can be converted by the ADC. VAREF is the reference voltage for the ADC. If VAREF is not available VDDA is used as reference.

For example: for 10-bit ADC, VIN=1V, VAREF=5V,

Digital value = (1V/5V ) *1023 = 204d = 0CCh

3.2 RESOLUTION

The ADC resolution is defined as the smallest incremental voltage that can be recognized and hence it causes a change in the digital output. It is usually expressed as the number of bits output by the ADC.

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Hence an ADC which converts the analog signal to a 10-bit digital value, has a resolution of 10 bits.

The smallest incremental voltage that can be recognized is expressed in terms of LSB.

1LSB = (VAREF - VSSA)/2n

where LSB = Least significant bit.

n = number of bits output by the ADC.

VAREF = Reference voltage

VSSA = Analog ground

n n

An ADC which has ‘n’ bit digital output, provides 2 digital values. It includes both 0 and 2 -1.

With a 5V reference voltage, the resolution is 5 (volts) /210 = 5 (volts)/1024 = 4.88 mV.

This means that for a change in 4.88mV analog input the ADC converted digital value will change by 1LSB.

In reality there are 2n-1 steps. So the actual resolution is 1LSB = (VAREF - VSSA)/(2n -1). As in practice there is very little difference between the two calculated values because ‘n’ is quite a

large number, both definitions are used.

Figure 11. Resolution representation

Digital		3FFh
Output

N+1
N

		Resolution

00h
				Analog


	n (n+1)		VAREFInput

VAREF VAREF

3.3 QUANTIZATION

In theory, the continuous analog signal can be broken into an infinite number of digital steps, but the quantization of an analog signal by the ADC can be done only in the finite number of steps which can be produced by the ADC.

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