ST AN1636 Application note

AN1636

APPLICATION NOTE

UNDERSTANDING AND MINIMISING ADC CONVERSION

ERRORS

By Microcontroller Division Applications

1 INTRODUCTION

The purpose of this do cum ent is to ex plai n th e diffe rent ADC e rrors an d t he tech niques tha t
application developers can use to minimise them. The ADC (Analog to Di gital Converter) is an
important peripheral that connects the analog world to the digital world of microcontrollers.

In this application note the ADC embedded in the ST7 microcontroller is used as an example,
however the same principles to apply to other ADCs.

The accuracy of analog to digital conversion has an impact on overall system quality and effi­ciency. To be able to improve accuracy you need to understand the err ors associated with the
ADC and the parameters affecting them.

The ADC itself, cannot ensure the accuracy of results, It depends on your overall system de­sign. For this reason, you need to do some careful pr eparation befor e starting your dev elop­ment.

Lots of parameters affect the ADC accuracy depending on the application. Some of these fac­tors are: PCB layout, voltage source, I/O switching and analog source impedance.

AN1636/0603 1/42

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UNDERSTANDING AND MINIMISING ADC CONVERSION ERRORS

1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1 WHAT IS AN ADC? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 ADC BLOCK DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.1 ANALOG INPUT PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.2 ANALOG MULTIPLEXER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.3 SAMPLE AND HOLD CIRCUIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.4 CONTROL BLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.5 ANALOG SUPPLY AND REFERENCE . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3 ADC TERMIN OLOGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.1 REF ERENCE VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.2 RESOLUTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.3 QUANTIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.4 MONOTONICITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.5 BIPOLAR AND UNIPOLAR ADC INPUT . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.6 HARDWARE AVERAGING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.7 SAMPLING THEOR EM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4 SOURCES OF ER ROR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.1 POWER SUPPLY NOISE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.2 POWER SUPPLY REGULATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.3 ANALOG INPUT SIGNAL NOISE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.4 EFFECT OF ANALOG SOURCE RESISTANCE . . . . . . . . . . . . . . . . . . . 19

4.5 EFFECT OF SOURCE CAPACITANCE . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.6 EFFECT OF INJECTION CURRENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.7 I/O PIN CROSS-TALK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.8 EMI-INDUCED NOISE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

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UNDERSTANDING AND MINIMISING ADC CONVERSION ERRORS

5 DIFFERENT TYPES OF A/D CONVERTER ERRORS . . . . . . . . . . . . . . . . . . 27

5.1 OFF SET ERROR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

5.2 GAIN ERROR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.3 DIF FERENTIAL LINEARITY ERROR . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.4 INT EGRAL LINEARITY ERROR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

5.5 TOTAL UNADJUSTED ERROR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

6 PCB LAYOUT RECOMMENDATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

7 HOW POWER SAVING MODES AFFECT THE ADC . . . . . . . . . . . . . . . . . . . 39

8 RELATED DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

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UNDERSTANDING AND MINIMISING ADC CONVERSION ERRORS

1 WHAT IS AN ADC?

An analog to digital converter is a peripheral whi ch converts analog signal s in a defined range
to the digital outputs.

In the real world, signals are mostly available in analog form. To use a microcontroller in this
type of system, an ADC is required, so that the signals can be converted to the digital values.
The application s oftwa re c an t hen pr ocess th e di gital ou tputs and t ake deci sions de pending
on the application or system requirements.

The limitation imposed by the finite number of digital outputs decides how close the output is
to the analog input. The more bits there are in the output, the closer the digital result will be to
the analog signal. In other words, the resolution of the ADC is defined by the number of bits in
the digital result (8 bits, 10 bits etc) and the input voltage range.

Successive Approximation Method

Different techniques are available for converting analog signal s to digital outputs. The Succes­sive approximation method is the most popular technique. It is also known as Successive ap­proximation Register (SAR) technique. This technique uses binary search method. It consists
of a high speed comparator, DAC (digital to analog converter), and control logic. Refer to
Figure 1.

Figure 1. Successive Approximation Block Diagram

V

IN

+

Control

From Sample
and Hold

­Comparator

DAC

V

AREF

Logic

n bit register

Digital Output

The SAR starts by forcing the MSB (Most Significant bit) high (for example in an 8 bit ADC it
becomes 1000 0000), the D AC converts it to V
input voltage with V

/2. If the input voltage is greater than the voltage corresponding to the

AREF

/2. The analog comparator compares the

AREF

MSB, the bit is left set, otherwise it is reset.

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UNDERSTANDING AND MINIMISING ADC CONVERSION ERRORS

V

is the reference voltage used by ADC for conversions. The details are mentioned in

AREF

Section 2.5

After this compa rison is done, th e next signifi cant bit is set (=V

/4) and a comparison is

AREF

done again with the input voltage. The procedure is followed till all the bit positions are com­pared.

At the end of a ll th e bi t c o mp aris on s w e get the cor resp on di ng d i gita l o ut pu t for the a na log
input.

The successive approximation steps are shown in T able 1. As you can see, the digital output
obtained from the ADC is B2h when the analog input is 3.5V.

Table 1. 8-bit ADC successive approximation steps

Steps Vin = 3.5v, V

Digital code DAC output

1 1000 0000 2.5v 1 1000 0000
2 1100 0000 3.76v 0 1000 0000
3 1010 0000 3.13v 1 1010 0000
4 1011 0000 3.45 1 1011 0000
5 1011 1000 3.6 0 1011 0000
6 1011 0100 3.52 0 1011 0000
7 1011 0010 3.49 1 1011 0010
8 1011 0011 3.509 0 1011 0010

Comparator

AREF

output

= 5V

digital out put

(for steps)

Final output = B2h

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UNDERSTANDING AND MINIMISING ADC CONVERSION ERRORS

2 ADC BLOCK DESCRIPTION

Figure 2. ADC Block diagram

f

CPU

AIN0

V

V

(f)

AREF

SSA

DIV 4

DIV 2

0

f

ADC

1

CH3

CH2 CH1EOC SPEED ADON 0 CH0

4

(e)

ADCCSR

AIN1

ANALOG

MUX

AINx

(a) (b)

ADCDRH

ADCDRL

The ADC can be divided into the following blocks.
a. Analog input pins
b. Analog multiplexer
c. Sample and Hold circuit
d. Successive approximation block
e. Control block

Sample and
Hold circuit

(c)

000000

Successive
Approximation
Block

D4 D3D5D9 D8 D7 D6 D2

(d)

D1 D0

f. Analog supply/ reference

2.1 ANALOG INPUT PINS

Several analog input pins are ava ilable to connect different analog signals. These are inter­nally multiplexed to use same sample and hold circuit and SAR logic.

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UNDERSTANDING AND MINIMISING ADC CONVERSION ERRORS

Figure 3. Electrical diagram of typical ADC ap plication

V

DD

V

T

R

V

AIN

AIN

AINx

C

AIN

0.6V

V

T

0.6V

R

ADC

I

L

±1µA

10-Bit A/D
Conversion

C

ADC

Configuring the analog pin

Choose any I/O port that has analog input c apability (AIN alternate function) and configure it
as floating input. You can do this by writing ‘0’ in the DDR and OR register bits of the corre­sponding port. At reset, most of the ST7 IOs are configured by default as floating input.

The pin shou ld NO T b e c onfig ured as f loati ng input wi th pul l-up. Th is con figur ation redu ce s
the ADC accuracy. The reason being the potential divider formed between the pull-up resist­ance and R
from th e V
where R

AIN

. Also some current flows from VDD to the analog source. This current is drawn

ADC

supply. Also there is a potential divider formed between VDD, RPU and R

DD

is the series impedance of the voltage source.

AIN,

Figure 4. Analog input with pull-up

NOT RECOMMENDED

V

RPU should not be enabled.

Current
from V

\/\/\/\/\/

V

IN

DD

R

AIN

DD

R

PU

\/\/\/\/\/\

\/\/\/\/\/\/

R

ADC

C

ADC

V

(Analog Ground)

SSA

Configuring the analog input as floating input with pull-up ( instead of floating input ) will cause
more current to be drawn from the V

supply.There is also an affect on the acc uracy of the

DD

ADC and the digital output converted by ADC may not be accurate.

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UNDERSTANDING AND MINIMISING ADC CONVERSION ERRORS

Analo g Pin In put Impedanc e

R

ADC

and C

(hold capacitor) define the input impedance of the analog pins. R

ADC

ADC

is also
called as Rss (Resis tance of samp ling switch an d internal trace /resista nce). Please r efer to
the Sample and Hold circuit explanation in Section 2.3.

If the hold capacitor is fully di scharged, the minimum input impedance is R

. As the hold ca-

ADC

pacitor starts to charge, the curre nt flowing into the pin w ill reduce. If the hold cap acitor is
charge d to a lev el equ al to the ext ernal v oltage there will b e only minima l char ging curre nt
flowing into the analog input.

Figure 5. Analog input pin Impedance

R

ADC

\/\/\/\/\/\/

Input

C

impedance

Zi = R

ADC

+ C

ADC

The minimum input impedance of the analog pin is thus R
value o f R

is specified instead of a typical value, so that the user can calculate the affect

ADC

ADC

V

(Analog Ground)

SSA

. In the datasheet the maximum

ADC

of external resistance on sampling. This is explained in Section 4.4.

2.2 ANALOG MULTIPLEXER

The ADC can have several analog input pins. These pins are connected internally to the An­alog to Digital converter using the analog multiplexer. You can select each pin simply by
writing in the appropriate control register. This allows a single Sample and Hold circuit and An­alog to Digital Converter block to be used to convert several analog input sources.

This allows you to switch the analog channels and convert them one by one through software
control.

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UNDERSTANDING AND MINIMISING ADC CONVERSION ERRORS

Figure 6. Analog multiplexer

AIN0
AIN1

AIN2

To Sample and Hold
Circuit

Analog Input

AIN7

Channels

Channel selection bits = 010 selects
AIN2

CH[2:0] = 010

2.3 SAMPLE AND HOLD CIRCUIT

The sample and hold circuit samples the input signal and charges the internal hold capacitor

to the voltage equal to V

C

ADC

through R

IN

. The analog pin is then disconnected and the

ADC

voltage across the capacitor is then converted to digital code using successive approximation.

Figure 7. Sample and Hold circuit

Electrically operated
switch

V

IN

R

ADC

\/\/\/\/\/\/

From Analog
Multiplexer

C

ADC

V

(Analog Ground)

SSA

The sa mpl e and hol d ci rcuit cons ists of an e lectr ically ope rated ana log s witc h, in terna l
charging resistance and hold capacitor.

As soon as the ADC c onversion s tarts, the ele ctrically operated switch i s closed, connect ing
the hold capacitor to the analog input through the internal ADC resistance R

. This causes

ADC

a charging current to flow into the analog input and the capacitor starts to charge. The time the
switch remains closed is decided by the f
generally indicated in the datasheet as a multiple of f

Time period t

AD

= 1/f

ADC

. It is called sampling time. The sampling time is

ADC

clock periods.

ADC

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UNDERSTANDING AND MINIMISING ADC CONVERSION ERRORS

Figure 8. Sample and Hold timing and electrical diagram

Sampling
Time

tAD = 1/f

Sampling

V

IN

Charging
+ leakage current

Hold and Conversion

Conversion time

ADC

Electrically operated
Switch = Closed

R

ADC

\/\/\/\/\/\/

Electrically operated
Switch = Open

V

C

ADC

SSA

Hold Time

Vc

Capacitor
charged=V

Vc = Voltage developed
across capacitor.

Vc = V

IN

time

Sampling

IN

time

V

IN

\/\/\/\/\/\/

Leakage

R

ADC

C

SAR

ADC

Current

V

SSA

Note: Please refer to product datasheet for Sample and Hold timing for AD C.

SAR = Successive Approximation Register block.
After the sam pling time, the input capacitor has the same voltage as the input, the analog
switch is then di sconn ected f rom the inp ut an d succ essive appro ximation conver sion i s
started, to convert the voltage stored in the hold capacitor. This time is known as Hold time.
It is also expressed in multiples of t

AD

(1/f

ADC

).

The total conversion time of the ADC is the addition of sampling time and hold time. The
sample and hold circuit is also known as track and hold.

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UNDERSTANDING AND MINIMISING ADC CONVERSION ERRORS

2.4 CONTROL BLOCK

This block consists of logic which controls the sample and hold circuit, starts the SAR and then
generates the conversion of the ‘conversion complete’ signal for the microcontroller.

2.5 ANALOG SUPPLY AND REFERENCE

Depending on microcontroller and packaging, the anal og supply pins are g enerally available
on the package.

- analog supply ( or, V

V

DDA

- analog ground.

V

SSA

If these pins are not available the V
to V

internally.

SS

- reference voltage)

AREF

(analog supply) is shorted to VDD and V

DDA

is shorted

SSA

Separate analog power supply pins are available to the user to improve the ADC performance.
It is recommended to put the filtering capacitor between V
noise ( or ripples) on V

The V
from the V

pins are available instead of V

AREF

. You may choose to keep V

DD

are filtered and do not affect the ADC accuracy.

DDA

when the analog supply voltage can be different

DDA

shorted to VDD if a dual supply is to be avoided.

AREF

DDA

and V

so that power supply

SSA

Figure 9. Analog Supply block

V

DD

POWER
SUPPLY
SOURCE

1 to 10µF

ST7
DIGITAL NOISE
FILTERING

(if neede d)

(if ne eded)

EXTERNAL
NOISE
FILTERING

10pF

10pF

0.1µF

0.1µF

ST72XXX

V

SS

V

DD

V

DDA

V

SSA

/\/\/\/\/\ /\

/\/\/\/\/ \/\

V

V

V

ST72xx

DD

AREF

SSA

NOT RECOMMENDEDRECOMMENDED

As these pins provide power supply to the analog block, you should not connect a resistor in
series with V

. This will cause the voltage to drop due to the current flowing through the re-

AREF

sistor and hence will affect the accuracy of the ADC.
Do not leave th e V

DDA/VAREF

ADC, you mu st connect these pins as follows: V

, VSS pins unconnected. If your application does not use the

must be connected to V

DDA

DD,

and V

SSA

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UNDERSTANDING AND MINIMISING ADC CONVERSION ERRORS

must be connected to the VSS of the microcontroller. V
V

.

SS

Make sure that V
Similarly V

should not be less than or greater than VSS. There are protection diodes con-

SSA

nected back-to-back between V

is not greater than VDD. There is a protection diode from V

AREF

and VSS.

SSA

cannot have any voltage other than

SSA

AREF

to VDD.

Figure 10. Multisupply Configuration

V

DD

V

AREF

V

SS

BACK TO BACK DIODE

V

SSA

BETWEEN GROUNDS

V

AREF

V

SSA

3 ADC TERMI NO L OGY

There are some terms associated with the ADC which we should understand before we move
further.

3.1 REFERENCE VOLTAGE

The ADC requires a reference voltage to which the analog input is compared to p roduce the
digital output. The digital outpu t is the ratio of the analog i nput w ith respec t to this reference
voltage.

n

digital value =((Analog input voltage)/(reference voltage high- reference voltage low)) * (2

-1)
where n = number of bits of ADC digital output.
The reference voltage is the maximum input voltage that can be converted by the ADC. V

is the reference voltage for the ADC. If V
For example: for 10-bit ADC, V

=1V, V

IN

is not available V

AREF

=5V,

AREF

is used as reference.

DDA

AREF

Digital value = (1V/5V ) *1023 = 204d = 0CCh

3.2 RESOLUTION

The ADC resolution is defined as the smallest incremental voltage that can be recognized and
hence it causes a chang e in the digita l output. It is usual ly expresse d as the numb er of bits
output by the ADC.

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UNDERSTANDING AND MINIMISING ADC CONVERSION ERRORS

Hence an ADC which converts the analog signal to a 10-bit digital value, has a resolution of 10
bits.

The smallest incremental voltage that can be recognized is expressed in terms of LSB.
1LSB = (V

AREF

- V

SSA

)/2

n

where LSB = Least significant bit.
n = number of bits output by the ADC.
V
V
An ADC which has ‘n’ bit digital output, provides 2
With a 5V reference voltage, the resolution is 5 (volts) /2

= Reference voltage

AREF

= Analog ground

SSA

n

digital values. It includes both 0 and 2n-1.

10

= 5 (volts)/1024 = 4.88 mV.

This means that for a change in 4.88mV analog input the ADC converted digital value w ill
change by 1LSB.

In reality there are 2

-1 steps. So the actual resolution is 1LSB = (V

AREF

- V

)/(2n -1). As in

SSA

n

practice there is very little difference between the two calculated values because ‘n’ is quite a
large number, both definitions are used.

Figure 11. Resolution representation

Digital
Output

3FFh

N+1

N

Resolution

00h

V

AREF

(n+1)

n

V

AREF

V

AREF

Analog
Input

3.3 QUANTIZATION

In theory, the continuous analog signal can be broken into an infinite number of digital steps,
but the quantization of an analog signal by the ADC can be done only in the finite number of
steps which can be produced by the ADC.

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