ST AN1625 APPLICATION NOTE

AN1625

APPLICATION NOTE

L6235 THREE PHASE BRUSHLESS DC MOTOR DRIVER

by Vincenzo Marano

Modern motion control applications need more flexibility that can be addressed only with specialized ICs products. The L6235 is a fully integrated motor driver IC specifically developed to drive a wide range of BLDC motors with Hall effect sensors. This IC is a one-chip cost effective solution that includes several unique circuit design features. These features, including a universal decoding logic that allows the device to be used with most common Hall effect spacing, will be described. The principal aim of this development project was to produce an easy to use, fully protected power IC. In addition several key functions as protection circuit and high speed PWM current control allow to drastically reduce the external components count to meet requirements for many different applications.

1 INTRODUCTION

For small-motor applications many appliance designers favor modern three phase brushless DC motors because of the high efficiency (as great as 95%) and small size for a given delivered power. Designers have to handle control logic, torque and speed control, power-delivery issues and ensure safe operation in every load condition. The L6235 is a highly i ntegrated, mixed-si gnal power IC that allows to easily design a co mplete motor control system for BLDC motor. Figure 1 shows the L6235 block diagram. The IC integrates six Power DMOS, a centralized logi c circuit to decode hall effect sensors and a constant t chronous mode) plus other added features for safe operation and flexibility.

PWM current contro l technique (Syn-

OFF

Figure 1. L6235 Block Diagram.

VBOOT V

VCP

DIAG

BRAKE

FWD/REV

RCPULSE

TACHO

BOOT

TACHO

MONOSTABLE

CHARGE

PUMP

OCD

HALL-EFFECT

10V 5V

VOLTAGE

REGULATOR

THERMAL

PROTECTION

OCD1 OCD2

OCD

SENSORS

DECODING

LOGIC

OCD3

ONE SHOT

MONOSTABLE

GATE

LOGIC

PWM

MASKING

TIME

BOOT

OCD1

10V

BOOT

OCD2

10V

BOOT

OCD3

10V

COMPARATOR

SENSE

OUT

SENSE

OUT

SENSE

VREF

RCOFF

D99IN1095B

October 2003

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AN1625 APPLICATION NOTE

Table of Contents

1 INTRODUCTION................................................................................................................................ 1

2 DESIGNING AN APPLICATION WI TH L623 5 ...................................................................................3

2.1 Current Ratings........................................................................................................................3

2.2 Voltage Rating s and Operating Range ....................................................................................3

2.3 Choosing th e Bulk Capacitor....................................................................................................5

2.4 Layout Considerations.............................................................................................................5

2.5 Sensing Resisto r.......... ............... ........................................................ ............................. ....... .7

2.6 Charge pump external components.........................................................................................8

2.7 Sharing the Charge Pump Circuitry .........................................................................................9

2.8 Reference Voltage for PWM Current Control.........................................................................10

2.9 Input Logic pins......................................................................................................................11

2.10 DIAG pin.................................................................................................................................11

2.11 Programmable off-time Monostable.......................................................................................12

2.11.1 Off-time Selection and minimum on-time ........................................................................14

2.11.2 Slow Decay Mode ...........................................................................................................14

2.12 Over Current Detection.........................................................................................................16

2.13 Powe r Management...............................................................................................................20

2.13.1 Maximum output current vs. selectable devices..............................................................20

2.13.2 Power Dissipation Formulae...........................................................................................21

2.14 The decoding logic................................................................................................................24

2.15 Tacho Outp ut and Speed Loop.............................................................................................25

2.15.1 Static performance - Speed Regulation vs. Resistant Torque: .......................................28

2.15.2 Dynamic performance:....................................................................................................29

2.15.3 Loop Stability:........................................................................................... .......................30

2.15.4 Reference voltage ripple: ................................................................................................30

2.16 Brake.....................................................................................................................................31

3 APPLICATION EXAM PL E.............................. ......................................................... .........................32

4 APPENDIX - EVALUATI ON BO ARD S...................................................................... .......................34

4.1 PractiSPIN............................................................................. .................................................34

4.2 EVAL6235N ...........................................................................................................................35

4.2.1 Important Not e s......... ................................... ......................................................... ....... ....36

5 REFERENCES....................................................................................... ..........................................39

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AN1625 APPLICATION NOTE

2 DESIGNING AN APPLICATION WITH L6235

2.1 Current Ratings

With MOSFET (DMOS) devices, unlike bipolar transistors, current under short circuit conditions is, at first approximation, limited b y the R and the two V

and VSB pins are rated for a maximum of 2.8 A r.m.s. and 5.6 A peak (typical values). These

values are meant to avoid damaging metal structures, including the metallization on the die and bond wires. In practical applications, though, maximum allowable current is less than these values, due to power dissipation limits (see Power Management section). The device has a built-in Over Current Detection ( OCD) that allows protection against shor t circuits between the outputs and between an output and ground (see Over Current Detection Section).

2.2 Voltage Ratings and Operating Range

The L6235 requires a single supply voltage (VS), for the motor supply. Internal voltage regulators provide the 5V and 10 V required for the internal circuitry. The operating range for V undesirable low supply voltage an Under Voltage Lock Out (UVLO) circuit shuts down the device when supply voltage falls below 6 V; to resume normal operating conditions, V vided to avoid false intervention of the UVLO function during fast V DMOS's R

is a function of the VS supply voltage. Actually, when VS is less than 10V, R

DS(ON)

affected, and this is particularly true for the High Side DMOS that are driven from V obtained through a charge pump fr om the internal 10V supply, which will tend to r educe i ts output v oltage when

goes below 10V. Figure 2 shows the supply voltage of the high side gate drivers (V

supply voltage (V

of the DMOS themselves and c ould reach v er y high values. L6235 Out pi ns

DS(ON)

is 8 to 52 V. To prevent working into

must then exceed 7 V. The hy steresis is pro-

ringings. It should be noted, however, that

DS(ON)

supply. This supply is

BOOT

- VS) versus the

BOOT

is adversely

Figure 2. High side gate drivers supply voltage versus supply volta ge.

7.6

BOOT

- V

[V]

7.2

6.8

6.4

8 8.5 9 9.5 10 10.5

VS [V]

Note that VS must be connected to both VSA and VSB because the bootstrap vol tage (at V

pin) is the same

BOOT

for the two H-bridges. The integrated DMOS have a rated Drain-Source breakdown voltage of 60 V. However V

should be kept b elow 52 V , si nce i n nor mal workin g condi tions th e DMOS see a Vds vo ltage that wil l ex ceed

supply. In particular when a high-side DMOS turns off due to a phase change (OUT1 in Figure 3), if one of

the other outputs (OUT2 in Figure 3) is high (during the off-time all active bridges turn their high-side on) the load current starts flowing in the low-side freewheeling diode and the SENSE pin sees a negative spike due to a not negligible parasitic inductance of the PCB path from the pin to GND. This spike is followed by a stable negative voltage due to the drop on R

. The output pin sees a similar behavior, but with a slightly larger

SENSE

voltage due to the forward recovery time of the integrated freewheeling diode and the forward voltage drop across it. Typical duration of this spike is 30 ns. At the same time, the OUT2 pin (in the example of Figure 3)

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AN1625 APPLICATION NOTE

sees a voltage above VS, due to voltage drop across the high-side (integrated) freewheeling diode, as the current reverses direction and flows into the bulk capacitor. It turns out that the highest differential voltage is observed between two OUT pins when a phase change turns a high-side off during an off-time, and this must always be kept below 60 V [2].

Figure 3. Currents and voltages if a phase change turns a high-side off during off-time.

Current starts

PCB Parasit ic Inductance

flowing in the

third half bridge

Bulk

Capacitor

Equivalent

Circuit

SENSE

*I+V

ESR ESL

F(Diode)

PCB Parasitic

Inductance

SENSE

on-time off-time during of f-time

a phase change can occur

Figure 4 shows the voltage waveforms at the OUT pins referring to a possible practical situation, with a peak output current of 2.8 A , V

= 52 V, R

= 0.33 Ω, TJ = 25 °C (approxim ately) and a good P CB layout. Below

SENSE

ground spike amplitude is -2.64 V for one output; the other OUT pin is at about 55 V. In these conditions, total differential voltage reaches almost 60 V, which is the absolute maximum rating for the DMOS. Keeping differential voltage between two Output pins within rated values is a must that can be accomplished with proper selection of Bulk capacitor value and equivalent series resistance (ESR), accordi ng to current peaks and adopting good layout practices to minimize PCB parasitic inductances (see below) [2].

Figure 4. Voltage at the two outputs if a phase change turns a high-side off during off-time.

OUT1

OUT2

SENSE

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AN1625 APPLICATION NOTE

2.3 Choosing the Bulk Capacitor

Since the bulk capacitor, placed between VS and GND pins, is charged and discharged during IC operation, its AC current capability must be greater than the r.m.s. value of the charge/discharge current. This current flows from the capacitor to the IC during the on-time (t power supply during off-time) to the capacitor during the off-time (t into the bulk capacitor depends on peak output current, output current ripple, switching frequency, duty-cycle. It also depends on power supply characteristics. A power supply with poor high frequency performances (or long, inductive connecti ons to the IC) will cause the bulk c apacitor to be recharged sl owly: the higher the current control switching frequency, the higher the current ripple in the capacitor; r.m.s. current in the capacitor, however, does not exceed the r.m.s. output current. Bulk capac itor value ( C) and the ESR determine the amount of voltage ripple on the c apacitor itself and on the IC. Neglecting the output current rippl e and assuming tha t during the on-time the capacitor is not recharged by the power supply, the voltage at the end of the on-time is

VSI

) and from the IC (during some phase changes; from the

). The r.m.s. value of the current flowing

OFF



ESR

⋅–

OUT



-------- -+

where I

is the output current. Usually (if C>100 µF) the capacitance role is much less than the ESR, then

OUT

supply voltage ripple can be estimated as

ESR⋅

OUT

For Example, if a max imum ri pple of 500 mV i s all owed and I

0.5V

------------

ESR

Note that additional ripple is due to parasitic inductances on V

= 2 A, the capac itor E SR s hould be lower than

OUT

250mΩ=<

PCB tracks (see Voltage Ratings and Operating

Range section). Actually, current sunk by V

and VSB pins of the device is subject to higher peaks due to reverse recovery

charge of internal freewheeling diodes. Duration of these peaks is, tough, very short (100÷200 ns) and can be filtered using a small value (100÷20 0 nF), good quality ceramic capaci tor, connected as close as possible to the V

, VSB and GND pins of the IC. Bulk capacitor will be chosen with maximum operating voltage 25% greater

than the maximum supply voltage, considering als o power supply toler ances . For exa mple, w ith a 48 V nomi nal power supply, with 5% tolerance, maximum voltage is 50.4 V, then operating voltage for the capacitor should be at least 63 V.

2.4 Layout Considerations

Working with devices that combine high power switches and control logic in the same IC careful attention has to be paid to the PCB lay out. In extreme cases, Power DMOS commutation can i nduce nois es that could c ause improper operation in the logic section of the device. Noise can be radiated by high dv/dt nodes or high di/dt paths, or conducted through G ND or Supply connectio ns. Logic connec tions, es pecial ly hi gh-i mpedance nodes (actually all logic inputs, see further), must be kept far from switching nodes and paths. With the L6235, in particular, external components for the charge pump circuitry should be connected together through short paths, since these components are subject to voltage and current switching at relatively high frequency (600 kHz). Primary mean in minimizing conducted noise is working on a good GND layout (see Figure 5).

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AN1625 APPLICATION NOTE

Figure 5. Typ ic a l App li ca ti on and Layout suggest io ns.

Phase

Brushless

DC Motor

SA VSB

SENSE

VS = 8 ÷ 52 V

GND GND

Logic Supply

3.3 ÷ 5 V

µC

Custom Logic

= 0 ÷1V

ref

BOOT

L6235

PUL SE

OUT

OUT1 OUT

H1 H2 H3 FWD/REV BRAKE TACHO DIAG

ref RCOFF

High cur rent GND tracks (i .e. the trac ks con nected to the sens ing r esistor) m ust be c onnecte d dire ctly to the ne gative terminal of the bulk capacitor. A good quality, high-frequency bypass capacitor is also required (typically a 100 nF÷200 nF ceramic would suffice), since electrolytic capacitors show a poor high frequency performance. Both bulk electrolytic and high frequency bypass capacitors have to be connected with short tracks to V

, V

and GND . On the L62 35 GND pins are th e Logic GND, sinc e only the q uiescent curren t flow s throu gh them . Logic GND and Power GND should be connected together in a single point, the bulk capacitor, to keep noise in the Power GND from affecting Logic GND. Specific care should be paid layouting the path from the SENSE pins through the sen sing r esistor to the negative termin al of the bulk ca pacitor (P ower Ground) . These tracks mus t be as short as possible in order to minimize parasitic inductances that can cause dangerous voltage spikes on SENSE and OUT pins (see the Voltage Ratings and Operating Range section); for the same reason the capacitors on V section for inf ormat ion on selec ting the sens e resis tors. Tr aces th at connect to V

, VSB and GND pi ns sho uld be ver y close to the GN D and sup ply pin s. Refe r to the Sens ing R esisto rs

, VSB, SENSEA, SENSEB, and

the three OUT pins must be d esi gne d w ith a dequ ate w id th, s inc e hig h cu rr ents ar e fl owing through the se tra ces , and layer ch anges sh ould be avoide d. Should a lay er ch ange prove necess ary, m ultiple an d large via holes have to be used. A wide GND copper area can be used to improve power dissipation for the device.

Figure 6 shows two typical situations that must be avoided. An important consideration about the location of the bulk capacitor is the ability to absorb the inductive energy from the load, without allowing the supply voltage to exceed the maximum rating. The diode shown in Figure 6 prevents the recirculation current from reaching the capacitors and will res ult in a high voltage on the IC pins th at can destroy the device. H aving a switch or a power connection that can dis connect the c apacitors from the IC, w hile there is stil l c ur rent in the motor, will a lso result in a high voltage transient since there is no capacitance to absorb the recirculation current.

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AN1625 APPLICATION NOTE

Figure 6. Two situations that must be avoided.

DON’T put a diode here!

Recircul ating c urrent c annot flow into the

bulk capac itor and caus es a high voltage

spike that can dest roy the IC.

VS = 8 ÷ 52 V

L6235

GND

SA VSB

SENSE

GND

DON’T conne ct the Logic GND here

Voltage dro p due t o c urrent in s ens e

path can disturb logic GND.

2.5 Sensing Resistor

Motor winding current flows through the sensing resistor, causing a voltage drop that is used, by the logic, to control the peak value of the load current. Two issues must be taken into account when choosing the R value:

■ The sensing resistor dissipates energy and provides dangerous negative voltages on the SENSE pins

during the current recirculation. For this reason the resistance of this component should be kept low.

■ The voltage drop across R

parator. The lower is the R

SENSE SENSE

to the input offset of the current sense comparator: too small values of R

A good compromise is calculating the sensi ng resistor value so that the voltage drop , corresponding to the peak current in the load (Ipeak), is about 0.5 V: R

It should be clear that sensing resistor must absolutely be non-inductive type in order to avoid dangerous negative spikes on SENSE pins. Wire wounded resistors cannot be used here, while Metallic film resistors are recommended for their high peak current capability and low inductance. For the same reason the connections between the SENSE pins, C6, C7, V (see also the Layout Considerations section).

SENSE

is compared to the reference voltage (on Vref pin) by the internal com-

value, the higher is the peak current error due to noise on Vref pin and

must be avoided.

SENSE

= 0.5 V / Ipeak.

SENSE

, VSB and GND pins (see Figure 5) must be taken as short as possible

The average power dissipated by the sensing resistor is:

PRI

D is the duty-cycle of the PWM current control, I

rms

SENSE

is the r.m.s. value of the load current.

rms

;

D⋅⋅≈

Nevertheless, sensing resistor power rating should be chosen taking into account the peak value of the dissipated power:

where I

is the peak value of the load current.

⋅≈

SENSE

Using multiple resistors in parallel will help obtaining the required power rating with standard resistors, and re-

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AN1625 APPLICATION NOTE

duce the inductance. R

The following table shows R

tolerance reflects on the peak current error: 1% resistors should be preferred.

SENSE

recommended values (to have 0.5V drop on it) and power ratings for typical

SENSE

examples of current peak values.

0.5 1 0.25 1 0.5 0.5 2 X 1Ω, 0.25W paralleled

1.5 0.33 0.75 3 X 1Ω, 0.25W paralleled 2 0.25 1 4 X 1Ω, 0.25W paralleled

SENSE

Value

[Ω]

SENSE

Power Rating

[W]

Alternatives

2.6 Charge pump external components

An internal oscillator, with its output at CP pin, switches from GND to 10 V with a typical frequency of 600 kHz (see Figure 7).

Figure 7. Charge Pump .

VS + 10 V - VD1 - V

BO OT

VS + 10 V - V

SA VSB

- V

f = 600 kHz

10 V

DS(O N)

DS(ON)

= 70Ω

Charge Pum p

Oscillator

10 V

5 V

10 V

f = kHz

600

To High-Side Gate Drivers

L6235

When the oscillator output is at ground, C5 is charged by VS through D2. When it rises to 10 V, D2 is reverse biased and the charge flows from C5 to C8 through D1, so the V imum voltage of V

With a differential voltage between V current drawn by the V

+ 10 V - VD1 - VD2, which supplies the high-side gate drivers.

pin is 1.85mA.

BOOT

and V

of about 9V and the bridges switching at 50 kHz, the typical

BOOT

Resistor R4 is added to r educe the maximum current in the exter nal components and to reduce the slew rate of the rising and falling edges of the voltage at the CP pin, in order to minimize interferences with the rest of the circuit. For the same reason car e must be taken in realiz ing the PC B layout of R 4, C5, D1, D2 connections ( see also the Layout Considerations section). Recommended values for the charge pump circuitry are:

8/39

pin, after a few cycles, reaches the max-

BOOT

D1, D2 : 1N4148

AN1625 APPLICATION NOTE

R4 : 100

Ω (1/8 W) C5 : 10 nF 100V ceramic C8 : 220 nF 35V ceramic

Due to the high charge pump frequency, fast diodes are required. Connecting the cold side of the bulk capacitor (C8) to V = 100

instea d of GND the ave rage cu rre nt in the ex ter nal di odes during operati on is le ss tha n 10 mA (with R4

Ω

); at star t up (w h en VS is provided t o the IC) is less than 200 mA while the reverse voltage is about 10 V in all co nd iti on s. 1N 41 48 dio de s withstand about 200 mA DC (1 A pea k ), and the max i mu m reverse vo lta ge is 75 V, so they should fit for the majority of applications.

2.7 Sharing the Charge Pump Circuitry

If more than one device is used in the applic ation, it's possible to use the char ge pump from one L6235 to suppl y the V Figure 8. A 100 nF capacitor (C8) should be connected to the V

Supply voltage pins (V

pins of several ICs. The unused CP pins on the slaved devices are left unconnected, as shown in

BOOT

) of the devices sharing the charge pump must be connected together.

pin of each device.

BOOT

The higher the number of devices sharing the same charge pump, the lower will be the differential volt age available for gate drive (V

- VS), causing a higher R

BOOT

for the high side DMOS, so higher dissipating po wer.

DS(ON)

In this case it's recommended to omit the resistor on the CP pin, obtaining a higher current capability of the charge pump circuitry.

Better performance can also be obtained using a 33 nF capacitor for C5 and using schottky diodes (for example BAT47).

Sharing the same charge pump ci rcuitr y fo r mor e than 3÷4 devi ces is not recommended, sinc e it wil l reduce the V

voltage increasing the high-side MOS on-resistance and thus power dissipation.

BOOT

Figure 8. Sharing the charge pum p circuitry.

To other Devices

BO OT

To High-Side Gate Drivers

L6235

C18 = 100 nF

D2 = BAT47

SA VSB

C8 = 100nF

BOOT

To High-Side Gate Drivers

D1 = BAT47

C5 = 33nF

L6235

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AN1625 APPLICATION NOTE

2.8 Reference Voltage for PWM Current Control

The device has an analog input, Vref, connected to the internal sense comparator, to control the peak value of the motor current through the integrated PWM circuitry. A fixed reference voltage can be easily obtained through a resistive divider from an available 5 V voltage rail (maybe the one supplying the µC or the rest of the application) and GND.

A very simple way to obtain a variable voltage without using a DAC is to low-pass filter a PWM output of a µC (see Figure 9).

Figure 9. Obt ain in g a va ri abl e v ol ta ge t hro ugh a PWM ou t put of a µC .

PWM Output

of a µC

DIV

GND

ref

Assuming that the PWM output swings from 0 to 5V, the resulting average voltage will be

5V DµCR

⋅⋅

-----------------------------------------=

RLPR

where D

ref

is the duty-cycle of the PWM output of the µC.

µC

Assuming that the µC output impedance is lower than 1k

DIV

Ω,

with RLP = 56kΩ, R

= 15kΩ, CLP = 10nF and a

DIV

µC PWM switching fr om 0 to 5V at 100kHz , the l ow pass fi lter tim e consta nt is about 0.12 ms an d the remai ning ripple on the V

voltage will be about 20 mV. Using higher values for RLP, R

ref

and CLP will reduce the ripple,

DIV

but the reference voltage will tak e more time to vary after changing the duty -cycle of the µC PWM, an d too high values of R

As sensing resistor value is typically kept small, a small noise on V

will also incr ease the impedance of the V

net at low frequencies, causi ng a poor noise immuni ty.

ref

input pins might cause a considerable error

ref

in the output current. It's then recommended to decouple this pin with a ceramic capacitor of some tens of nF, placed very close to Vref and GND pins. Note that Vref pin cannot be left unconnected, while, if connected to GND, zero current is not guaranteed due to voltage offset in the sense comparator. The best way to cut down (IC) power consumpti on and clear the l oad current is pul ling down the EN pin. With very small refer ence voltage, PWM integrated circuitry can loose control of the current due to the minimum allowed duration of t

(see the

Programmable off-time Monostable section).

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AN1625 APPLICATION NOTE

2.9 Input Logi c pin s

H1, H2, H3, FWD/REV, BRAKE, ENABLE, are CMOS/TTL compatible logic input pins. The input comparator has been realized with hysteresis to ensur e the required noise immunity . Typical val ues for turn-on and turn-off thresholds are V electro-static discharge), and can be directly connected to the logic outputs of a µC; a series resistor is generally not recommended, as it could hel p induct ed noise to dist urb the input s. All logic pi ns enfor ce a specifi c behavior and cannot be left unconnected. If connected to the DIAG pin, EN pin must be driven through a series resi stor of 2.2 k imum (for 5 V logic), to allow the voltage at the pin to be pulled below the turn-off threshold (see below).

Figure 10. Logic input pins.

= 1.8 V and V

TH(ON)

TH(OFF)

= 1.3 V.

H1, H2 H3 FWD/REV, BRAKE ENABLE

Pins are ESD protected (see Figure 10) (2kV human-body

5 V

ESD

Protection

Ω

min-

2.10DIAG pin

DIAG pin is an open-drain output pul led to GND in case of ov ercurrent or over temperatur e conditions. Connecting this pin to EN will allow the internal open drain to disable all the power DMOS of the L6235, provided that the EN pin is driven through a resistor (see Input Logic pins).

A capacitor (C1 in Figure 5 and Figure 11) conne cted between EN and DIAG pins and GND is als o recommended, to reduce the r.m.s. value of the output current when overcurrent conditions persist (see Over Current Protection section).

Figure 11. DIAG pin.

µC or Logic

Output

DIAG

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AN1625 APPLICATION NOTE

2.11Programma ble off-time Monostable

The L6235 includes a constant off time PWM Current Controller. The current control circuit senses the bridge current by sensing the voltage drop across an external sense resistor connected between the source of the three lower power MOS transistors and ground, as shown in Figure 12. As the current in the motor increases the voltage across the sense r esistor incr eases pr oportionall y. When the voltage drop across the s ense r es istor becomes greater than the voltage at the reference input pin VREF the sense comparator triggers the monostable switching the bridge off. The power MO S re main off for the time set by the monos table and the motor current recirculates ar ound the upper half of the bridge in S low Decay Mode as described in the next sec tion. When the monostable times out, the bridge will again turn on. Since the internal dead time, used to prevent cross conduction in the bridge, delays the turn on of the power MOS, the effective Off Time t the monostable time plus the dead time.

Figure 13 shows the typical operating waveforms of the output current, the voltage drop across the sensing resistor, the pin RC vol tage and the status of the bridge. More d etails regarding the S ynchronous Rectificati on and the output stage configuration are included in the next section.

Immediately after the Power MOS turn on, a high peak current flows through the sense resistor due to the reverse recovery of the freewheeling diodes. The L6235 provides a 1µs Blanking Time t

BLANK

comparator output so that the current spike cannot prematurely retrigger the monostable.

is the sum of

OFF

that inhibits the

Figure 12. PWM Current Controller Simplified Schematic

TO GATE

LOGIC

5mA

(0) (1)

RCOFF

OFF

2.5V

BLANKING TIME

MONOST ABLE

1µs

MONOST ABLE

SET

COMP ARATOR

BLANKER

SENSE

FROM THE

LOW-SIDE

GATE DRIVERS

DRIVERS

DEAD TIME

VREF

SENSE

DRIVERS

DEAD TIME

SENSE

DRIVERS

DEAD TIME

D02IN1380

OUT OUT OUT

2 3 1

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