ST AN1625 APPLICATION NOTE

AN1625

APPLICATION NOTE

L6235 THREE PHASE BRUSHLESS DC MOTOR DRIVER

by Vincenzo Marano

Modern motion control applications need more flexibility that can be addressed only with specialized ICs products. The L6235 is a fully integrated motor driver IC specifically developed to drive a wide range of BLDC motors with Hall effect sensors. This IC is a one-chip cost effective solution that includes several unique circuit design features. These features, including a universal decoding logic that allows the device to be used with most common Hall effect spacing, will be described. The principal aim of this development project was to produce an easy to use, fully protected power IC. In addition several key functions as protection circuit and high speed PWM current control allow to drastically reduce the external components count to meet requirements for many different applications.

1 INTRODUCTION

For small-motor applications many appliance designers favor modern three phase brushless DC motors because of the high efficiency (as great as 95%) and small size for a given delivered power. Designers have to handle control logic, torque and speed control, power-delivery issues and ensure safe operation in every load condition. The L6235 is a highly integrated, mixed-signal power IC that allows to easily design a complete motor control system for BLDC motor. Figure 1 shows the L6235 block diagram. The IC integrates six Power DMOS, a centralized logic circuit to decode hall effect sensors and a constant tOFF PWM current control technique (Synchronous mode) plus other added features for safe operation and flexibility.

Figure 1. L6235 Block Diagram.

VBOOT	VBOOT					VBOOT		VSA
			THERMAL
VCP	CHARGE
	PUMP		PROTECTION
						OCD1		OUT1
DIAG			OCD1			10V
	OCD		OCD2
			OCD3
			OCD
EN						VBOOT
BRAKE
FWD/REV
						OCD2		OUT2
H3				GATE		10V
		HALL-EFFECT		LOGIC
H2		SENSORS
		DECODING
								SENSEA
			LOGIC
H1						VBOOT		VSB
RCPULSE	TACHO					OCD3
	MONOSTABLE							OUT3
						10V
TACHO
	10V	5V
					PWM			SENSEB
	VOLTAGE
				ONE SHOT	MASKING		+
	REGULATOR
				MONOSTABLE	TIME	SENSE	-	VREF
						COMPARATOR
								RCOFF
								D99IN1095B

October 2003

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Table of Contents

1	INTRODUCTION................................................................................................................................		1
2 DESIGNING AN APPLICATION WITH L6235 ...................................................................................			3
	2.1	Current Ratings ........................................................................................................................	3
	2.2	Voltage Ratings and Operating Range ....................................................................................	3
	2.3	Choosing the Bulk Capacitor....................................................................................................	5
	2.4	Layout Considerations .............................................................................................................	5
	2.5	Sensing Resistor ......................................................................................................................	7
	2.6	Charge pump external components .........................................................................................	8
	2.7	Sharing the Charge Pump Circuitry .........................................................................................	9
	2.8	Reference Voltage for PWM Current Control.........................................................................	10
	2.9	Input Logic pins ......................................................................................................................	11
	2.10	DIAG pin.................................................................................................................................	11
	2.11	Programmable off-time Monostable .......................................................................................	12
	2.11.1 Off-time Selection and minimum on-time ........................................................................		14
	2.11.2 Slow Decay Mode ...........................................................................................................		14
	2.12	Over Current Detection .........................................................................................................	16
	2.13	Power Management ...............................................................................................................	20
	2.13.1 Maximum output current vs. selectable devices..............................................................		20
	2.13.2 Power Dissipation Formulae ...........................................................................................		21
	2.14	The decoding logic ................................................................................................................	24
	2.15 Tacho Output and Speed Loop .............................................................................................		25
	2.15.1 Static performance - Speed Regulation vs. Resistant Torque: .......................................		28
	2.15.2 Dynamic performance: ....................................................................................................		29
	2.15.3 Loop Stability: ..................................................................................................................		30
	2.15.4 Reference voltage ripple: ................................................................................................		30
	2.16	Brake.....................................................................................................................................	31
3	APPLICATION EXAMPLE................................................................................................................		32
4	APPENDIX - EVALUATION BOARDS .............................................................................................		34
	4.1	PractiSPIN..............................................................................................................................	34
	4.2	EVAL6235N ...........................................................................................................................	35
	4.2.1 Important Notes ................................................................................................................		36
5	REFERENCES.................................................................................................................................		39

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2 DESIGNING AN APPLICATION WITH L6235

2.1 Current Ratings

With MOSFET (DMOS) devices, unlike bipolar transistors, current under short circuit conditions is, at first approximation, limited by the RDS(ON) of the DMOS themselves and could reach very high values. L6235 Out pins and the two VSA and VSB pins are rated for a maximum of 2.8 A r.m.s. and 5.6 A peak (typical values). These values are meant to avoid damaging metal structures, including the metallization on the die and bond wires. In practical applications, though, maximum allowable current is less than these values, due to power dissipation limits (see Power Management section).

The device has a built-in Over Current Detection (OCD) that allows protection against short circuits between the outputs and between an output and ground (see Over Current Detection Section).

2.2 Voltage Ratings and Operating Range

The L6235 requires a single supply voltage (VS), for the motor supply. Internal voltage regulators provide the 5V and 10 V required for the internal circuitry. The operating range for VS is 8 to 52 V. To prevent working into undesirable low supply voltage an Under Voltage Lock Out (UVLO) circuit shuts down the device when supply voltage falls below 6 V; to resume normal operating conditions, VS must then exceed 7 V. The hysteresis is provided to avoid false intervention of the UVLO function during fast VS ringings. It should be noted, however, that DMOS's RDS(ON) is a function of the VS supply voltage. Actually, when VS is less than 10V, RDS(ON) is adversely affected, and this is particularly true for the High Side DMOS that are driven from VBOOT supply. This supply is obtained through a charge pump from the internal 10V supply, which will tend to reduce its output voltage when VS goes below 10V. Figure 2 shows the supply voltage of the high side gate drivers (VBOOT - VS) versus the supply voltage (VS).

Figure 2. High side gate drivers supply voltage versus supply voltage.

	8
	7 .6
VBOOT - VS	7 .2
[V]	6 .8
	6 .4
	6
	8	8 .5	9	9 .5	1 0	1 0 .5
				VS [V]

Note that VS must be connected to both VSA and VSB because the bootstrap voltage (at VBOOT pin) is the same for the two H-bridges. The integrated DMOS have a rated Drain-Source breakdown voltage of 60 V. However VS should be kept below 52 V, since in normal working conditions the DMOS see a Vds voltage that will exceed VS supply. In particular when a high-side DMOS turns off due to a phase change (OUT1 in Figure 3), if one of the other outputs (OUT2 in Figure 3) is high (during the off-time all active bridges turn their high-side on) the load current starts flowing in the low-side freewheeling diode and the SENSE pin sees a negative spike due to a not negligible parasitic inductance of the PCB path from the pin to GND. This spike is followed by a stable negative voltage due to the drop on RSENSE. The output pin sees a similar behavior, but with a slightly larger voltage due to the forward recovery time of the integrated freewheeling diode and the forward voltage drop across it. Typical duration of this spike is 30 ns. At the same time, the OUT2 pin (in the example of Figure 3)

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sees a voltage above VS, due to voltage drop across the high-side (integrated) freewheeling diode, as the current reverses direction and flows into the bulk capacitor. It turns out that the highest differential voltage is observed between two OUT pins when a phase change turns a high-side off during an off-time, and this must always be kept below 60 V [2].

Figure 3. Currents and voltages if a phase change turns a high-side off during off-time.

				Current starts
				flowing in the
	Bulk		PCB Parasitic	third half bridge
		ESR	Inductance
	Capacitor
	Equivalent	ESL		VS
	Circuit
	RSENSE*I+ VF(Diode)
				RSENSE*I
				PCB Parasitic
				Inductance
on-time	off-time		during off-time
			a phase change can occur

Figure 4 shows the voltage waveforms at the OUT pins referring to a possible practical situation, with a peak output current of 2.8 A, VS = 52 V, RSENSE = 0.33 Ω, TJ = 25 °C (approximately) and a good PCB layout. Below ground spike amplitude is -2.64 V for one output; the other OUT pin is at about 55 V. In these conditions, total differential voltage reaches almost 60 V, which is the absolute maximum rating for the DMOS. Keeping differential voltage between two Output pins within rated values is a must that can be accomplished with proper selection of Bulk capacitor value and equivalent series resistance (ESR), according to current peaks and adopting good layout practices to minimize PCB parasitic inductances (see below) [2].

Figure 4. Voltage at the two outputs if a phase change turns a high-side off during off-time.

OUT1

OUT2

SENSE

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2.3 Choosing the Bulk Capacitor

Since the bulk capacitor, placed between VS and GND pins, is charged and discharged during IC operation, its AC current capability must be greater than the r.m.s. value of the charge/discharge current. This current flows from the capacitor to the IC during the on-time (tON) and from the IC (during some phase changes; from the power supply during off-time) to the capacitor during the off-time (tOFF). The r.m.s. value of the current flowing into the bulk capacitor depends on peak output current, output current ripple, switching frequency, duty-cycle. It also depends on power supply characteristics. A power supply with poor high frequency performances (or long, inductive connections to the IC) will cause the bulk capacitor to be recharged slowly: the higher the current control switching frequency, the higher the current ripple in the capacitor; r.m.s. current in the capacitor, however, does not exceed the r.m.s. output current. Bulk capacitor value (C) and the ESR determine the amount of voltage ripple on the capacitor itself and on the IC. Neglecting the output current ripple and assuming that during the on-time the capacitor is not recharged by the power supply, the voltage at the end of the on-time is

V		– I		tO N
	S		O UT	× ESR + --------
				C

where IOUT is the output current. Usually (if C>100 µF) the capacitance role is much less than the ESR, then supply voltage ripple can be estimated as

IO UT × ESR

For Example, if a maximum ripple of 500 mV is allowed and IOUT = 2 A, the capacitor ESR should be lower than

ESR ------------ = 250m

< 0.5V W

2 A

Note that additional ripple is due to parasitic inductances on VS PCB tracks (see Voltage Ratings and Operating Range section).

Actually, current sunk by VSA and VSB pins of the device is subject to higher peaks due to reverse recovery charge of internal freewheeling diodes. Duration of these peaks is, tough, very short (100÷200 ns) and can be filtered using a small value (100÷200 nF), good quality ceramic capacitor, connected as close as possible to the VSA, VSB and GND pins of the IC. Bulk capacitor will be chosen with maximum operating voltage 25% greater than the maximum supply voltage, considering also power supply tolerances. For example, with a 48 V nominal power supply, with 5% tolerance, maximum voltage is 50.4 V, then operating voltage for the capacitor should be at least 63 V.

2.4 Layout Considerations

Working with devices that combine high power switches and control logic in the same IC careful attention has to be paid to the PCB layout. In extreme cases, Power DMOS commutation can induce noises that could cause improper operation in the logic section of the device. Noise can be radiated by high dv/dt nodes or high di/dt paths, or conducted through GND or Supply connections. Logic connections, especially high-impedance nodes (actually all logic inputs, see further), must be kept far from switching nodes and paths. With the L6235, in particular, external components for the charge pump circuitry should be connected together through short paths, since these components are subject to voltage and current switching at relatively high frequency (600 kHz). Primary mean in minimizing conducted noise is working on a good GND layout (see Figure 5).

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Figure 5. Typical Application and Layout suggestions.

				3-Phase
				Brushless
				DC Motor
						D1	D2
								C8
						C5
						R4
		OUT1	OUT2 OUT3		VBOOT	CP	VSA	VSB
		H1
+		H2						SENSEA		+
	µ C	H3						SENSEB
Logic Supply		FWD/REV						R5	C6
	or				L6235					C7
3.3 ÷ 5 V	Custom Logic	BRAKE								VS = 8 ÷ 52 V
-		TACHO
		DIAG								-
		EN
		R1
			Vr ef	RCOFF		RCPULSE	GND GND GND GND
		C1
				C3		C4
		C2	R2		R3
	Vref = 0 ÷1V

High current GND tracks (i.e. the tracks connected to the sensing resistor) must be connected directly to the negative terminal of the bulk capacitor. A good quality, high-frequency bypass capacitor is also required (typically a 100 nF÷200 nF ceramic would suffice), since electrolytic capacitors show a poor high frequency performance. Both bulk electrolytic and high frequency bypass capacitors have to be connected with short tracks to VSA, VSB and GND. On the L6235 GND pins are the Logic GND, since only the quiescent current flows through them. Logic GND and Power GND should be connected together in a single point, the bulk capacitor, to keep noise in the Power GND from affecting Logic GND. Specific care should be paid layouting the path from the SENSE pins through the sensing resistor to the negative terminal of the bulk capacitor (Power Ground). These tracks must be as short as possible in order to minimize parasitic inductances that can cause dangerous voltage spikes on SENSE and OUT pins (see the Voltage Ratings and Operating Range section); for the same reason the capacitors on VSA, VSB and GND pins should be very close to the GND and supply pins. Refer to the Sensing Resistors section for information on selecting the sense resistors. Traces that connect to VSA, VSB, SENSEA, SENSEB, and the three OUT pins must be designed with adequate width, since high currents are flowing through these traces, and layer changes should be avoided. Should a layer change prove necessary, multiple and large via holes have to be used. A wide GND copper area can be used to improve power dissipation for the device.

Figure 6 shows two typical situations that must be avoided. An important consideration about the location of the bulk capacitor is the ability to absorb the inductive energy from the load, without allowing the supply voltage to exceed the maximum rating. The diode shown in Figure 6 prevents the recirculation current from reaching the capacitors and will result in a high voltage on the IC pins that can destroy the device. Having a switch or a power connection that can disconnect the capacitors from the IC, while there is still current in the motor, will also result in a high voltage transient since there is no capacitance to absorb the recirculation current.

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Figure 6. Two situations that must be avoided.

VSA	VSB
	SENSEA
L6235	SENSEB
	R5
	C6	C7
GND GND	GND GND

DON’T put a diode here!

Recirculating current cannot flow into the bulk capacitor and causes a high voltage spike that can destroy the IC.

+

VS = 8 ÷ 52 V

-

DON’T connect the Logic GND here

Voltage drop due to current in sense path can disturb logic GND.

2.5 Sensing Resistor

Motor winding current flows through the sensing resistor, causing a voltage drop that is used, by the logic, to control the peak value of the load current. Two issues must be taken into account when choosing the RSENSE value:

■The sensing resistor dissipates energy and provides dangerous negative voltages on the SENSE pins during the current recirculation. For this reason the resistance of this component should be kept low.

■The voltage drop across RSENSE is compared to the reference voltage (on Vref pin) by the internal comparator. The lower is the RSENSE value, the higher is the peak current error due to noise on Vref pin and to the input offset of the current sense comparator: too small values of RSENSE must be avoided.

A good compromise is calculating the sensing resistor value so that the voltage drop, corresponding to the peak current in the load (Ipeak), is about 0.5 V: RSENSE = 0.5 V / Ipeak.

It should be clear that sensing resistor must absolutely be non-inductive type in order to avoid dangerous negative spikes on SENSE pins. Wire wounded resistors cannot be used here, while Metallic film resistors are recommended for their high peak current capability and low inductance. For the same reason the connections between the SENSE pins, C6, C7, VSA, VSB and GND pins (see Figure 5) must be taken as short as possible (see also the Layout Considerations section).

The average power dissipated by the sensing resistor is:

PR » Irms2 × RS ENSE × D ;

D is the duty-cycle of the PWM current control, Irms is the r.m.s. value of the load current.

Nevertheless, sensing resistor power rating should be chosen taking into account the peak value of the dissipated power:

PR » Ipk2 × RS ENSE ,

where Ipk is the peak value of the load current.

Using multiple resistors in parallel will help obtaining the required power rating with standard resistors, and re-

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duce the inductance.

RSENSE tolerance reflects on the peak current error: 1% resistors should be preferred.

The following table shows RSENSE recommended values (to have 0.5V drop on it) and power ratings for typical examples of current peak values.

Ipk	RSENSE Value [Ω]	RSENSE Power Rating [W]	Alternatives
0.5	1	0.25
1	0.5	0.5	2 X 1Ω, 0.25W paralleled
1.5	0.33	0.75	3 X 1Ω, 0.25W paralleled
2	0.25	1	4 X 1Ω, 0.25W paralleled

2.6 Charge pump external components

An internal oscillator, with its output at CP pin, switches from GND to 10 V with a typical frequency of 600 kHz (see Figure 7).

Figure 7. Charge Pump.

VS + 10 V - VD1 - VD2			VS + 10V - VD1
			VS	-VD1	f = 600 kHz
	D1			C8
		D2
	C5
	R4
VBOOT	CP	VSA	VSB
To High-Side		10 V			Charge Pump
Gate Drivers		RDS(ON) = 70 Ω			Oscillator
					10 V
					5 V
10 V
		RDS (ON) = 70 Ω
f = 600 kHz
					L6235

When the oscillator output is at ground, C5 is charged by VS through D2. When it rises to 10 V, D2 is reverse

biased and the charge flows from C5 to C8 through D1, so the VBOOT pin, after a few cycles, reaches the maximum voltage of VS + 10 V - VD1 - VD2, which supplies the high-side gate drivers.

With a differential voltage between VS and VBOOT of about 9V and the bridges switching at 50 kHz, the typical current drawn by the VBOOT pin is 1.85mA.

Resistor R4 is added to reduce the maximum current in the external components and to reduce the slew rate of the rising and falling edges of the voltage at the CP pin, in order to minimize interferences with the rest of the circuit. For the same reason care must be taken in realizing the PCB layout of R4, C5, D1, D2 connections (see also the Layout Considerations section). Recommended values for the charge pump circuitry are:

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D1, D2	: 1N4148
R4	: 100 Ω (1/8 W)
C5	: 10 nF 100V ceramic
C8	: 220 nF 35V ceramic

Due to the high charge pump frequency, fast diodes are required. Connecting the cold side of the bulk capacitor (C8) to VS instead of GND the average current in the external diodes during operation is less than 10 mA (with R4 = 100 Ω); at startup (when VS is provided to the IC) is less than 200 mA while the reverse voltage is about 10 V in all conditions. 1N4148 diodes withstand about 200 mA DC (1 A peak), and the maximum reverse voltage is 75 V, so they should fit for the majority of applications.

2.7 Sharing the Charge Pump Circuitry

If more than one device is used in the application, it's possible to use the charge pump from one L6235 to supply

the VBOOT pins of several ICs. The unused CP pins on the slaved devices are left unconnected, as shown in Figure 8. A 100 nF capacitor (C8) should be connected to the VBOOT pin of each device.

Supply voltage pins (VS) of the devices sharing the charge pump must be connected together.

The higher the number of devices sharing the same charge pump, the lower will be the differential voltage available for gate drive (VBOOT - VS), causing a higher RDS(ON) for the high side DMOS, so higher dissipating power. In this case it's recommended to omit the resistor on the CP pin, obtaining a higher current capability of the charge pump circuitry.

Better performance can also be obtained using a 33 nF capacitor for C5 and using schottky diodes (for example BAT47).

Sharing the same charge pump circuitry for more than 3÷4 devices is not recommended, since it will reduce the VBOOT voltage increasing the high-side MOS on-resistance and thus power dissipation.

Figure 8. Sharing the charge pump circuitry.

To other Devices
					D1 = BAT47	D2 = BAT47
			C18 = 100 nF				C8 =	100nF
					C5 = 33nF
VBOOT	CP	VSA	VSB	VBOOT	CP	VSA	VSB
To High-Side				To High-Side
Gate Drivers				Gate Drivers
			L6235				L6235

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2.8 Reference Voltage for PWM Current Control

The device has an analog input, Vref, connected to the internal sense comparator, to control the peak value of the motor current through the integrated PWM circuitry. A fixed reference voltage can be easily obtained through a resistive divider from an available 5 V voltage rail (maybe the one supplying the µC or the rest of the application) and GND.

A very simple way to obtain a variable voltage without using a DAC is to low-pass filter a PWM output of a µC (see Figure 9).

Figure 9. Obtaining a variable voltage through a PWM output of a µC.

PWM Output	RLP
of a µC

Vref

RDIV

C LP

GND

Assuming that the PWM output swings from 0 to 5V, the resulting average voltage will be

V 5V × Dμ C × RDIV ref = ----------------------------------------

RL P + RDIV

where DµC is the duty-cycle of the PWM output of the µC.

Assuming that the µC output impedance is lower than 1kΩ, with RLP = 56kΩ, RDIV = 15kΩ, CLP = 10nF and a µC PWM switching from 0 to 5V at 100kHz, the low pass filter time constant is about 0.12 ms and the remaining

ripple on the Vref voltage will be about 20 mV. Using higher values for RLP, RDIV and CLP will reduce the ripple, but the reference voltage will take more time to vary after changing the duty-cycle of the µC PWM, and too high values of RLP will also increase the impedance of the Vref net at low frequencies, causing a poor noise immunity.

As sensing resistor value is typically kept small, a small noise on Vref input pins might cause a considerable error in the output current. It's then recommended to decouple this pin with a ceramic capacitor of some tens of nF, placed very close to Vref and GND pins. Note that Vref pin cannot be left unconnected, while, if connected to GND, zero current is not guaranteed due to voltage offset in the sense comparator. The best way to cut down (IC) power consumption and clear the load current is pulling down the EN pin. With very small reference voltage, PWM integrated circuitry can loose control of the current due to the minimum allowed duration of tON (see the Programmable off-time Monostable section).

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2.9 Input Logic pins

H1, H2, H3, FWD/REV, BRAKE, ENABLE, are CMOS/TTL compatible logic input pins. The input comparator has been realized with hysteresis to ensure the required noise immunity. Typical values for turn-on and turn-off thresholds are VTH(ON) = 1.8 V and VTH(OFF) = 1.3 V. Pins are ESD protected (see Figure 10) (2kV human-body electro-static discharge), and can be directly connected to the logic outputs of a µC; a series resistor is generally not recommended, as it could help inducted noise to disturb the inputs. All logic pins enforce a specific behavior and cannot be left unconnected. If connected to the DIAG pin, EN pin must be driven through a series resistor of 2.2 kΩ minimum (for 5 V logic), to allow the voltage at the pin to be pulled below the turn-off threshold (see below).

Figure 10. Logic input pins.

5 V

H1, H2 H3,

FWD/REV, BRAKE,

ENABLE

ESD

Protection

2.10 DIAG pin

DIAG pin is an open-drain output pulled to GND in case of overcurrent or over temperature conditions. Connecting this pin to EN will allow the internal open drain to disable all the power DMOS of the L6235, provided that the EN pin is driven through a resistor (see Input Logic pins).

A capacitor (C1 in Figure 5 and Figure 11) connected between EN and DIAG pins and GND is also recommended, to reduce the r.m.s. value of the output current when overcurrent conditions persist (see Over Current Protection section).

Figure 11. DIAG pin.

µC or Logic
Output	EN
	R1
	DIAG
	C1

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2.11 Programmable off-time Monostable

The L6235 includes a constant off time PWM Current Controller. The current control circuit senses the bridge current by sensing the voltage drop across an external sense resistor connected between the source of the three lower power MOS transistors and ground, as shown in Figure 12. As the current in the motor increases the voltage across the sense resistor increases proportionally. When the voltage drop across the sense resistor becomes greater than the voltage at the reference input pin VREF the sense comparator triggers the monostable switching the bridge off. The power MOS remain off for the time set by the monostable and the motor current recirculates around the upper half of the bridge in Slow Decay Mode as described in the next section. When the monostable times out, the bridge will again turn on. Since the internal dead time, used to prevent cross conduction in the bridge, delays the turn on of the power MOS, the effective Off Time tOFF is the sum of the monostable time plus the dead time.

Figure 13 shows the typical operating waveforms of the output current, the voltage drop across the sensing resistor, the pin RC voltage and the status of the bridge. More details regarding the Synchronous Rectification and the output stage configuration are included in the next section.

Immediately after the Power MOS turn on, a high peak current flows through the sense resistor due to the re-

verse recovery of the freewheeling diodes. The L6235 provides a 1µs Blanking Time tBLANK that inhibits the comparator output so that the current spike cannot prematurely retrigger the monostable.

Figure 12. PWM Current Controller Simplified Schematic

			VSB		VS
					VSA
		BLANKING TIME
	TO GATE	MONOSTABLE
	LOGIC	1 s	FROM THE
			LOW-SIDE
			GATE DRIVERS
5mA		MONOSTABLE
		SET
	S	BLANKER			OUT2
	Q
					OUT3
(0)	(1)
	R				OUT1
			DRIVERS	DRIVERS
	-		+	+
			DEAD TIME	DEAD TIME	DRIVERS
5V	+
					+
	2.5V				DEAD TIME
			+
		SENSE	-
		COMPARATOR
	RCOFF		VREF	SENSEB	SENSEA
COFF	ROFF		RSENSE
					D02IN1380

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