ST AN1624 Application note

AN1624

APPLICATION NOTE

STSR3 SIMPLIFIES IMPLEMENTATION OF

SYNCHRONOUS RECTIFIER IN FLYBACK CONVERTER

F. Librizzi - F. Lentini

1. ABSTRACT

This paper describes the f unctionality and the operation of the STS R3 device used as the second ary synchronous rectifier driver in Flyback topology switched mode power supplies. A Schematic and layout description of a dem o board a ble to replace diode rectifica tion with synchron ous rectification in Fl yback converters is shown below.

Figure 1: Typical Application Schematic

Feedback

Loop

TRANSFORMER

VoutVin

Cout

PWM

option

MosfetN

C1 100nF

OUTGate

PWRGND

STSR3

Vcc

SGLGND

SETANT

INHIBIT

+5V

C2 100nF

+5V

January 2003

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AN1624 - APPLICATION NOTE

2. GENERAL DEVICE DESCRIPTION

The STSR3 Smart Driver IC provide s a high current output to properly drive secon dary Power Mosfets used as Synchronous Rectifiers in high output current, high efficiency Flyback Converters. From a synchronizing clock input, withdrawn on the secondary side of the isolation transformer, the IC generates a driving signal with set dead times with respect to the primary side PWM signal.

The IC operation prevents secondary side shoot-through conditions at turn-on of the primary switch providing anticipation in turn-off of the output. This sm art function is im plemented by a f ast cycle-aftercycle logic control mechanism, based on a hi gh frequency oscillator synchronized by the clock signal. This anticipation is externally set through external components.

A special Inhibit function allows shut-off of the drive output by sensing the Synchronous Rectifier sourcedrain voltage and consequently turning it off when necessary. This feature makes a discontinuous conduction mode possible and avoids reverse conduction of the synchronous rectifier in parallel operation of the converter.

The STSR3 allows implementing Synchronous Rec tification in Discontinuous Mode PWM , Continuous Mode PWM and Quasi Resonant Flyback Converters.

3. PIN CONNECTIONS AND DESCRIPTIONS

The STSR3 is hous ed in a n S O -8 pac kage for SMD as sembly. Device pin out is shown i n f igure 2 and table 1 briefly summarizes the device pin functionality.

Figure 2: Pin Configuration

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Table 1: Pin Description

Pin Nu m ber Pin Name Pin Function

1 N/C Not internally connected 2 Vcc S uppl y input from 4V to 5.5V

3 SETANT Sets the anticipation in turning-off the OUT 4 CK Synchronization for IC’s operation

5 INHIBIT Discontinuous Mode Detector 6 SGLGND Reference for all the control logic signals 7 OU TG ate Output for MOSF E T G ate Dr ive 8 PWRGND Reference for power signals

Figure 3: Block Schematic

Vcc

GAT E

INHIBIT

output buffer

5.7V

N/C

BIAS

UVLO

Peak

detector

High

frequency

oscillator

20mV

SGLGND

DIGITAL

CONTROL

Anticipation

SET

PWRGND

4. SUPPLY VOLTAGE AND UNDER VOLTAGE LOCK-OUT

The supply input range is from 4V to 5.5V. An internal zener diode limits the maximum voltage to 5.8V. A 100nF ceramic capacitor must be connected between Vcc and SGLGND pin in order to assure a stable supply voltage. This capacitor must be placed very close to the device. Another 100nF capacitor must be connected between Vcc and PWRGN D.

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Under Voltage Lock Out feature guarantees proper start-up while it avoids undesirable driving during eventual dropping of the supply voltage. As shown in the Block Diagram, the V cc voltage also supplies also the output driver, consequently the maximum driving voltage is 5.5V, so the use of logic gate threshold mosfets is recommended.

5. SYNCHRONIZATION

An innovative feature of the STSR3 is the capability to operate in the secondary side without any synchronization signal coming from the primary side. The STSR3 synchron ization is obtained directly from the secondary side using the voltage across the Synchron ous mosfet as the information for the switching transitions. The Ck pin is the input for the synchronization signal; the internal threshold is set at

2.6V. As can be seen in figure 3, a Peak Det ect or is present at the in put of the Ck pin . This block is able to distinguish between the p rimary mosfet switching transitions and the e ventual sinusoidal waveform caused by discontinuous mode operation or resonant reset configurations (see figure 4). A wrong synchronization causes wrong driving of the synchronous rectifier.

Figure 4: DCM waveform

Peak

Peak Detector

Detector Input

Input

Peak

Peak Detector

Detector Output

Output

5.1 Continuous Conduction Mode

On Time

Time

Off Time Dead Time

When the Flyback conv erter is working in continuous mode the voltage across the source and d rain of the synchronous mosfet has a square shape. This voltage can be applied to the Ck pin using two different configurations: with a resistor divider (figure 6) or with a diode and pull-up resistor (figure 7). In most cases a spike is present during turn-off of the synchronous mosfet; this spike must be eliminated at the Ck pin in order to avoid false synchronization.

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Using the resistor divider, the spike is eliminated by adding a small capacitor (C1) as shown in figure 6.

Figure 5: CCM waveform and Ck circuit

Turn-Off

Turn-Off Spike

Spike

On Time Off Time

Figure 6: Synchronization with a resistor divider

SYNC RECT

+5V

SGLGND

OUTGate

STSR3

PWRGND

SETANT

INHIBIT

Vcc

+5V

As an exam ple , in a Flybac k co nver ter fo r teleco m app licat ion , the DC inp ut vo ltage has a 1:2 variab ility range (typically 36V-72V). Consequently, the secondary winding voltage also has 1:2 variability. The resistor divider can be calculated in order to have about 2.8V at the Ck pin at 36V input; at 72V input, the

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Ck pin reaches 5.6V. Even if this value is higher than the maxim um voltage on the CK pin it can be accepted, limiting the current flowing into the pin to 10mA. The value of capacitor C1 is depende nt on the amount of sy nchronous mos fet turn-off spike and on the value of R1. In order to reduce the delay introduced by R1 and C1 together , the minimum capacitor value should be used.

In the case of an Adaptor Flyback converter , workin g with 85VAC to 270VAC input, the variabilit y range is 1:3. At the minimum inpu t voltage, 2.8V must be guaranteed at the Ck pin , consequently at maximum input voltage, the voltage at the Ck pin will be 8.9V or higher. This voltage exceeds the absolute maximum ratings of the device. If R1 limits the current flowing into the Ck pin to a value below the maximum Ck current valu e indicated in the datasheet, the device can still working properly; otherwise diode D1 must be added to protect the device.

Figure 7 shows the synchronization circuit with diode and pull-up resistor. In this case there is no problem with the turn-off spike and maximum CK pin voltage. This circuit cannot work properly in Discontinuous Mode due to the ringing present in the voltage drain of the synchronous rectifier.

Figure 7: Synchronization with a diode and pull-up resistor

SYNC RECT

+5V

OUTGate

SGLGND

PWRGND

SETANT

INHIBIT

Vcc

STSR3

The STSR3 can be turned off easily adding a NPN transistor between Ck and SGLGND. This transistor forces the CK pin to GND when the signal OFF is high. In this condition the OUTGate will be in a low state turning off the Synchronous Mosfet.

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Figure 8 shows the turn-off circuit when using a diode and pull-up resistor to synchronize the STSR3, the same configuration of Q1 and R2 can be used with a resistor divider circuit.

Figure 8: Shut down circuit

SYNC RECT

+5V

OFF

OUTGate

PWRGND

Vcc

SETANT

NPN

SGLGND

INHIBIT

STSR3

5.2 Discontinuous Conduction Mode

As shown in figure 4, in d iscontinuous mode operat ion there can be some problems in detecting the primary switching transitions. The internal peak detector is only able to determine the peak value reached by the signal at the Ck pin, neglecting all signals that have a lower value. Referring to figure 4, a minimum voltage difference V

waveform must be assured in order to allow the Peak Detector to work properly.

=400mV between the switching transition wavef orm and the sinusoidal

As mentioned in the previous paragraph, if the input voltage variability range is higher than 1:2, diode D1 must be added to clamp the voltage on the Ck pin. In these conditions, both switching transition waveform and the sinusoidal waveform are clamped, and the peak detector is unable to operate correctly causing false triggering of the STSR3 (see figure 9). In this case, using an external peak detector, like the one shown in the next paragraph, solves the proble m.This allows correct ope ration of t he dev ice bot h i n continuous and discontinuous mode.

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