ST AN1606 Application note

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AN1606
APPLICATION NOTE
November 2002
L4981 PFC Controller
This application features the L4981 P FC contr oller. It is a high per formanc e dev ice operating in average current
mode with many on-ch ip functions. The driv er output stage can deli ver 1.5A, which is very important for this type
of application.
Figure 1. Funct i on a l Di agram
by Ugo Moriconi
A "BRIDGELESS P.F.C. CONFIGURATION"
BASED ON L4981 P.F.C. CONTROLLER.
This technical document describes an innovative topology dedicated to a medium to high power PFC
stage. The originality of this topology is the absence of the bridge that usually is placed between the
EMC filter and the PFC stage. The advantages of this topology can be found in terms of increased ef-
ficiency and improved thermal management.
AN1606 APPLICATION NOTE
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Description of "Bridgeless PFC Configuration" Topology
The conventional boost topology is the most efficient for PFC applications. It uses a dedicated diode bridge to
rectify the AC input voltage to DC, which is then followed by the boost section. See Figure 2.
This approach is good for a low to medium power range. As the power level increases, the diode bridge begins
to become an important part of the application and it is necessary for the designer to deal with the problem of
how to dissipate the heat in limited surface area. The dissipated power is important from an efficiency point of
view.
Figure 2.
The bridgeless configuration topology presented in this paper avoids the need for the rectifier input bridge yet
maintains the classic boost topology.
This is easily done by m aking use of the intrinsic b ody diode c onnected between drain and s ource of P owerMOS
switches.
A simplified schematic of the bridgeless PFC configuration is shown in Figure 3.
Figure 3.
Load
L
A
controller
Rs
V_Rs
Mains
M
D
Inductor
Controller
Mains
Load
L
O
A
D
Inductor
M1
M2
D1
D2
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AN1606 APPLICATION NOTE
The circuit shown from a functional point of view is similar to the common boost converter. In the traditional to-
pology current flows through two of the bridge diodes in series. In the bridgeless PFC configuration, current
flows through only one diode with the PowerMOS providing the return path.
To analyze the circuit operation, it is necessary to separate it into two sections. The first section operates as the
boost stage and the second section operates as the return path for the AC input signal.
Referring to Figure 4, the left side (Figure 4a) shows curr ent flow dur ing the po sitive half cyc le and the right s ide
(Figure 4b) shows current flow during the negative half cycle
Figure 4.
Positive "HALF Cycle."
When the AC input voltage goes positive, the gate of M1 is driven high and c ur rent flows from the input through
the inductor, storing energy. When M1 turns off, energy in the inductor is released as current flows through D1,
through the load and returns through the body diode of M2 back to the input mains. See Figure 4A
During the-off time, the current throw the inductor L (that during this time discharges its energy), flows in to the
boost diode D1 and close the circuit through the load.
Negative "HALF Cycle".
During the negative half cycle circuit operation is mirrored as shown in Figure 4B. M2 turns on, current flows
through the inductor, storing energy. When M2 turns off, energy is released as current flows through D2, through
the load and back to the mains through the body diode of M1.
Note that the two PowerMOSFETs are dr iven synchronously. It doesn't matter whether the sections are per-
forming as an active boost or as a path for the current to return. In either case there is benefit of lower power
dissipation when current flows through the PowerMOSFETs during the return phase.
Current Sensing.
The PFC function requires controlling the current drawn from the mains and shaping it like the input voltage
waveform. To accomplish this it is necessary to sense the current and feed its signal to the control circuit.
In average current conventi onal boost topol ogy, we sense the rectified current rather than the AC input current.
This can be achieved by a simple sensing resisto r in the return of the current to the bridge, as shown in Figure5a.
in
v
L
O
A
D
controller
L
0
v
1
M
2
M
1
D
2
D
Posit ive half cycle
Fig4a
C
H
O
P
P
E
R
return
L
O
A
D
in
v
controller
L
0
v
1
M
2
M
1
D
2
D
Negative half cycle
Fig4b
C
H
O
P
P
E
R
return
AN1606 APPLICATION NOTE
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The L4981A/B current loop is designed to handle this negative signal. This type of resistor current sense can
easily be achieve in medium power applications. For high power PFC circuits it is necessary to use a magnetic
current transformer for improved efficiency as shown in Figure 5b.
In the bridgeless PFC configuration since an input rectifi er bridge is not used, the current is continuously chang-
ing its direction and the complexity of current sensing with a simple resistor can increase. Also in high power
applications, resistor sensing may dissipate too much power. In these cases, current sensing with a current
transformer is the preferred approach.
A current sense transformer core is typically high permeability ferrite (toroidal or a small core set). The primary
of the transformer is a single turn of wire through the core. The secondary typically consists of 50 to 100 turns.
Figure 5. .
This type of sense transformer c annot oper ate at low frequency and for this reason it must be connected w here
the current is switched at high frequency. The magnetic core must be allowed reset.
This is normally accomplished by using a diode. In order to reproduce the inductor's current in boost topology,
two of magnetic sense sections are needed and the simplified schematic is shown in figure 5b.
When the sense transformer solution is applied in the bridgeless topology, the simple sense as in fig5b, is no
longer valid.
v
s
R
s
IL
Iret.
Fig.5a
Standard Sensing
Inductor
Magnetic sensing for high power
Fig.5b
v
s
R
s
Iret.
IL
Inductor
Lm_p
Rs
1:n
Typical sense transformers
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AN1606 APPLICATION NOTE
The circuitry is more complex than in the boost case because here we have two pair of PowerMOS (M1, M2)
and diodes (D1, D2) alternating.
It is necessary to sense the chopping current of the (PowerMOS + diode) section and to sum the signals to be
applied to Rs.
The sensing of the diode's current can be simply done by placing a magnetic sensor at the common cathode
(L2 in fig.6.). Only one of the two diodes operates each half input cycle.
Figure 6.
For the PowerMOSFET portion of the circuit, the complexity increases because during the half cycle when one
of the PowerMOSFETs is chopping, the other one has to handle the current flowing back to the mains.
Using the configuration of sensors as shown in Figure 6 it is possible to solve the problem without undue com-
plexity. The unnecessary high frequency portion of the cur rent signal is cancell ed because of the method M1 is
connected to L1A as shown in Figure 6b. The problem due to the change of polarity during each half cycle is
solved by using a center tapped secondary and two rectifiers.
Since the coupling of the two windings must not permit the demagnetization of L1, an auxiliary transistor Q1 is
used that opens the c ircuit during the off-time. For the L4981 c ontroller, the off- time is guaranteed no t to be less
than 5% of the period. Q1 can be a small signal transistor because its switched current is low due to the fact
that the transformer secondary will have a large number of turns.
To realize the current sensing transformer, a high permeability toroidal core (ur=>5000) has been used. The
secondary has 50 turns as a compromise to reduce secondary current yet not require a large number of turns.
L2
v
s
i
in
L
O
A
D
R
s
M
1
M2
controller
Q1
D
1
D
2
L1
Structure of sense transformers
L2 L1
AN1606 APPLICATION NOTE
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Fig 6b
Other control circuits
Input voltage sensing: in the standard boost topology the rectified in put voltage wavefor m is sensed using a re-
sistor that, by one internal circuit, delivers the mirrored signal to one of the multiplier's inputs (Iac-pin4).
For the bridgeless configuration see the circuit shown in fig.7.
L2
L
O
A
D
R
s
v
s
L1a
L1b
controller
M
1
M
2
Q1
D
1
D
2
Da
Db
Dc
Φ
i
in
Inductor
L1a
L1b
L1=L1a+L1b
L2L1 TOT
Φ
v
s
v
s
v
R
s
Φ
Φ
M2_D2 Chopping Phase
L1a
L1b
L1=L1a+L1b
L2
L1
TOT
v
sa
v
sb
v
R
s
ΦΦ
Φ
M1_D1 Chopping Phase
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