ST AN1596 APPLICATION NOTE

AN1596

®

- APPLICATION NOTE

VIPower: HIG H SIDE DRIVERS FO R AUTOMOTIVE

V. Graziano - L. Guarrasi - A. Pavlin

INTRODUCTION

Today’s automotive market requires a continuous increasing of complexity and reliability in the electronic
systems. To achieve this, the concept of the automotive systems is more and more based on micro
controllers architec ture driving integrated monolith ic circuits that include a power stage, control , driving
and protection circuits on the same chip. Vertical Intelligent Power, a STMicroelectronics patented
technology, est ablished over 13 ye ars ago, uses a f abrication pr ocess which allows the integration of
complete dig ital an d/or ana log co ntrol ci rcuits driving a vertic al pow er trans istor on the s ame ch ip. The
VIPower M0 technol ogy used for makin g High Side Driv ers (HSDs) prod uces a monolithic silicon chip,
which combines control and protectio n circuitry with a standard powe r MOSFET structure where the
power stage current flows vertically through the silicon (see figure 1).

Figure 1: M0 chip structure

Drivin g ci r cu itr y

Enhancement and depletion NMOS

Power stage

VDMOS

p - well

n - type epilayer

n + substrate

Power st a ge out put

The evolution of M0 tech nology made the drastic reductio n of die si ze and o f the res istanc e of devic es
possible during conduction as well; each generation has seen a significant (from 40% to over 50%)
decrease in specific on-resistance and this translates into die size reduction, smaller packages, reduced
power dissipatio n and hence cost effecti ve solutions. The third ge neration - the M0- 3 - is in production
while STMicroelectronics is now developing the M0-4 and M0-5 technologies which will allow to achieve
less than 5mΩ R
are power switches that can manage hi gh curr ents an d work up to about 36V su pply voltage. They only
require a sim ple TTL logic input a nd incorporate a diagnostic output to th e micro-controll er. They can
drive an inductiv e load without th e need for a freewhee ling diode. For complete prot ection the devic es
have an over-temperature sensing circuit that will shut the chip down under over-temperature conditions.
Due to the aggre ssive automoti ve environment , High Side D rivers are de signed to w ork from -40 °C to
+150°C. They also have an under-voltage shutdown feature. Each application exerts an external

November 2002 1/24

in a PowerSO-10 package. High Side Drivers, with their integrated extra features

DS(on)

AN1596 - APPLICATION NOTE

influence over the switch. A filament lamp or DC motor, for example, has in-rush currents that any switch
needs to h andle. So lenoids and moto rs h ave an ind uctive e ffect a nd must lose th e resi dual magne tism
when the curr ent is turned of f. Extern al fault condition s can also str ess the dri vers and their associat ed
circuitry. Th e M0-3 High Side Dr iver can be di vi de d in An alog and di gital . This c lass ific ation is do ne wi th
regard to diagnostic pin, which can be a two level signal pin or an analogue current sense pin. Diagnostic
information outp ut helps the on Board mi crocontroller to qui ckly identify and isolate faults saving repai r
time and often improving safety. High Side Drivers can reduce the size and weight of switch modules, and
where multiplexed systems are used, they dramatically reduce the size of the wiring harness.

Figur e 2: Generic HSD Internal Block Diagram

Vcc

Vcc

clamp

OVERVOLTAGE

UNDERVOLTAGE

Power

CLAMP

GND

GND

Input

Status or

Current

sense

Isense =

OUT/K

I

Logic

DRIVER

OVERTEMPERATURE

Current

LIMITER

OPENLOAD

ON STATE

OPENLOAD

OFF STATE

&

Vcc/OUT

SHORTED

OUT

STMicroelectronics HSDs are designed to provide the user with simple, self protected, remotely controlled
power switches. They have the general structure as shown in figure 2.

THE GENERAL FEATURES OF HIGH SIDE DRIVERS
Input

The 5V TTL input to the se High Side Drivers i s protected agai nst elec trostati c discharg e (V
control pins an d 5kV for P ower pins ) . Gener al rules conc e rning T TL log ic sho ul d be app lie d to the inp ut.
The input volta ge is clam ped inter nal ly at V
a higher input voltage using an external resistor calculated to give a current not exceeding IIN=10mA (see

=6.8V as typical value. It is possible to drive the input with

ICL

ESD

=4kV for

datasheets absolute maximum ratings section).

Internal power Supply

To accommoda te the wide supply voltage ra nge experienced by the l ogic and control functi ons, these
devices have an internal power supply. Some parts of the chip are only active when the input is high, the
charge pum p for e xample. Therefo re it i s poss ible to conserve p ower when the device i s idl e. The new
M0-3 generat ion High Side Drivers supply cur rent in the ON state is 5mA/channel. Th e internal power
consumption for the basic functions of the chip under any circumstances - even when the input is 0V - is
very low. The supply quiescent current IS, guaranteed at junction temperature of 25°C, a ba ttery volta ge

2/24

AN1596 - APPLICATION NOTE

of 13V and the output pin grounded, is limited to a typical value of 10µA for a one channel HSD. In figure
3 a plot of typical IS values versus Tj is shown for single channel and double channel monolithic HSDs.

Figur e 3: Stand-by current for single and double channel single chip HSDs Vs. junction temperature

Is(uA)

25

20

15

10

5

Double channel Single Channel

0

-50 0 50 100 150

Tcase(ºC)

Thermal considerations
In order to choose the s uitable HSD for a given load s ome impo rtant po ints mu st be hi ghlight ed. In t he

worst-case operation (Tj=150ºC), for a single channel HSD and in steady state conditions, the Joule effect
power developed by the device equals the Power dissipated according to the following equation:

TT

2

)(

IVIR

SCCOUTonDS

Assuming that the second term can be neglected, for a given load current I
sink and a given ambient temperature (fixed at 85°C in automotive environment) the result is:

()

150

CR

)(

onDS

This is the maximum value of R
function of the junction temperature and in the datasheet its value is given at 25°C and this is

which can be chosen. The steady state on-resistance of HSDs is a

DS(on)

=°

2

approximately doubled at 150°C. In some cases it may be convenient to use an HSD with a bigger R
in the same package. To still comply with the above equation we must reduce R
heatsink. The trend from through-hole packages to low-cost SMD applications has led to think of the PCB

−

=⋅+⋅

−

RI

⋅

ambJ

R

ambthj

−

a given package and heat

OUT

TT

ambJ

ambthjOUT

−

and have a better

thi-amb

DS(on)

as a heatsink itself. In earlier packages (like PENTAWATT) a solid heatsink was either screwed or
clamped to the po we r packa ge and it was easy to calcul a te the th erm al resis tan ce from the ge ometr y of
the heatsink. In SMDs the heat path must be evaluated: chip (junction) - leadframe - case or pin - footprint

- PCB materials - PCB volume - surroundings. To evaluate static thermal properties of an SMD an
associated stati c equ iva lent ci rcuit (s ee figur e 4) can be c onsider ed. The power dissipation of the chip is
symbolized by a c urrent source whi lst the ambient temperature is represented by a vol tage source. By
estimating the PCB heatsink area in a real applica tion, the user can easily determin e R

thj-amb

in still air,

3/24

AN1596 - APPLICATION NOTE

which is the worst case; in re al applications the values for the heat resistance are much lower. T he
following equation applies:

TTR−

ambj

P

V

Figur e 4: Static thermal equivalent circuit

=

−

ambthj

Rthj-amb

Die

d

P

In the above equation, the power loss PV and the ambient temperature T
a temperatur e chamber. The chip temperatur e Tj can be derived dur ing the operation, meas uring the
device’s R

Figur e 5: PowerSO-10 recommended layout for high power dissipation capability

DS(on)

j

T

= (VCC - V

OUT

Die Bond

R

thj-case

)/I

OUT

Lead-frame

Solder

R

Tcase

.

Heatsink

thcase-amb

amb

Tamb

can be easily determined in

Rthjamb = 50 C/W Rthjamb = 35 C/W
recomended pad layout pad layout + 6 cm2 on board heat sink

4/24

R

thjamb

= 20 C/W R

thjamb

= 15 C/W

pad layout + ground layers pad layout + ground layers + 16 via holes

AN1596 - APPLICATION NOTE

Having the characteristic R
different PCB layout for PowerSO-10 package. The thermal resistance R

50°C/W to 15°C/W by holes linking different copper layers.

versus Tj, the relevant chip temperature can be derived. Figure 5 shows

DS(on)

can be reduced fro m

thj-amb

In the VIPower H SDs dat asheet s there are two section s concer ning th e thermal ma nagement. The fi rst
one shows the thermal calculation in order to find out the junction temperature in static conditions together
with a plot of thermal resistance junction to ambient versus PCB heatsink area. The second one shows a
plot of thermal impedance junction ambient in single pulse and the thermal model is shown with relevant
thermal resi stances and cap acitors values ( easy simu lations ca n be per formed bo th in st atic cond itions
and during transi en ts as , for exam ple, s wit ching on a l oad wi th high i n rush curren ts or PWM operation).
In figure 6 an example of a double channel HSD thermal model is shown.

Figur e 6: VND830 (SO16L package) thermal model

Area/island (cm2) Footprint 6

R1 (°C/W) 0.15
R2 (°C/W) 0.8
R3 (°C/W) 2.2
R4 (°C/W) 12
R5 (°C/W) 15
R6 (°C/W) 37 22
C1 (W.s/° C) 0.0006
C2 (W.s/°C) 2.10E-03
C3 (W.s/°C) 1.50E-02
C4 (W.s/°C) 0.14
C5 (W.s/°C) 1
C6 (W.s/°C) 3 5

Tj_1

Pd1

Tj_2

C1

C1 C2

R1

Pd2

C3 C4

R3R1 R6R5R2

R2

R4

T_amb

C5 C6C2

THE CONTROL AND PROTECTION CIRCUIT
Protection against low energy spikes and load dump

The voltage tra ns ients ar e v ery d ange rous hazards to the au tomo tive el ectro ni cs. The transients tend to
be either low energy- high voltage spikes or high energy-high voltage, up to 125V levels. The low energy
spikes are ge nera ted by fas t tu rnof f of hi gh- curre nt i nductive loads, such as air -cond it ioning c om presso r
clutches. This effect, combined with inductive behavior of wires, causes an overshoot voltag e on the
devices VCC pin. M0-3 Hi gh Sid e Driver s have an intern al protec tion desi gned to clamp the low ener gy
spikes to 41V (VCC clamp bloc k in figure1). In thi s situation the e nergy can flow thro ugh the internal
MOSFET T2 that is turned on through an internal clamp circuit (see figure 7).

M0-3 High Side Drivers are designed to su ccessfully pass the 1, 2, 3a, 3b and 4 ISO-7637 standar d
pulses t est ( see table 1 c arr ied i n HS Ds datasheets as wel l) - si mula ti ng the l ow e nerg y v olta ge spikes.
These values must be added to the voltage battery (for cars about 13.5V) to obtain the actual voltage. The
N.5 ISO7637 pulse simulates the alternator load dump in the case of a Generator with an internal
impedance of 2Ω and d i ffere nt value s of m agnetic field of the exc ita ti on circu i t (see figur e 8 for the level
IV pulse); this occurs when the battery is disconnected whilst being charged by the alternator. The voltage
spike can reach duration of approximately ½ second and it is of high-energy nature because of the
alternator' s low source imp edance. Where a cen tralized clam p circuit is not pro vided or ISO7637 rat ed
devices are not used, an external zener Dld diode is necessary to clamp the transient voltage battery (see
figure 7). This is done bec ause an inter nal prot ection ag ainst load du mp would requi re a large r die size
and - therefore - higher cost than putting on a module level protection.

5/24

AN1596 - APPLICATION NOTE

Figure7: VCC clamp circuit against low energy spikes

Protection circuit

T1

Power

T2

MOSFET

Vcc

Dld

Ground

Table 1: Electrical transient requirements on VCC PIN

ISO T/R 7637/1

Test Pulse

I II III IV Delays and

1 -25 V -50 V -75 V -100 V 2 ms 10 Ω

2 +25 V +50 V +75 V +100 V 0.2 ms 10 Ω
3a -25 V -50 V -100 V -150 V 0.1 µs 50 Ω
3b +25 V +50 V +75 V +100 V 0.1 µs 50 Ω

4 -4 V -5 V -6 V -7 V 100 ms, 0.01

5 +26.5 V +46.5 V +66.5 V +86.5 V 400 ms, 2

Figur e 8: N.5 ISO 7637 pulse (level IV)

Tr < 10ms

Tr

R

i = 2

Ω

T

Output

TEST LEVELS

T=400ms

Impedance

Ω

Ω

6/24

90%

100V

10%

13.5V

AN1596 - APPLICATION NOTE

max)(

600

onS

GND

I

mV

R ≤

GND

CC

GND

I

V

R

−

≥

GNDCCD

RVP2−=

Under and over voltage lockout

Under and overvoltage protections occur when the supply voltage drops or raises to minimum and
maximum le vels specified in the datashee t as V
simply turns of f, just because it wo uld not work properly. Th e undervoltage condi tion may occur when
turning on a car headlamp for example, which is a near short circuit. The inductive effect of wires (typically

1µH/m) generates an opposing voltage across the wire and the apparent supply voltage drops. The
current increase rate for an HSD is about 1A/ms for a short-circuited load and using a 5m length wire, the
induced voltage will not be large enough to reduce the supply voltage below 5.5V and - therefore - the
HSD switches on. The overvoltage contr ol circuit acts as a protecti on for the load against overvol tages
(VOV=36V and above that value the device switches off).

Reverse battery protection

Most auto manu facturers specify t hat any el ectronic d evice must be able to withstand a reverse batte ry
connection. T he exact magnitu de of the reverse voltage requir ement varies per m anufacturer, but t he
worst case seems to be -24V for 10 min. The maximum allowed value of the ground current during reverse
battery is -I
problem.

Solution 1: Resistor in the ground line (R
is an indication on how to dimension the R

and it is specified in the device's datasheet. There are two possible solutions to this

GND

only). This can be used with any kind of load. The following

GND

GND

and VOV. Under V

USD

resistor.

(1)

=5.5 V val ue the Po werMO S

USD

−

Power dissipation in R

during reverse battery situation is the following:

GND

(2)

()

This resistor can be shar ed amongst several different HSDs. In this case in the formula (1) I
becomes the sum of the maximum on-state currents of the different d evices. When the microprocessor
ground is not common with the device ground then the R
input thresholds and the status output values. This shift will vary depending on how many devices are ON
in the case of several HSDs sh aring the sa me R
with formula (1) and formula (2) may not be fulfilled. To overcome this problem, ST suggests the following

. This can lead to a very little value of R

GND

will produce a shift (I

GND

S(on)max

solution.
Solution 2: a diode (D

DGND if t he de vice drive s an ind uc tive l oa d (se e c hap ter about fast d emag netizati o n). T his sma ll signal

) in the grou nd line. A resistor ( R

GND

=1kΩ) should be inserted in parallel to

GND

diode can be safely shared amongst several different HSDs. Also in this case, the presence of the ground
network will produce a shift (~ 600mV) in the input threshold and in the status output values if the
microcontroller ground is not common to the device ground. This shift will not vary if more than one HSD
share the same diode/resistor network.

Micro-controller I/Os protection

If a ground protection network is u sed and negative transien ts are present on the VCC line, the HSD
control pins will be pulled negative due to parasitic in ternal structures. Th is may cause the microcontr oller
I/O pins to latch up. The value of the resistors (R
voltage shift from the mic ro-controller output to the HSD control pins, and the latch-up limit current of

) to be connected, is a compromis e between the

prot

micro-controller I/Os. The following condition must be fulfilled:

V −−

−

CCpeak

I

R

≤≤

lu

prot

µ

VVV

GNDIHCout

I

IN

Where:

-V

=negative peak voltage

ccpeak

* R

GND

S(on)max

) in the

GND

to comply

7/24

AN1596 - APPLICATION NOTE

outonDSsensedsn

IRIR ⋅=⋅

)(

Ilu=µC's latch up current

V

=output µC's voltage

out µC

VIH=minimum input HSD high level
V

=voltage drop across ground network

GND

IIN=maximum input current

Figure 9 shows the external circuitry used for reverse battery protection and micro-controller protection.

Figur e 9: Ground and µC protection network

+5V

µ

C

R

R

prot

prot

+

5V

V

CC

STATUS

INPUT

HSD

GND

Vcc

OUT

Iout

Vout

GND

D

R GND

Over temperature protection

Over-temper atur e pro tecti on is based on sen s ing the c hip tem pera ture onl y. T he l oca tion of the sensing
element on t he chip in the pow er stag e area, e nsure s that accura te, ve ry fast , tempera ture detect ion is
achieved. Th e range within which over -temperature cutout occurs is T
output goes lo w with a maximum delay of only 20µs. Over-temperat ure protection acts to pr otect the

=150ºC minim um. The status

TSD

device fro m th erma l dama ge a nd l imi ts t he av e rage curr ent wh en sh ort ci r cuits occur i n th e load as well
(see chapter about abnormal load conditions).

Analog current sense

Some of the new HSDs made by using the VIPow er M0-3 technolog y have the curr ent sense featur e
(VN60, VN61, VN92 and VNC6 lines). This allows to develop a voltage signal - that is proportional to the
load current - across an external resistor R
principle of operation is to compare the currents flowing through two paths: the sense path made up of the
series of n-cells PowerMOSFET plus the sense resistor (I
of N-cells MOS plus the connected load (I

. In figure 10 the HSD current sense circuit is shown. The

sense

) and the power path made up of the series

sense

out

).

During the on-state condition the load current creates a voltage drop on the output pin; the OpAmp
compares the voltage drop across the Power MOSFET V
n-se nse MOSFET V

dsn=Rdsn

• I

; in normal operation V

sense

dsN=RDS(on)

dsn

= V

• I

OUT

, therefore:

dsN

to the voltage drop across the

8/24

(3)