ST AN1572 Application note

AN1572

Application note

Power-down time-stamp function in serial real-time clocks (RTCs)

By Doug Sams

Introduction

Power-down time stamp and the Halt bit

Many serial RTC devices from STMicroelectronics include a feature known as power-down time stamp. One register bit, Halt (HT), controls this feature. It is important that users understand three things about the HT bit in order to ensure correct operation of these devices.

1. Upon power-up, prior to writing any of the clock/calendar registers - that is, prior to writing any address in the range 00h to 07h - the user must first clear the HT bit by writing it to 0 (in bit 6 of address 0Ch).

2. Writing to addresses 00h to 07h (upon power-up) without first clearing the HT bit will result in the counters being overwritten, thus corrupting the time/date.

3. Before the HT bit is cleared, reads of the device will return the time of power-down (or, in the case of the M41T82/83/93, the time of the last read or write prior to power-down).

May 2012 Doc ID 10604 Rev 2 1/9

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Address auto-increment and clock data coherency

When reading and writing the time/date, users should always use the address autoincrement feature of the serial interface. This ensures that the data is transferred coherently between the user and the counters. The time/date values read from the counters will all come from the same instant in time (or be written to the counters at the same instant in time). This does not apply to the non clock registers (eg, Flags or Watchdog registers), only to the clock/calendar registers at addresses 00h to 07h.

For example, without using auto-increment, the user must read the time using multiple accesses. On the first access, the seconds are read. Then, on the next transfer, the minutes are read. This continues until all the date and time values have been read as shown in the timing diagram below.

AN1572

Figure 1. I

C timing sequence

1ST ACCESS 2ND ACCESS 7TH ACCESS

BUS

ACTIVITY

READ

SECONDS

READ

MINUTES

READ

HOURS

READ YEAR

time

These transfers, in more detail, are depicted below. To read the seconds, two 2-byte transfers occur in sequence. First, the processor sends the slave address and write bit followed by the register address (01h). Then the slave address is sent again, with the read bit, followed by a read of the seconds register. To read the minutes, this same sequence is repeated, but with a different register address (02h).

Figure 2. Detailed I

BUS

ACTIVITY

C timing sequence

READ

SECONDS

READ

MINUTES

READ

HOURS

READ YEAR

time

SEND SLAVE ADDR

AND WRITE BIT

1 BYTE 1 BYTE 1 BYTE 1 BYTE

SEND SECONDS

In reading the time this way, each byte comes from a different time. The seconds are from time t

, the minutes are from time t2, and so forth. That is, the seconds, minutes, hours,

and so forth, are each read at a different instant in time. They are not coherent; they are not from the same instant in time.

Example: the user begins reading at 23:59:59 (t 59 minutes (at t 00:00:00. So the hours are read (at time t

). Before the hours are read, the RTC increments such that the new time is

) as 00 and not 23. Thus the time, when re-

assembled, will appear to be 00:59:59. It is incorrect by one hour. Thus, it is better to read all the time/date registers during the same transfer so that they come from the same instant in time. That way, the time read will be coherent.

2/9 Doc ID 10604 Rev 2

SEND SLAVE ADDR

AND READ BIT

), and reads 59 as the seconds, then reads

READ SECONDS

AN1572

Buffer/transfer registers

Figure 3. Buffer/transfer registers

USER SIDE

I2C

AT START OF READ OR WRITE, DATA IN COUNTERS IS COPIED TO BUFFER/TRANSFER REGISTERS.

READ / WRITE

BUFFER-TRANSFER

REGISTERS

SECONDS

MINUTES

HOURS

I2C / SPI

INTERFACE

DAY-OF-WEEK

MONTHS

YEARS

CENTURIES

NON-CLOCK

REGISTERS

SQUAREWAVE

CALIBRATION

DATE

RTC COUNTERS

32KHz

OSC

DIVIDE BY 32768

1 Hz

COUNTER

AFTER A WRITE, DATA IS TRANSFERRED FROM BUFFERS TO COUNTERS

COUNTER

ALARM / HALT

WATCHDOG

With a serial RTC, the user accesses the device via its serial interface, either I

HALT BIT SET AT POWER-DOWN

C or SPI. Inside the RTC, the serial interface does not directly access the counters. Instead, a set of buffer/transfer registers sit between the serial interface and the counters. Reads and writes by the user will transfer data into and out of the buffer/transfer registers.

At the start of any I

C (or SPI) transfer, the device copies the counters into the buffer/transfer register. Thus, when the user is reading the time/date, a fresh copy has been placed in the registers. More importantly, because all the counters are simultaneously copied into the registers, the time/date found in them is coherent - the seconds, minutes, hours, etc, all come from the same instant in time.

The buffer/transfer registers ensure coherency and that none of the counter values are incremented while the data is being transferred.

Doc ID 10604 Rev 2 3/9

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