ST AN1560 APPLICATION NOTE
AN1560
APPLICATION NOTE
Design Guide for the uPSD3200 Family
The uPSD3200 f amily is a s eries of 8 051-cl ass microc ontroll ers (MC Us) co nta ining a n 8032 core wi th a
large dual-bank Flash memory, a large SRAM, many peripherals, programmable logic, and JTAG In-System Programming (ISP) (see Figure 1.).
This document sh ows the ste ps to create a design using the DK3200 dev elopment boa rd, the so ftware
development tool PSDsoft Expre ss, and uVi sion 2 805 1 Integ ra ted Deve lop men t Env i ronme nt ( IDE) fr om
Keil Software.
Figure 1. uPSD3234A Block Diagram
Dedicated
Pins (80-
pin pkg
only)
Port 3, UART,
Intr, Timers
8032 Core
2 UARTs
Interrupts
Port 0
DATA
PSD MCU Interface
PSD Page
Register
Decode PLD
Port 1, Bit I/O and I2C,
2nd UART and ADC
Port 1Port 3
4 ADCs
3 Timer/Cntrs
256B SRAM
Port 2
ADDR
128K or 256K
Main Flash
Byte
I2C
Master /
Slave
8032 Internal Bus
32K Byte
Secondary
Flash
PSD Internal Bus
CPLD - 16 MACROCELLSJTAG ISP
Port 4, PWM and DDC Port
PWM
4 Channels
8K Byte
SRAM
DDC
w/ 256 Byte
SRAM
Low Vcc Detect
Reset Supervisor
Watchdog Timer
Dedicated USB
Transceiver
8032 reset
PSD Reset
Pins
USB 1.1
&
Reset Input
Reset Output
VCC, GND,
XTAL
Dedicated
Pins
uPSD3200
Port C,
JTAG, PLD I/O
and GPIO
Port A, PLD
I/O and
GPIO
Port B, PLD
I/O and
GPIO
Port D
GPIO
Dedicated
Pins
AI06868b
1/49February 2005
AN1560
TABLE OF CONTENTS
Figure 1. uPSD3234A Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
uPSD3200 FAMILY OVERVIEW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
DK3200 OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. DK3200 Development Board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
DESIGN EXAMPLE BLOCK DIAGRAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Design Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4. 8032 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
ENTERING DESIGN IN PSDSOFT EXPRESS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Invoke PSDsoft Express and Create Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Select MCU and Initial Placement of Flash in Code Space or Data Space. . . . . . . . . . . . . . . . . 9
Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 5. MCU Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 6. Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Page Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 7. Page Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Chip-Select Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 8. Chip-Select Definition for 8K byte SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 9. Chip-Select Definition for Flash Memory Segments . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 10.External Chip-Select Definition for LCD Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
I/O Logic Equations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 11.Logic Equation for signal LCD_rw. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
User-Defined Node Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Figure 12.4-bit Down-Counter with Automatic Reload of Initial Count . . . . . . . . . . . . . . . . . . . . . . 16
Figure 13.D-register Node. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Edit ABEL HDL Statements for PLD Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 14.Design Flow Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Additional µPSD Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
C Code Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 15.Coded Example Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Fitting Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Merging 8032 Firmware with µPSD Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 16.Firmware Merging Utility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 17.Merging the Example Firmware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
JTAG Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 18.Programming with FlashLINK JTAG Cable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
WATCH IT RUN ON DK3200 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
USING UVISION2 AND ISD51 DEBUGGER FROM KEIL SOFTWARE, INC.. . . . . . . . . . . . . . . . . . . 26
Loading a Keil uVision2 Project. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
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AN1560
Building the Project and Programming the µPSD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Running the Keil ISD51 UART Debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 19.Debug icon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 20.Keil ISD51 Just After it is Successfully Invoked . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
CONCLUSION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
APPENDIX A.PSDSOFT EXPRESS PROJECT SUMMARY FILE, DK3200_1.SUM. . . . . . . . . . . . . . 29
APPENDIX B.PSDSOFT EXPRESS ABEL HDL FILE DK3200_1.ABL . . . . . . . . . . . . . . . . . . . . . . . 32
APPENDIX C.PSDSOFT EXPRESS FITTER REPORT DK3200_1.FRP . . . . . . . . . . . . . . . . . . . . . . . 36
APPENDIX D.DK3200 BOARD LAYOUT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 21.DK3200 Board Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
APPENDIX E.DK3200 SCHEMATICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 22.DK3200 Schematics (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Figure 23.DK3200 Schematics (2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Figure 24.DK3200 Schematics (3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Figure 25.DK3200 Schematics (4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Figure 26.DK3200 Schematics (5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3/49
AN1560
UPSD3200 FAMILY OVERVIEW
The uPSD3200 family is a standard 12-c lock per instruc tion 8032 MCU cap able of being cloc ked up to
40MHz at 5.0V and 24MHz at 3.3V at industrial oper ating temp erature ran ge. Currently ther e are seven
family members that are different comb inations of Flash memor y size, ope rating vo ltage, peri pheral set,
and packaging (see datash eet). The fullest featured pa rt, uPSD3234A-40U6, is used in this Applicati on
Note. The term µP SD i s us ed th ro ugh out the r e mai nde r of th e do cument for brevity. Se e µPSD block diagram in Figure 1..
The µPSD has a unique memory structure that includes two independent Flash memory arrays (main and
secondary) capab le of r ead-w hile-wr ite op eration. This is ideal for In-A ppli cation Pro grammin g (IA P) be cause the 8032 can fetch instructions from one Flash memory array while erasing/writing the other array.
Individual sectors of ea ch Flas h memory ar ray can be m apped to vi rtually an y 8032 addr ess by the De code PLD (DPLD) for total flexi bility. The µPSD al so contains a Page Register whose outputs feed the
inputs of the DPLD. This allows paging (or banking) of Flash memory to break the 8032’s inherent limit of
64K byte addresses. The 8032 may write to the Page Register at runtime.
For more complex designs, the µPSD is capable of placing each of the Flash memory arrays (Main or Secondary) into 8032 code address space, into 8032 data space, or into both code and data space on the fly.
Mapping flexibil ity li ke this supports IAP b ecause either Fl ash mem ory array may b e tempor arily pl aced
into data space while the firmware is updated, then moved back into code space when finished, all under
control of the 8032.
Many peripherals are ava ilable in this µ PS D, incl uding: USB v1.1 (lo w speed), two UART ch annels , four
PWM channels, one I
and projectors), a watch dog timer, low-V
GPIO.
All of the peripherals on Ports 1, 3, and 4 are controlled using 8032 Special Function Registers (SFRs). I/
O Signals on ports A, B, C , and D are controlled one of two ways: One, by a block of xdata memory
mapped control regis ters, whose b ase add ress (
by the programmable logic.
The JTAG ISP channel on Por t C is ideal for rapid code iterations during fir mware develo pment and for
Just-In-Time inventory management during manufacturing. JTAG ISP eliminates the need for sockets and
pre-programmed devices, and requi r es no partic i pati on of the 8032.
2
C channel, four 8-bit ADC channels, DDC (Data Display Channel for LCD monitors
detection with reset-ou t, a general purp ose PLD, and man y
CC
csiop
) can be mapped anywh ere usi ng the DPL D; Two,
4/49
AN1560
DK3200 OVERVIEW
A picture of the DK320 0 board is shown in Figure 2.. Board layout and schematic s are in the Appen dix.
Connectors JP1, J3, J4, J5 provide easy access to all µPSD I/O signals for expansion or testing. JP1 accepts jumper shunts to wrap µ PSD ou tputs b ack into µ PSD i nputs f or tes ting. J 3, J4, J5 ca n conn ect directly to standard Agilent (HP) Logic analyzer pods. UARTs are available on P1 and P2. A USB host can
connect to the µPSD as a peri phe ral v ia J 2. The F lash LINK JTAG IS P cabl e co nnec ts at J1 . Conn ec tor s
JP2, JP3, JP4, JP5 allow direct connection of the In-Circuit Emulator from Nohau Corp, EMULuPSD3200-PC. JP6 ac cepts jumper s to c onnec t the sw itch es (SW 1, SW2) and the LEDs (LED 1, LED2)
to PSD port B. LED D5 indicates JTAG ISP Programming . The DK3200 also has a 2-line 16 character
LCD interface and a full featured real-time clock with SNAPHAT snap-on battery/crystal pack.
Figure 2. DK3200 Development Board
5/49
AN1560
DESIGN EXAMPLE BLOCK DIAGRAM
This simple design example is represented by the block diagram of Figure 3., and the memory map of
Figure 4.. All 16 macrocells of the PLD are used, Flash memory is paged, and few of the 8032 interfaces
(ADC, PWM, UART) are configured and used. The idea is to touch several aspects of the µPSD that may
be unfamiliar to a typica l 8051 user an d to give yo u an idea of how to use the des ign tools and be come
familiar with µPSD architecture.
Figure 3. Design Block Diagram
pin P4.7 (PMW0)
pin P1.4
(ADC0)
pin _RESET
pin XTAL1
40 MHz
pin XTAL2
pin P3.0 (RxD1)
pin P3.1 (TxD1)
RS-232 Transceiver
P1
A8 - A15
PWM0
ADC0
AD0-AD7
_RESET_IN
8032
XTAL1
XTAL2
RxD1
TxD1
Latch
ALE
8
8
DATA
ADDR
16
8
uPSD3234A-40U6
16
ADDR
15
256KB Main
Flash (data)
13
32KB 2ndary
Flash (code)
13
8KB SRAM
Data Bus
Repeater
8
256 Control Regs
16
pin PB4 (term_count)
16
fs0 - fs7
8
csboot0 -
csboot3
4
rs0
1
psel0 -
psel1
2
csiop
1
Initial Count
DownCounter
8
16 PLD
MarcoCells
pins PA0 - PA7 (LDC_d0 - LCD_d7)
ADDR
12
DATA pins P0.0 - P0.7
8
DPLD
Page Reg
(from Control
Regs)
JTAG
ISP
pin PB5 (LCD_rs)
pin PB6 (LCD_rw)
pin PB7 (LCD_e)
pins A0 - A11
pin PC0 (tms)
pin PC1 (tck)
pin PC3 (tstat)
pin PC4 (_terr)
pin PC5 (tdi)
pin PC6 (tdo)
pin PB0 (a12_x)
pin PB1 (a13_x)
pin PB2 (a14_x)
pin PB3 (a15_x)
REG SELECT
READ/WRITE
CHIP SELECT
D0 - D7
LCD
MODULE
AI07073
Figure 3. show s the de sign i mplem ented i n this appl ication note. Maj or el ements ar e the µ PS D, an LCD
module, and an RS-232 transceiver chip.
The 8032 outputs a repetitive PWM pulse train with a slowly varying pulse width to an RC network which
converts the pulse train in to a slowly sw eeping DC voltag e (0 to 5V). Th is DC signal i s looped back i nto
an ADC input. The 8032 will write the resulting Hexadecimal ADC conversion value to the LCD so you can
watch the results. The RC network and loop-back is implemented with two jumpers on the DK3200 board.
Additionally and independently, a 4-bit auto-reloading down-counter is created using PLD macrocells. The
8032 directly loads the initial count value into four macrocells, and that count is automatically loaded into
another four macrocells that create the 4-bit down-counter. Reloading occurs each time the counter reaches terminal count of zer o. Terminal count is indica ted externally by a puls e on a µPSD output pi n. The
down-counter is clocked by ALE signal (ALE was random choice, could be any signal). The 8032 may load
a different initial count at anytime, creating a variable divider of the ALE signal.
6/49
AN1560
Four more macrocells a re us ed to outp ut the high four 8032 address sign als . T he 80-pi n µPSD only outputs the low twelve 8032 address signals on dedicated pins. If more address signals are needed externally, they have to be added this way using the PLD.
The LCD module is connected to the µPSD via a Port A for data and Port B for some glue logic and a chipselect signal. Port A is operating is an special data bus repeater mode this example, called Peripheral I/O
mode. 8032 data will pass through port A onl y for a given address range specifie d in PSDsoft Express
(illustrated later).
Figure 4. 8032 Memory Map
Code Space (_PSEN) Data Space (_RD and _WR)
FFFF
Page X Page 0
Page 3
Page 7Page 5 Page 6Page 4Page 2Page 1
FFFF
8000
7FFF
6000
5FFF
4000
3FFF
2000
1FFF
0000
nothing mapped
csboot3
8K bytes uPSD
Secondary Flash
csboot2
8K bytes uPSD
Secondary Flash
csboot1
8K bytes uPSD
Secondary Flash
csboot0
8K bytes uPSD
Secondary Flash
fs0
32K bytes uPSD
Main Flash
(xdata)
fs1
32K bytes uPSD
Main Flash
(xdata)
fs2
32K bytes uPSD
Main Flash
(xdata)
LCD_e and psel
32K bytes uPSD
Main Flash
(xdata)
nothing mapped
fs4
fs3
32K bytes uPSD
Main Flash
(xdata)
nothing mapped
, 8K bytes PSD SRAM (xdata)
rs0
chip select and data bus repeater for LCD module
csiop
, cntl regs for ports A, B, C, D (xdata)
fs5
32K bytes uPSD
Main Flash
(xdata)
fs6
32K bytes uPSD
Main Flash
(xdata)
Common
Memory
Across All
Data Pages
fs7
32K bytes uPSD
Main Flash
(xdata)
8000
7FFF
4000
2000 - 3FFF
0400 - 1FFF
0300 - 03FF
0200 - 02FF
0000 - 00FF
AI07074b
The memory map in Figure 4. shows th at th e 32K b yte sec ondary F lash me mory is used for 8032 co de,
and the 256K byte main Flash memory is used for 8032 data, banked over eight pages. The nomenclature
fsx, csbootx, rs0, csiop,
µPSD main Flash mem or y h as a total of e igh t 32K by te s egm ents (
memory has a total o f fo ur 8K byt e s eg men ts (
segment (
rs0
). A group of µ PS D co ntr ol regi st er s wh ic h c ont rol I/O ports A, B, C, and D li e i n a 2 56-by te
xdata address space whose base address is named
is enabled over a giv en address range as specified by
select signal,
LCD_e
and
psel
in Figure 4. refer to the individual internal µPSD memory segments. The
csboot0-csboot3
csiop
. The µPSD has a data bus repeater feature that
psel
. Figure 4. also shows one e xternal mem ory
fs0..fs7
). The µPSD 8K byte SRAM has a single
). The µPS D se condary Flash
, for the LCD module. This memory map is specified using the software tool PSDsoft
Express. Each memory segment can be placed at virtually any address, which provides an infinite number
of mapping schemes. This is just one example.
We’ll keep things simple for this particular application note, meaning the 8032 will “boot” and run code contained completely withi n the 32K byte seconda ry Flash memory i n code space and we’ll tr eat the 256K
byte main Flash me mory as data only. However, this memory map may grow with the need s of your
project. For example, if a large Flash memory is needed for code space and IAP is required, a slight variation of the map in Figure 4. can accomplish this. The 8032 can boot from secondary Flash memory (secondary Flash memory resides in code space from 0-7FFF as in Figure 4.), then the 8032 can calculate a
checksum on the main Flash memory and then program the main Flash memory if necessary (main Flash
memory resides in data space from 8000- FFFF on eight pa ges as in Figure4.). After the contents of main
7/49
AN1560
Flash memory are verified, the 8032 c an write to s pecial register , called the VM regi ster within th e
register block, to “reclassify” the main Flash memory from data space to code space. After which, the 8032
will have access to 256K bytes of Flash memory for code in code space, paged across eight code pages
in upper memory (8000-FFFF), and the 8032 will have access to 32K bytes of Flash memory for code in
code space common to all pages in lower memory (0-7FFF). At that point no Flash memory will reside in
data space. Upon reset, the memory map is reset to look like Figure 4. again. The VM register can be accessed by the 8032 at runtime to perform a variety of manipulations. PSDsoft is used to set the initial value
of the VM register upon power-up. Future Application notes will illustrate various memory schemes.
csiop
8/49
AN1560
ENTERING DESIGN IN PSDSOFT EXPRESS
Highlights of the design process will be given here. The steps are simple and navigation through PSDsoft
Express is easy. Invoke PSDsoft Express and follow along if you wish. PSDsoft Express is included in the
DK3200 CD, but you should check for latest updates. Updates are available from our web site at
www.st.com/psm, in the “Software Downloads” area.
Invoke PSDsoft Express and Create Project
■ Install PDSsoft Express (from the web or the included CD)
■ Start PSDsoft Express
■ Create a new project
■ Select your project folder and name the project (in this example, name the project “DK3200_1” in the
folder
PSDexpress\my_project\dk3200_dsn_1\
Note that the folder,
dk3200_dsn_1 under PSDexpress\my_project
ed.
Select MCU and Initial Placement of Flash in Code Space or Data Space
■ Select an MCU. In this case it is STMicroelectronics, then uPSD32xx, then uPSD3234A.
■ Select the main Flash memory to reside in 8032 data space at power-up (means that the 8032 _RD
and _WR signals are routed to the main Flash memory array)
■ Select the secondary Flash memory to reside in 8032 code space at power-up (means that the 8032
_PSEN signal is routed to the secondary Flash memory array)
Note: At runtime, the 8032 can alter the initial settings of code and data space by writing to the VM register.
Figure 5. shows what the screen should look like after you’ve made the selections.
Click OK. Now you will be asked i f you want to use the Desi gn Assis tant, Ex tended Design As sist ant, or
Example Template. Choose Example Template. This is a predefined design that matches this application
note and it runs on the DK3200 board. Next choose the template for the DK3200 Kit when prompted.
Pin Definitions
You will see the Pin Definitions screen appear. All of the pin definitions shown in block diagram of Figure 3.
are filled in. Click through the pins and see how they are configured and how they relate to Figure 3.. You’ll
notice that you cannot change the definition of some pins because they have a fixed function.
A comment about JTAG pins. Th is example us es 6-pin JTA G which is up to 30% fas ter than the defau lt
standard 4-pin JTAG. The two extra pins in the 6-pin JTAG configuration are
Now click “Next” to move on to the Design A ssistant fo r memory mapp ing and logic equations. You will
see the Page Register definition screen.
..
, does not exist and needs to be creat-
_tstat
and
terr
.
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uPSD3000
Figure 5. MCU Selection
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Figure 6. Pin Definitions
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Memory Map
Defining the memory map requ ires defi ning the ad dress r ange of chip- sele cts for indiv idual me mory ele ments of the µPSD (memor y ex terna l to the 8032 c ore) . Defin ition of the use of the µPSD Page Regi ste r
is also required.
Four memory blocks (main Flash memory, secondary Flash memory, SRAM, and control registers) external to the 8032 core are available and are individually selected segment-by-segment when 8032 addresses are presented to the D ecode PLD (DPLD). E ach of these m emory segments ha s its own chip-se lect
name (
fs3, csboot1, rs0, c siop
must be specified using PSDsoft Express. For this example, chip-selects are defined to match the memory
map of Figure 4..
Page Register
Since eight memory pa ges (or banks) are ne eded as shown in Figure 4., thr ee paging bits (2
specified as sh ow n in Figure 7.. The µPSD supports up to 4 paging bits (pg0, pg1, pg2, pg3) for a total of
16 pages. Unused paging bits including pg4, pg5, pg6 and pg7 may be used for other functions. Note that
the paging bits used must be the LSB bits in the paging register. Click “Next”.
Figure 7. Page Register Definition
, etc.). Equations for these chip-s elect s, and fo r any e xternal chip-s elect s,
3
= 8) are
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AN1560
Chip-Select Equations
rs0
Now you will see the Chip- Sele ct de finition scr een. Clic k the chip- select signa l
SRAM, and see that its definition matches the memory map of Figure 4..
rs0
Notice that no page n umber is spe cified f or
dent). Additional signal qualifiers (8032 control signals
µPSD chip-selects as this is taken care of in silicon. The SRAM always defaults to 8032 data space.
At any time, you can click the “View” button to see how you are doing. A summary will appear.
csiop
Now click on the chip-select
control µPSD ports A, B, C, D, the Page Register, power management, and other functions. 40 of the 256
registers are used, se e µPSD datasheet for r egister definitions and th eir address offset from th e
base address. There i s no need to specify additional signal qu alifiers for
place
csiop
on a particular memory page. The
Next click on
Notice the page nu mbe r i s 0 for
Figure 4.. Cl ick on remain ing chip-selects f or main Flash m emory and notice the page number assign-
ments. No additional signal qualifiers are needed.
Figure 8. Chip-Select Definition for 8K byte SRAM
fs0. fs0 .. fs7
are chip-selects for the eight 32K byte segments of µPSD main Flash memory.
(Chip Select I/O Por t). This is a band o f 256 xdata registe rs used to
fs0
, and the address range is 8000 - FFFF as shown in memory map of
since the SRAM is c ommon to all pages (page i ndepen -
_rd, _wr, _psen, ale
) are NOT needed for internal
csiop
csiop
must be xdata address space.
for the 8K byte xdata
csiop
, and it is not allowed to
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Figure 9. Chip-Select Definition for Flash Memory Segments
Now click on
ary Flash memory. Check the address assignments for each of these chip-selects and notice there are no
page numbers assigned. The secondary Flash memory is common to all pages.
Next click on
Peripheral I/O Mode to dr i ve the LCD m odule. Port A pins were ear lier sp ec ified a “Peripheral I/O M ode ”
which acts like a ‘245 bus tr ansceiver chi p connecting the 8032 d ata bus to exter nal peripher als over a
given address range specified by the label
trolled automatically in silicon by the 8032
have to do is click on
range as shown in Figure 4., with no Page Number assignment.
eral I/O feature is active for the logical OR of
And finally, clic k on
chip-select, we mus t include signal qualifiers
when the 8032 presents an a ddres s in the r ang e of 3 00 to 3F F AND wh en e ithe r 8032 co ntr ol signal
is true, OR when 8032 cont rol sig nal
Figure 10.. Since both signals
are specified as qualifiers. Signal qualifiers may be added by setting the cursor where you want the signal
name to go, then just double click on the signal name in the list of eligible qualifiers.
Click “next” to move on to logic definitions.
csboot0. csboot0 .. csboot3
psel0
. This address range specifies when Port A pins will behave like a data bus repeater in
psel0
and enter the address range 300 to 3FF to enable this feature for that address
LCD_e
. This is an external chip-select for the LCD module. Since this is an external
_rd
and
are chip-selects for the four 8K byte segments of µPSD second-
psel0
or
psel1
. The direction of this transceiver function is con-
_rd
and
_wr
signals. See µPSD data sheet for details. So all we
psel1
is not needed because the Periph-
psel0
or
psel1
.
_rd
and
_wr.
In this design,
_wr
is true. To create this log ic, in format ion is entere d as shown in
_wr
are active low, the logical NOT operator (!) is used when they
LCD_e
is true (active hi) only
_rd
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Figure 10. External Chip-Select Definition for LCD Module
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I/O Logic Equations
Defined here are equations for PLD outputs for the LCD interface signals, the additional 8032 address outputs, and the terminal count output signa l from the down-cou nter. The De sign Assista nt (DA) will c reate
HDL logic statements using the ABEL language in the background after you enter logic in this point-andclick design entry environment. The DA will also create all the declaration statements in ABEL. This saves
much typing and reduces the c han ce of err or . For m ore co mpl ic ate d lo gic PSDs oft al lo ws you to edit the
ABEL statements d irec tl y. In th is ex am pl e you’ ll s ee si mpl e l og ic entered point-and- clic k st yl e, a nd yo u’l l
see the 4-bit down-counter entered by editing the ABEL file directly.
Click on “
output signal “
logic operators are also available for general purpose logic.
LCD_rw
” as shown in Figure 11., and notice t hat the inter nal sign al a0 is assigned to drive the
LCD_rw
”. Although this was a very simple logic equation, AND, OR, XOR, NOT, and other
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