ST AN1517 APPLICATION NOTE

AN1517

Application note

Designing with the L5972D high efficiency DC-DC converter

Introduction

The L5972D is a step-down monolithic power switching regulator capable of delivering up to 2 A at output voltages from 1.235 V to 35 V. The operating input voltage ranges from 4.4 V to 36 V. It has been designed using BCDV technology and the power switching element is implemented through a P-channel DMOS transistor. It does not require a bootstrap capacitor, and the duty cycle can range up to 100%. An internal oscillator fixes the switching frequency at 250 kHz. This minimizes the LC output filter.

Pulse-by-pulse and frequency foldback over-current protection offer effective protection against short-circuit. Other features are voltage feed-forward, protection against feedback disconnection, and thermal shutdown. The device is housed in a thermally improved SO-8 package (with 4 pins connected to GND so that the thermal resistance junction-to-ambient is reduced to approximately one-half compared with a standard SO-8 package.

Figure 1. Demonstration board

L5972D (SO-8) Board dimensions: 23 x 20 mm

Figure 2. Package Figure 3. Pin connection

May 2008 Rev 2 1/29

VCC

AM00004v1

GND

VREF

www.st.com

SO-8

OUT

SYNC

INH

COMP

Contents AN1517

Contents

1 Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.1 Power supply and voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.2 Voltages monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.3 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.4 Current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.5 Error amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.6 PWM comparator and power stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.7 Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3 Additional features and protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.1 Feedback disconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.2 Output over-voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.3 Zero load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

4 Closing the loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4.1 Error amplifier and compensation network . . . . . . . . . . . . . . . . . . . . . . . . 11

4.2 LC filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.3 PWM comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.1 Component selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.1.1 Input capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.1.2 Output capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.1.3 Inductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.2 Layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.3 Thermal considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5.4 Short-circuit protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.5 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6 Application ideas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

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AN1517 Contents

6.1 Positive buck-boost regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

7 Buck-boost regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

7.1 Dual output voltage with auxiliary winding . . . . . . . . . . . . . . . . . . . . . . . . 25

8 Compensation network with MLCC (multiple layer ceramic capacitor) at

the output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

8.1 External soft-start network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3/29

List of figures AN1517

List of figures

Figure 1. Demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 2. Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 3. Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 4. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 5. Internal regulator circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 6. Oscillator circuit block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 7. Current limitation circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 8. Driving circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 9. Block diagram of the loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 10. Error amplifier equivalent circuit and compensation network . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 11. Module plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 12. Phase plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 13. Layout example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 14. Short-circuit current V Figure 15. Short-circuit current V

Figure 16. Demonstration board application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 17. PCB layout (component side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 18. PCB layout (bottom side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 19. PCB layout (front side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 20. Junction temperature vs. output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 21. Junction temperature vs. output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 22. Junction temperature vs. output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 23. Efficiency vs. output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 24. Positive buck-boost regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 25. Buck-boost regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 26. Dual output voltage with auxiliary winding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 27. MLCC compensation network example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 28. Soft-start network example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

= 25 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

= 30 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

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AN1517 Pin functions

1 Pin functions

1.1 Pin description

Table 1. Pin description

N. Name Description

1 OUT Regulator output.

2GND

Ground. Lead connected directly to the frame in order to reduce the junction-to-ambient thermal resistance.

3GND

Ground. Lead connected directly to the frame in order to reduce the junction-to-ambient thermal resistance.

4 COMP E/A output to be used for frequency compensation.

Step-down feedback input. Connecting the output voltage directly to this pin results in

5FB

an output voltage of 1.235 V. An external resistor divider is required for higher output voltages (the typical value for the resistor connected between this pin and ground is

4.7 k).

6GND

7GND

Ground. Lead connected directly to the frame in order to reduce the junction-to-ambient thermal resistance.

Unregulated DC input voltage.

Figure 4. Block diagram

VOLTAGES

MONITOR

PWM

THERMAL

SHUTDOWN

SUPPLY

1.235V 3.5V

PEAK TO PEAK

CURRENT LIMIT

DCkQ

GND

COMP

GND

TRIMMING

1.235V

E/A

OSCILLATOR

DRIVER

FREQUENCY

SHIFTER

VCC

REF

BUFFER

LPDMOS

POWER

GND

GND OUT

AM00028v1

5/29

Functional description AN1517

2 Functional description

The main internal blocks are shown in the device block diagram in Figure 4. They are:

● A voltage regulator that supplies the internal circuitry. From this regulator, a 3.3 V

reference voltage is externally available.

● A voltage monitor circuit which checks the input and internal voltages.

● A fully integrated sawtooth oscillator with a frequency of 250 kHz ±15%, including also

the voltage feed-forward function and an input/output synchronization pin.

● Two embedded current limitation circuits which control the current that flows through

the power switch. The pulse-by-pulse current limit forces the power switch OFF cycle by cycle if the current reaches an internal threshold, while the frequency shifter reduces the switching frequency in order to significantly reduce the duty cycle.

● A transconductance error amplifier.

● A pulse width modulation (PWM) comparator and the relative logic circuitry necessary

to drive the internal power.

● A high-side driver for the internal P-MOS switch.

● A circuit to implement the thermal protection function.

2.1 Power supply and voltage reference

The internal regulator circuit (shown in Figure 5) consists of a start-up circuit, an internal voltage Preregulator, the Bandgap voltage reference and the Bias block that provides current to all the blocks.

The Starter gives the start-up currents to the entire device when the input voltage goes high and the device is enabled (inhibit pin connected to ground).

The Preregulator block supplies the Bandgap cell with a preregulated voltage V a very low supply voltage noise sensitivity.

2.2 Voltages monitor

An internal block continuously senses the VCC, V their thresholds, the regulator begins operating. There is also a hysteresis on the V (UVLO).

and VBG. If the voltages go higher than

REF

REG

that has

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AN1517 Functional description

Figure 5. Internal regulator circuit

2.3 Oscillator

Figure 6 shows the block diagram of the oscillator circuit.

The Clock Generator provides the switching frequency of the device, which is internally fixed at 250 kHz. The Frequency Shifter block acts to reduce the switching frequency in case of strong over-current or short-circuit. The clock signal is then used in the internal logic circuitry and is the input of the Ramp Generator.

The Ramp Generator circuit provides the sawtooth signal, used to for PWM control and the internal voltage feed-forward.

Figure 6. Oscillator circuit block diagram

STARTER

PREREGULATOR

VREG

BANDGAP

IC BIAS

VREF

AM00006v1

2.4 Current protection

The L5973AD has two types of current limit protection: pulse-by-pulse and frequency foldback.

The schematic of the current limitation circuitry for the pulse-by-pulse protection is shown in

Figure 7. The output power PDMOS transistor is split into two parallel PDMOS transistors.

The smallest one includes a resistor in series, R R switched off until the next falling edge of the internal clock pulse.

and if it reaches the threshold, the mirror becomes unbalanced and the PDMOS is

SENSE

FREQUENCY

Ibias_osc

GENERATOR

FREQUENCY

SHIFTER

CLOCK

GENERATOR

RAMP

GENERATOR

SYNCHRONIZATOR

SYNCHRONIZER

. The current is sensed through

SENSE

CLOCK

RAMP

SYNC

AM00007v1

7/29

Functional description AN1517

Due to this reduction of the ON time, the output voltage decreases.

Since the minimum switch ON time (necessary to avoid a false over-current signal) is too short to obtain a sufficiently low duty cycle at 250 kHz, the output current, in strong overcurrent or short-circuit conditions, could increase again. For this reason the switching frequency is also reduced, thus keeping the inductor current under its maximum threshold. The Frequency Shifter (Figure 6) functions based on the feedback voltage. As the feedback voltage decreases (due to the reduced duty cycle), the switching frequency decreases also.

Figure 7. Current limitation circuitry

VCC

DRIVER

OUT

A1/A2=95

PWM

RSENSE

OFF

RTH

NOT

AM00008v1

2.5 Error amplifier

The voltage error amplifier is the core of the loop regulation. It is a transconductance operational amplifier whose non inverting input is connected to the internal voltage reference (1.235 V), while the inverting input (FB) is connected to the external divider or directly to the output voltage. The output (COMP) is connected to the external compensation network. The uncompensated error amplifier has the following characteristics:

Table 2. Uncompensated error amplifier characteristics

Description Values

Transconductance 2300 µS

Low frequency gain 65 dB

Minimum sink/source voltage 1500 µA/300 µA

Output voltage swing 0.4 V/3.65 V

Input bias current 2.5 µA

The error amplifier output is compared with the oscillator sawtooth to perform PWM control.

2.6 PWM comparator and power stage

This block compares the oscillator sawtooth and the error amplifier output signals generating the PWM signal for the driving stage.

The power stage is a highly critical block, as it functions to guarantee a correct turn ON and turn OFF of the PDMOS. The turn ON of the power element, or more accurately, the rise time of the current at turn ON, is a very critical parameter. At a first approach, it appears that

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AN1517 Functional description

the faster the rise time, the lower the turn ON losses. However, there is a limit introduced by the recovery time of the recirculation diode.

In fact, when the current of the power element is equal to the inductor current, the diode turns OFF and the drain of the power is able to go high. But during its recovery time, the diode can be considered a high value capacitor and this produces a very high peak current, responsible for many problems:

● Spikes on the device supply voltage that cause oscillations (and thus noise) due to the

board parasitics

● Turn ON over-current leads to a decrease in the efficiency and system reliability

● Major EMI problems

● Shorter freewheeling diode life

The fall time of the current during the turn OFF is also critical, as it produces voltage spikes (due to the parasitics elements of the board) that increase the voltage drop across the PDMOS.

In order to minimize these problems, a new driving circuit topology has been used and the block diagram is shown in Figure 8. The basic idea is to change the current levels used to turn the power switch ON and OFF, based on the PDMOS and the gate clamp status.

This circuitry allows the power switch to be turned OFF and ON quickly and addresses the freewheeling diode recovery time problem. The gate clamp is necessary to avoid that V the internal switch goes higher than V

max. The ON/OFF Control block protects against

any cross conduction between the supply line and ground.

Figure 8. Driving circuitry

Vgs

STOP

DRIVE

DRAIN

2.7 Thermal shutdown

The Thermal Shutdown block generates a signal that turns OFF the power stage if the temperature of the chip goes higher than a fixed internal threshold (150 °C). The sensing element of the chip is very close to the PDMOS area, ensuring fast and accurate temperature detection. A hysteresis of approximately 20 °C avoids that the device turns ON and OFF continuously.

max

CLAMP

ON/OFF

CONTROL

GATE

OFF

DRAIN

VCC

PDMOS

ESR

VOUT

AM00009v1

LOAD

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