ST AN1496 APPLICATION NOTE

AN1496

APPLICATION NOTE

Flash Programming / Reprogramming ST10F269 / ST10F280

By André ROGER

INTRODUCTION

This application not e provides with software guidelines and examples for programming ST10F269 and ST10F280. More generally, this application note is applicable for any ST10 variant with 0.35µm technology embedded Flash memory.

The first chapter gives an overview the ST10F269/ F2 80 em bedded Flash key features. It also shows the differences between ST10F269/ST10F280 and ST10F 168.

The second chapter de scribes h ow to develop software for ST10’s embedded Flash t hrough guidelines, examples and tips.

The last chapter is dedicat ed to embedded application aspects. More specifically, it gi ves advises for Flash field reprogramming.

This application note do es not replace ST10 p roduct datashe ets. It refers to them and it is necessary to have a copy the specific ST10 variant targetted by the user to follow some of the explanations.

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TABLE OF CONTENTS PAGE

1 INTRODUCTION TO ST10 0.35MM EMBEDDED FLASH ......................................... 3

1.1 DIFFERENCES WITH ST10F 1 68..... ............ ............ ............ ....................... ............ ... 3

1.1.1 Single Supply.................................................................................... ................... ........ 3

1.1.2 New Erase/Program Controller.................................................................................... 3

1.1.3 Improved Granularity of Block Sizes ........................................................................... 3

1.2 COMPARISON WITH STAND-ALONE FLASH MEMORIES...................................... 3

1.2.1 Similar But Different Erase/Program Commands........................................................ 3

1.2.2 Description of the Commands to the Flash Controller................................................. 3

1.2.3 Same Flash Status Register ........................................................................................ 5

1.2.4 Bo o t Blocks Architecture .......... ....................... ............ ............ ............ ............ ............ 6

1.2.5 Pr o tection ........... ........................ ............ ............ ............ ........... ........................ .......... 6

2 WRITING CODE FOR THE FLASH OF ST10 WITH 0.35MM EMBEDDED FLASH.. 7

2.1 ST10 PROGRAMMING CONSTRAINTS .................................................................... 7

2.2 POLLING THE FLASH ERASE PROGRAM CONTROLLER..................................... 7

2.2.1 Ready/Busy Signal ...................................................................................................... 7

2.2.2 Flash Status Register .................................................................................................. 7

2.3 FLASH MEMORY MAPPING IN ST10 SPACE........................................................... 7

2.4 PROGRAMMING COMMAND.................. ............ ........................ ............ ........... ........ 8

2.5 ERASING COMMAND ................................................................................................ 9

2.6 FLASH PROTECTION COMMANDS.......................................................................... 10

2.6.1 Block Protection..... ............ ....................... ............ ............ ............ ............ ................... 10

2.6.2 Code Protection........................................................................................................... 10

2.6.2.1 Using Code Protection with ST10................................................................................ 10

2.6.2.2 Code Protection and Bootstrap Loader . ...................................................................... 10

2.6.2.3 Code Protection and Block0 Protection....................................................................... 11

2.7 OTHER FLASH COMMANDS..................................................................................... 12

2.8 TIPS TO REDUCE FLASH PROGRAM AND ERASE TIMES .................................... 12

2.8.1 Reducing the Programming Time................................................................................ 12

2.8.2 Reducing Erase Times ........................................................................................ ........ 12

3 EMBEDDED APPLICATION ASPECTS..................................................................... 13

3.1 READING THE FLASH WHILE ERASING OR PROGRAMMING .............................. 13

3.1.1 Minimum Software to be Copied into the On-chip RAM.............................................. 13

3.1.2 Maximizing Programming Performance at System Level............................................ 13

3.1.3 Suspend and Resume Commands.............................................................................. 13

3.2 FIELD REPROGRAMMING WITH ST10F269 ............................................................ 14

3.2.1 Reset ........................................................................................................................... 14

3.2.2 List of Events and Suggested Handling Methods........................................................ 14

3.2.2.1 Supply out of ST Specification. .................................................................................... 14

3.2.2.2 ST10 PLL Unlock......................................................................................................... 14

3.2.3 Generic Aspects of Flash Field Reprogramming......................................................... 14

3.2.3.1 Completion of the Reprogramming Process................................................................ 15

3.2.3.2 Events That May Interrupt the Reprogramming Process ............................................ 15

4 QUICK SUMMARY ..................................................................................................... 16

5 CONCLUSION ............................................................................................................ 16

6 APPLICATION NOTE VERSION INFORMATION...................................................... 16

6.1 REVISION OF 26TH OF FEBRUARY 2002................................................................ 16

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1 - INTRODUCTION TO ST10 0.35µm EMB E DDED FL A SH

This chapter is describing the improvements made from the ST10F168 and the differences with stand-alone Flash memories.

1.1 - Differences with ST10F168

1.1.1 - Single Supply

ST10 variants with 0.35µm embedded Flash do not require specific programming supply. On-chip charge pumps will provide with the necessary programming supply from the external single 5 volt supply.

1.1.2 - New Erase/Program Controller

The 0.35µm Erase/Program Controller has been changed to be closer to the one of stand-alone Flas h memories : erasing and programming of Flash memory cells is no more done by the ST10. This allows :

Savings on system stack :

–

ing and programming,

Improved efficiency during programming :

–

the time where the Erase/Program Controller is dealing with the Flash,

Improved clock scheme :

–

to specify it the CPU clock. This also simplifies the hand ling of special events (like PLL unlock) during erasing/programming.

there is no more need to allocate space on the ST10 system stack f or eras-

ST10 CPU can be used to handle communication during

the Flash erase/program controller has its own clock; there is no more need

1.1.3 - Improved Granularity of Block Sizes

ST10 0.35µm embedded Flash has improved block granulaty (smaller blocks) and also features boot block organisation :

– Block size is 64 Kbyte for standard blocks, – Small blocks for the 4 boot blocks (16 Kbyte, then 8 Kbyte, 8 Kbyte, 32 Kbyte).

1.2 - Comparison with Stand-alone Flash Memories

1.2.1 - Similar But Different Erase/Program Commands

The Erase/program Controller of ST10F269/F280 is derived from the Common Flash memory Interface : – To keep the same level of proven safety, the special sequence of commands of stand alone Flash mem-

ories has been kept,

– To differentiate from ex ternal Flash memories, the value of the commands (address and data) have

been slighlty modified.

This allows to re-use existing software written for stand-alone Flash memories with few modifications. The following chapters describe them.

1.2.2 - Description of the Commands to the Flash Controller

The following table is describing the possible commands with ST10F269/F280 Erase/Program Controller. Commands to the Flash are defined by a sequence of ST10 write cycles with specific addresses and data

within the Flash memor y range. The length of the seq uence varies from 1 cycle (ex : Read/Reset) to 6 cycles (chip erase).

Block erase command can be extended by 1 cycle per additional block to erase. This translates in a maximum of 12 cycles for ST10F2 69 and of 16 cycles for ST10F280.

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Table 1 :

Commands for ST10 with 0.35µm embedded Flash

Instruction Mne Cycle

Read/Reset RD 1+

Read/Reset RD 3+

Program Word PW 4

Block Erase BE 6

Chip Erase CE 6

Erase Suspend ES 1

Erase Resume ER 1

Set Block/Code Protection

SP 4

Read Protection Status

RP 4

Block Temporary

BTU 4

Unprotection Code

Temporary

CTU 1

Unprotection Code

Temporary

CTP 1

Protection

Cycle

Addr.

Data xxF0h

Addr.

x1554h x2AA8h xxxxxh

Data xxA8h xx54h xxF0h

Addr.

x1554h x2AA8h x1554h WA

Data xxA8h xx54h xxA0h WD

Addr.

x1554h x2AA8h x1554h x1554h x2AA8h BA BA’

Cycle

3rd Cycle 4th Cycle

5th

Cycle

6th

Cycle

Read Memory Array until a new write cycle is initiated

Read Data Polling or Toggle Bit until Program

completes.

7th

Cycle

Data xxA8h xx54h xx80h xxA8h xx54h xx30h xx30h

Addr.

Data xxA8h xx54h xx80h xxA8h xx54h xx10h

Addr.

Data xxB0h

Addr.

Data xx30h

Addr.

Data xxA8h xx54h xxC0h WPR

x1554h x2AA8h x1554h x1554h x2AA8h x1554h

Read until Toggle stops, then read or program all data needed from block(s) not being erased then Resume Erase.

Read Data Polling or Toggle bit until Erase completes or Erase is supended another time.

x2A54h x15A8h x2A54h Any odd

word

address

Note

Addr.1x2A54h x15A8h x2A54h Any odd

word

address

Data xxA8h xx54h xx90h Read

Read Protection Register

until a new write cycle is initiated.

Addr.

x2A54h x15A8h x2A54h X

Data xxA8h xx54h xxC1h xxF0h

Addr.

Data FFFFh

Addr.

Data FFFBh

MEM

Write cycles must be executed from Flash.

Notes 1. Address bi t A14, A15 and above are don’t care for coded address inputs.

2. X = Don’t Care.

3. WA = Write Address: address of memor y location t o be programmed.

4. WD = Write Data: 16-bi t data to be programmed

5. Optional, add i tional blocks addresses must be entered within a time-out delay (96 µs) after l ast wr i te entr y, timeout st at us can be verified through FSB.3 value. When full command is entered, read Data Polling or Toggle bit until Erase is completed or suspend ed.

6. Read Data Polling or Toggle bit until Erase completes.

7. WPR = W rite protection r egister. To pr ot ect code, bi t 15 of WPR must be ‘0’. To protect block N (N=0,1,. .. ), bit N o f WPR mu st be ‘0’. Bit that are already at ‘0’ in protection register must also be ‘0’ in WPR, else a writing error will occurs (it is not possible to write a ‘1’ in a bit already programmed at ‘0’).

8. MEM = any address inside the Flash memory spa ce. Absolut e addressing mo de must be used (MOV MEM, Rn), and inst ruction must be executed from F l ash memory space.

9. Odd word address = 4n-2 w here n = 0, 1, 2, 3..., ex. 00 02h, 0006h. ..

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1.2.3 - Same Flash Status Register

The Flash Status register is used to flag the status of the Flash memory and the result of an operation. To maximise the re-use of Flash programming software, the Flash Status register of stand-alone Flash

memories has been kept. This register can be accessed by Read cycles during the program-Erase Controller operations. The

Erase/Program operation can be controlled by data polling on bi t FSB7 of Status Re gister, detection of Toggle on FSB6 and FSB2, or Error on FSB5 and Erase Timeout on FSB3 bits. Any read attempt in Flash during Erase/Program. operation will automatically output these five bits. The E.P.C. sets bits FSB2, FSB3, FSB5, FSB6 and FSB7. Other bits are reserved for future use and should be masked.

Flash Status (see note for address)

1514131211109876543210

Bit Function

FSB.7

FSB.6

FSB.5

FSB.3

FSB.2

Flash Status Bit 7: Data Polling Bit

Programming Op eration: this bit outputs the complement of the bit 7 of the word being programme d, and after completion, will output the bit 7 of the word programmed.

Erasing Operation: outputs a ‘0’ during erasing, and ‘1’ after erasing completion. If the Block selected for erasure is (ar e) pro tected, FSB.7 wi ll be se t to ‘0’ for about 100 µs, and th en ret ur n

to the previous addressed memory data value. FSB.7 will also flag the Erase Suspend Mode by switching from ‘0’ to ‘1’ at the start of the Erase Suspend. During Program o peration in Erase Suspend Mo de, FSB.7 will have the same behaviou r as in nor mal Pro-

gram execution outside the Suspend mode.

Flash Status Bit 6: Toggle Bit

Programming or Erasing Operations: successive read operations of Flash Status register will deliver complementar y values. FSB.6 will toggle each time the Flash Status register is read. The Program operation is completed when two successive reads yield the same value. Th e next read will output the bit last programmed, or a ‘1’ after Erase operation

FSB.6 will be set to‘1 ’ if a re ad op eration is attempted on a n Erase S uspe nded block. In additio n, an Erase Suspend/Resume command will cause FSB.6 to toggle.

Flash Status Bit 5: Error Bit

This bit is set to ‘1’ when there is a failure of Program, Block or Chip Erase operations.This bit will also be set if a user tries to program a bit to ‘1’ to a Flash location that is currently programmed with ‘0’.

The error bit resets after Read/Reset instruction. In case of success, the Error bit will be set to ‘0’ during Program or Erase and then will output the bit last pro-

grammed or a ‘1’ after erasing

Flash Status Bit 3: Erase Time-out Bit

This bit is set to ‘1’ by the P/E.C. when th e last Block Erase c ommand ha s been ente red to the C ommand Interface and it is awaiting the Erase start. Wh en the time-out per iod is finished, aft er 96 µs, FSB.3 returns back to ‘1’.

Flash Status Bit 2: Toggle Bit

This toggle bit, tog ether with FSB.6, can be used to dete rmine the chip status during the Erase Mode or Erase Suspend Mode. It can be used also to identifiey the block being Erased Suspended. A Read operation will cause FSB.2 to Toggle during the Erase Mode. If the Flash is in Erase Suspend Mode, a Read operation from the Erase suspended block or a Program operation into the Erase suspended block will cause FSB.2 to toggle.

When the Flash is in Pro gram Mode dur ing Eras e Susp end, FSB.2 will be read a s ‘1’ if ad dress used is the address of the word being programmed.

After Erase completion with an Error status, FSB.2 will toggle when reading the faulty sector.

FSB.7 FSB.6 FSB.5 FSB.3 FSB.2

RRR RR

Note :

The address of the Flash Status Register is the address o f the word being programmed when Programming operation is in progress, or an address within the block being erased when Erasing operation is in progress.

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