ST AN1491 Application note

AN1491

APPLICATION NOTE

IGBT BASICS

M. Aleo ([e-mail])

1. INTRODUCTION.

IGBTs (Insulated Gate Bipolar Transistors) combine the simplicity of drive and the excellent fast
switchin g capabilit y of the MO SFET str ucture with the ability t o handle h igh curren t values t ypical of a
bipolar device. IGBTs also offer good behavior in terms of voltage drop. IGBT technology, developed in
the early 1980s, has quickly gaine d market share for app lications exceeding 400V and that work up to
130kHz. This paper includes a brief description of the structure and the physics of the device, followed by
an analysis of the principal static and dynamic characteristics. Further details about the behavior in
operation will also be analyzed and discussed in order to give a complete overview of the main
parameters, features, and static and dynamic behaviors of this power component.

2. IGBT STRUCTURE AND OPERATION.
Figure 1: IGBT Structure And Equivalent Schematic

ALUMINUM

N+

N­N+

P+

IGBTs are a natural evolution of the vertical Power MOSFETs for high current, high voltage applications
and fast end-equipment. This device eliminates the main disadvan tage of current high voltage power
MOSFETs characterized b y an high value of R

path necessary to obtain a high breakdown voltage BV
levels are considerably less in IGBT technology even when compared with the latest generation of Power

MOSFET devices that have been greatly improved in terms of R

N+ N+

P+

GATE

EMITTER

SUBSTRATE

COLLECTOR

POLYSILICON

N+

P+

caused by the high resistivity of the source-drain

DS(on)

DSS

J3

J2

J1

. The power conduction losses at high current

G

. The lower voltage drop,

DS(on)

C

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translated into a low V

standard bipolar device simpl ifying the IGBTs driver schematic as well. The vertical section depi cted in
figure 1 together with the equivalent circuit shows IGBTs basic structure.

3. TURN-ON.

The structure of the silicon die is evidently similar to that of a Power MOSFET with the fundamental
difference of the addition o f a P+ substrate a nd an N+ buffer layer (absent in NPT-non-punch-through­IGBT technology). This is represented in the equivalent schematic (figure 1), with a MOSFET driving two
bipolar devices. The presence of the substrate cre ates a junction J1 between t he P+ and th e N zone of
the body.

When the positive gate bias allows the inversion of the P base region under the gate, an N channel is
created, with a flow of electrons, generating a current in the exact same way as a Power MOSFET. If the
voltage caused by this flux is in the range of 0.7V, then J1 is forward biased and some holes are injected
in the N- region, modulating the resistance between anode and cathode, in this way decreasing the
overall power conduction losses and a second flow of charges starts.

The final result is the contemporary presence of two different typologies of current inside the
semiconductor’s layers:

- an electron flux (MOSFET current);

- a hole current (bipolar).

, together with the device’s structure allow a higher current density than a

CE(sat)

The typical waveforms with an inductive load are reported in figure 2.

Figure 2: Typical Waveforms During Turn-On

V

CC

V

ge

L

O

A

V

CE

D

I

C

gnd

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4. TURN-OFF.

When a negative bias is applied to the gate or the gate voltage falls below the threshold value, the
channel is inhibited and no holes are i njected in the N- region . In any case even if the MO SFET current
decreases rapidly in t he switching off phase, the collector current gradual ly reduces because t here are
minority car riers still pre sent in the N laye r, immedia tely aft er th e start of c om mutati on. Th e d ecre ase i n
value of this residual current (tail) is strictly dependent on the de nsity of these charges in turn-off that is

linked to several factors as the amount of dopant, dopant typology, layers’ thickness and temperature.

The minority carrier’s density decay gives the characteristic tail shape (reported in figure 3) to the
collector c ur re n t th at is re sp o ns ible for:

- an increase in power losses;

- cross conduction problems, in peculiar appliances where the free-wheeling diodes are used.

Figure 3: Typical Waveforms During Turn-Off

V

ge

V

CE

Considering that the tail current is linked to the minority carrier’s recombination its value and shape are
strictly related to the holes’ mobility strictly related to the temperature r eached by the die, I

depending on the temperature reached, it is possible to reduce the undesirable effect of this current
acting on the end equipment design, as indicated in the graphs below, where the tail current (I

behavior related to V

, IC, and TC is depicted (figure 4).

CE

I

C

and VCE. So

C

tail

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AN1491 - APPLICATION NOTE

Figure 4: I

I

tail

8
7
6
5
4
3
2
1
0

0 5 10 15 20 25

Dependance From IC, TC, and V

tail

(A)

Tc = 100°C
Vce = 400V
Rg = 100Ω
Vge = 15V

IC(A)

4

3.5
3

2.5
2

1.5
1

0.5
0

CE

I

(A)

tail

4

3.5
3

2.5
2

1.5
1

0.5
0

0 100 200 300 400 500

Tc = 100°C
Ic = 10A
Rg = 100Ω
Vge = 15V

VCE(V)

I

(A)

tail

Vce=400°C
Ic = 10A
Rg = 100Ω
Vge = 15V

0 25 50 75 100 125

TC(°C)

5. REVERSE BLOCKING .

When a negative vol tage is applied to the collector then J1 is reverse biased and the de pletion layer

expands to the N- region. This mechanism is fundamental because an excessive reduction of this layer’s
thickness does not obtain a valid blocking capability. On the other hand increasing the dimension of this
region too much consistently elevates the voltage drop.

This second option explains clearly why NPT devices have a higher voltage drop when compared with an
equivalent (equal I

6. FORWARD BLOCKING.

When gate and emitter are shorted and a positive voltage is applied to the collector terminal the P/N- the
J3 junction is reverse biased. Again it is th e depletion layer in the N- drift region that withstands the
voltage applied.

7. LAT CH UP.

IGBT s contains a parasitic PNPN thyristor between the collector and the emitter, as evidenced in figure 1.
Under particular conditions this parasitic device enters in turn on. This causes an i nc rease in the c urrent
flowing between emitter and coll ector, a lose of control of the equivalent MOS FET and gene rally the
disruption of the compon ent. T he turn-o n of the thyristor is k nown as la tch up of the I GBT, more in detail

and speed) PT part.

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the causes of this failure are different and strictly dependent on the status of the device.

In general a static and a dynamic latch up are distinguished by the following:

- Static latch up happens when the device is in full conduction.

- Dynamic latch up takes place only du ring turn-off. This peculiar phenomenon strongly limits the safe
operating area.

In order to avoid this dangerous effect of the parasitic NPN and PNP transistors it is necessary:

- to prevent the turn-on of the NPN part, modifying both the layout and doping level;

- to reduce the overall current gain of the NPN and PNP transistors.

Furthermore the latching current is strictly dependent on the junctions’ temperature since it affects the
current gains of PNP and NPN parts; moreover with an increase of temperature, together with the gains,
the resistance of the P base region becomes higher, aggravating the overall behavior. So particular
attention must be paid by the manufacturer of the parts in order keep distant the maximum collector
current value to the one of the latching current. In general the ratio is in the order of 1 to 5.

8. FORWARD CONDUCTION CHARACTERISTICS.
Figure 5: Forward Characteris tics And Equi valent Sc hematic Operation

Ice(A)

C

10

8
6
4
2
0

0 0.6 1 1.5 2 2.5 3 3.5 4 4.5 5

V

(V)

CE(sat)

3.5

V

(V)

CE

3

G

2.5
2

1.5
1

E

0.5
0

0 5 10 15 20

I

(A)

C

The IGBT in conduction can be modeled, as a first approximation, as a PNP transistor driven by a Power
MOSFET. Figure 5 only shows the el ements of the structure necessary for the understanding of physic
the device in operation (parasitic elements are not considered).

As showed in the graph rep orting I

as a func tion of VCE (static characteristic), the collector current I

C

does not flow if the vol tage drop between anode and cathode does not exceed 0.7V even if the gate
signal allows the formation of the MOSFET channel, as evidenced in the graphs.

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