ST AN1491 Application note

AN1491

APPLICATION NOTE

IGBT BASICS

M. Aleo ([e-mail])

1. INTRODUCTION.

IGBTs (Insulated Gate Bipolar Transistors) combine the simplicity of drive and the excellent fast switching capability of the MOSFET structure with the ability to handle high current values typical of a bipolar device. IGBTs also offer good behavior in terms of voltage drop. IGBT technology, developed in the early 1980s, has quickly gained market share for applications exceeding 400V and that work up to 130kHz. This paper includes a brief description of the structure and the physics of the device, followed by an analysis of the principal static and dynamic characteristics. Further details about the behavior in operation will also be analyzed and discussed in order to give a complete overview of the main parameters, features, and static and dynamic behaviors of this power component.

2. IGBT STRUCTURE AND OPERATION.

Figure 1: IGBT Structure And Equivalent Schematic

ALUMINUM GATE

C

POLYSILICON

EMITTER

N+

N+

N+

N+

P+

P+

J3

J2

N-

N+

P+	SUBSTRATE		G
		J1

E

COLLECTOR

IGBTs are a natural evolution of the vertical Power MOSFETs for high current, high voltage applications and fast end-equipment. This device eliminates the main disadvantage of current high voltage power MOSFETs characterized by an high value of RDS(on) caused by the high resistivity of the source-drain path necessary to obtain a high breakdown voltage BVDSS. The power conduction losses at high current levels are considerably less in IGBT technology even when compared with the latest generation of Power MOSFET devices that have been greatly improved in terms of RDS(on). The lower voltage drop,

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translated into a low VCE(sat), together with the device’s structure allow a higher current density than a standard bipolar device simplifying the IGBTs driver schematic as well. The vertical section depicted in figure 1 together with the equivalent circuit shows IGBTs basic structure.

3. TURN-ON.

The structure of the silicon die is evidently similar to that of a Power MOSFET with the fundamental difference of the addition of a P+ substrate and an N+ buffer layer (absent in NPT-non-punch-through- IGBT technology). This is represented in the equivalent schematic (figure 1), with a MOSFET driving two bipolar devices. The presence of the substrate creates a junction J1 between the P+ and the N zone of the body.

When the positive gate bias allows the inversion of the P base region under the gate, an N channel is created, with a flow of electrons, generating a current in the exact same way as a Power MOSFET. If the voltage caused by this flux is in the range of 0.7V, then J1 is forward biased and some holes are injected in the N- region, modulating the resistance between anode and cathode, in this way decreasing the overall power conduction losses and a second flow of charges starts.

The final result is the contemporary presence of two different typologies of current inside the semiconductor’s layers:

-an electron flux (MOSFET current);

-a hole current (bipolar).

The typical waveforms with an inductive load are reported in figure 2.

Figure 2: Typical Waveforms During Turn-On

VCC

Vge

L

O

A VCE

D

IC

gnd

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4. TURN-OFF.

When a negative bias is applied to the gate or the gate voltage falls below the threshold value, the channel is inhibited and no holes are injected in the N- region. In any case even if the MOSFET current decreases rapidly in the switching off phase, the collector current gradually reduces because there are minority carriers still present in the N layer, immediately after the start of commutation. The decrease in value of this residual current (tail) is strictly dependent on the density of these charges in turn-off that is linked to several factors as the amount of dopant, dopant typology, layers’ thickness and temperature.

The minority carrier’s density decay gives the characteristic tail shape (reported in figure 3) to the collector current that is responsible for:

-an increase in power losses;

-cross conduction problems, in peculiar appliances where the free-wheeling diodes are used.

Figure 3: Typical Waveforms During Turn-Off

	Vge
V	IC
CE

Considering that the tail current is linked to the minority carrier’s recombination its value and shape are strictly related to the holes’ mobility strictly related to the temperature reached by the die, IC and VCE. So depending on the temperature reached, it is possible to reduce the undesirable effect of this current acting on the end equipment design, as indicated in the graphs below, where the tail current (Itail) behavior related to VCE, IC, and TC is depicted (figure 4).

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Figure 4: Itail Dependance From IC, TC, and VCE
Itail	(A)						Itail	(A)
8							4
7							3.5
6							3
5							2.5
4				Tc = 100°C			2				Tc = 100°C
3							1.5
				Vce = 400V							Ic = 10A
2							1
				Rg = 100Ω							Rg = 100Ω
1							0.5
0				Vge = 15V			0				Vge = 15V
0	5	10	15	20	25		0	100	200	300	400	500
		IC (A)		Itail	(A)				VCE (V)
				4
				3.5
				3
				2.5
				2				Vce=400°C
				1.5
								Ic = 10A
				1
								Rg = 100Ω
				0.5
								Vge = 15V
				0
				0	25	50	75	100	125
							TC (°C)

5. REVERSE BLOCKING.

When a negative voltage is applied to the collector then J1 is reverse biased and the depletion layer expands to the N- region. This mechanism is fundamental because an excessive reduction of this layer’s thickness does not obtain a valid blocking capability. On the other hand increasing the dimension of this region too much consistently elevates the voltage drop.

This second option explains clearly why NPT devices have a higher voltage drop when compared with an equivalent (equal IC and speed) PT part.

6. FORWARD BLOCKING.

When gate and emitter are shorted and a positive voltage is applied to the collector terminal the P/N- the J3 junction is reverse biased. Again it is the depletion layer in the N- drift region that withstands the voltage applied.

7. LATCH UP.

IGBTs contains a parasitic PNPN thyristor between the collector and the emitter, as evidenced in figure 1. Under particular conditions this parasitic device enters in turn on. This causes an increase in the current flowing between emitter and collector, a lose of control of the equivalent MOSFET and generally the disruption of the component. The turn-on of the thyristor is known as latch up of the IGBT, more in detail

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the causes of this failure are different and strictly dependent on the status of the device.

In general a static and a dynamic latch up are distinguished by the following:

-Static latch up happens when the device is in full conduction.

-Dynamic latch up takes place only during turn-off. This peculiar phenomenon strongly limits the safe operating area.

In order to avoid this dangerous effect of the parasitic NPN and PNP transistors it is necessary:

-to prevent the turn-on of the NPN part, modifying both the layout and doping level;

-to reduce the overall current gain of the NPN and PNP transistors.

Furthermore the latching current is strictly dependent on the junctions’ temperature since it affects the current gains of PNP and NPN parts; moreover with an increase of temperature, together with the gains, the resistance of the P base region becomes higher, aggravating the overall behavior. So particular attention must be paid by the manufacturer of the parts in order keep distant the maximum collector current value to the one of the latching current. In general the ratio is in the order of 1 to 5.

8. FORWARD CONDUCTION CHARACTERISTICS.

Figure 5: Forward Characteristics And Equivalent Schematic Operation

Ice (A)

C	10
	8
	6
	4
	2
	0
	0	0.6	1	1.5	2	2.5	3	3.5	4	4.5	5

VCE (V)

	3.5	VCE(sat) (V)
G	3
	2.5
	2
	1.5
E	1
	0.5
	0	0	5	10	15	20	IC (A)

The IGBT in conduction can be modeled, as a first approximation, as a PNP transistor driven by a Power MOSFET. Figure 5 only shows the elements of the structure necessary for the understanding of physic the device in operation (parasitic elements are not considered).

As showed in the graph reporting IC as a function of VCE (static characteristic), the collector current IC does not flow if the voltage drop between anode and cathode does not exceed 0.7V even if the gate signal allows the formation of the MOSFET channel, as evidenced in the graphs.

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