ST AN1485 APPLICATION NOTE
AN1485
APPLICATION NOTE
MDmesh™ PERFORMANCE EVALUATION IN A
CONTINUOUS MODE PFC BOOST CONVERTER
G. Belverde - M. Melito - A. Raciti - M. Saggio - S. Musumeci
1. ABSTRACT
A new high voltage MOSFET structure is presented which results in static as well as dynamic
performances far ahead conventional Power MOSF ET devices. The impact of the particular features of
the device is analyzed and quant ified in a c ase stu dy regarding a DC-DC boost conv erter, which is used
in a power factor corrector (PFC) converter. Results obtained from the analysis of the electrical and
thermal behavior of the component in the specific are discussed.
2. INTRODUCTION.
Standard technology for high voltage suited Power MOSFETs has been dramatically improved, thus the
physical limit in terms of reduction of the device’s on-state resistance is going to be reached. In fact, such
a device parameter is strongly affected by the drain resistivity value, which is designed according to the
requirements of the high v oltage blocking capability. Recently, an innovative concept of Power M OS FET
design has been proposed that is able to enhance t he dev ice’s performance [1 , 2]. In these new devices
the charge balance makes the electric field constant over the whole drain volume in spite of t he low
resistivity in this conducting region. In breakdown conditions the electric field has a value almost equal to
the critical one for silicon.
In this paper the main issues of process technology are shortly recalled and discussed. The static and
dynamic characteristics are shown aiming to evaluate the advantages of the new device in comparison to
standard Power MOSFETs having both the same rated voltage and current carrying capability. Finally,
the evaluation of the performance is foc used on in a spec ific application, in particular in a bo ost-based
power factor corrector (PFC) converter.
3. TRENDS ON POWER MOSFET (MDmesh™) DEVICE TECHNOLOGY .
A revolutionary three-dimensional design of the drain device volume is at the basis of the MDmesh™
MOSFET device. The extensio n of the top strip layout to the whole drain volume, by p-doped column
insertion under device stripes, allows a strong resistivity reduction of the c onduction n-doped layer and
an impressive decrease of the device’s on-state resistance when com pared to a convent ional MOSFE T
[1]. The cross section of an MDmesh™ device is depicted in figure 1, where both the strip layout and the
column insertion under the de vice stripes are shown. As a consequence of this approach, the known
theoretical limit of performanc e for vertical Power MOS FET devices decreases. I n fact, the MDmesh™
MOSFET overcomes this limit allowing a mass production of devices with improved perform ance and
reduced area. For example, a 500V MDmesh™ MOSFET is almost three times smaller than a
conventional MOSFET having the same blockin g voltage.
November 2001
1/14
AN1485 - APPLICATION NOTE
SUBSTRATE
DRAIN
10
Vgs=10V
Figure 1: Three-Dimensional Cross Section Of MDmes h™ Device
N-SOURCE
P-MESH
GAT E
FINGER
BACK METAL
The static output characteristics o f a n M Dme sh ™ MO SF ET i n c om parison to a s tandard dev ice wit h the
same silicon area a re reported in figure 2. Moreover, simulation anal ysis and theoretical consi derations
show that in MDmesh™ t echnology the device’s on-state resistance increases linearly as funct ion of t he
breakdown voltage, according to the traces shown in figure 3. The direct consequenc e of this result is
that the extension of the M Dmesh™ MOSFETs towards higher blocking voltage values will continually
increase the advantages of this technology . The fabrication of a 1000V MDmesh™ MOSFET will require,
as expected from the design, a silicon area seven (7) times smaller than a conventional M OSFET with
the same on-state resistance and blocking voltage capability. This will cause a package reduction and a
major improvement in any appli cation based on these devices, as c onsequenc e of the st rong reduction
obtained on volume and weight of the board. The extension to very high blocking voltage of MDmesh™
MOSFETs will represent a real revolution in high voltage converter applications.
Figure 2: Static Output Characteristics (I/V Curves) Of An MDmesh™ (STP12NM50) And A
St andard MO S FET Having Equal Si l icon Area
18
16
14
MDmesh™
Std Technology
12
10
Ids (A)
8
6
4
Vgs=6V
2
0
0123456789
Vds(V)
2/14
AN1485 - APPLICATION NOTE
Figure 3: Standard MOSFET and MDmesh™ Depend ence Of On-State Resistance As A Function
Of The Breakdown Voltage
1000
1000
t
t
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T
T
E
E
]
]
2
2
o
o
i
100
100
Ron Area [mΩ cm
Ron Area [mΩ cm
10
10
100 1000
100 1000
i
t
t
n
n
e
e
v
v
n
n
o
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M
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Breakdown Voltag e [V]
Breakdown Voltag e [V]
Another important feature obtained b y the proposed approach reduction of the intrinsic c apacitances [3],
in comparison to the one of a more t raditional device, as seen in table 1. In switch m ode power supply
(SMPS) and PFC applications the reduction of the intrinsic parasitic capacitance allows a com mutation
time decrease, thus enabling the increase of the switching frequency. As known, this will result in
important reduction of both volume and cost of the reactive components used to filter the output and/or
electrical quantities.
Table 1. Main Characteristics Comparison
Part Number BV
DSS
[V]
R
DS(on)
[Ohm]
@ 25°C
Ciss
[pF]
Coss
[pF]
Crss
[pF]
Package
Standard STW15NB50 >500 0.36 2600 330 40 TO-247
MDmesh™ STP12NM50 >500 0.38 1000 160 25 TO-220
4. SWITCHING CHARACTERISTICS.
A characterization of the new device has been carried out in order to give evidence to the good switching
performance of the new de vice. The silic on area shrin king allowed by the M D m esh™ techn ology ad ds a
further benefit to the device’s gate charge due to the parasitic capacitance reduction. Th e gate charge
comparison of figure 4 refers to two devices with equal rated electrical characteristics. At the driving
voltage of 10V the MDmesh™ requires a gate charge reduced by a factor of 3.5 in respect to the
traditional counterpart, at a drain current of 12A and a drain-source voltage of 200V. The charge stored in
the input capacitance is reduced from 50nC (STW15NB50) t o 25nC (STP12NM50). This immediately
suggests to the end-user an effective driving loss reduction. Moreover, as a consequence, this feature
allows an improvement of the performance during the switching transients in comparison with
conventional devi ces [4 ].
3/14
AN1485 - APPLICATION NOTE
The switching transient evaluation has been performed at room temperature on inductive load at several
gate-driving conditions. The main quantities of a typical c ommutation, in hard switching conditions on
inductive load, are reported in table 2, while in figure 5 the traces of an experimental turn-off switching
transients are shown.
Figure 4: Gate Charge Behavior Of Two Different Power MOSFET Devices
Gate Charge
15
10
(V)
GS
V
STP12NM50
5
STW14NB50
0
0 10 20 30 40 50 60
Charge [nC]
Table 2. MDmesh™ Typical Switching Quantities (RG=4.7Ohm)
E
off
[µJ]
28.6 10.8 7.6 888.9 36.84 33.6
t
fall
[ns]
t
rise
[ns]
di/dt
[A/ns]
dv/dt
[V/ns]
t
delay
[ns]
4/14
AN1485 - APPLICATION NOTE
Figure 5: Current And Voltage Traces During A Typical Turn-Off Transient Of An MDmesh™
(V
=100V/div, VGS=10V/div, ID=5A/div, t=20ns/div)
DS
5. INTRINSIC BODY-DRAIN DIODE.
In some industrial equipment, which requires a conv erter configuration with bi-directional switches, the
intrinsic diode of the MOSFET device may be used as antiparallel diode if its own characteristics are
adequate. In order to optimize the design, the performance of the body-drain diode of the new device has
been investigated. In particular, the switching behavior of t he body-drain diode has bee n widely tested.
The well-established technique of Platinum implanting has been performed in order to reduce the reverse
recovery time (t
) of the body-drain diode b y reducing the carrier lifetime. Platinum implanting a cts as a
rr
lifetime killer by introducing a mi d gap center in the silicon. By increasing the Platinum dose ( Φ) a t
reduction is observed. The obtained experimental waveforms during a reverse recovery transient for
three devices with different Platinum doses are reported in figure 6 that is related to a current slope di/dt
equal to 100A/ms.
Figure 6: Reverse Recovery Of The Body-Drain Diode In Case Of Different Platinum Doses
(ID=5A/div, t=100ns/div)
Vds=100V, di/dt=100A/µs, Id=12A
Φ1 < Φ2
Φ2
Id (A)
Φ1
rr
BV
DSS
=600V
No lifetime killer
100ns/div
5/14
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