ST AN1451 APPLICATION NOTE

AN1451

APPLICATION NOTE

L6208 FULLY INTEGRATED TWO PHASE

STEPPER MOTOR DRIVER

by Domenico Arrigo, Vincenzo Marano and Thomas Hopkins

Modern motion control applications need more flexibility that can be addressed only with specialized IC products. The L6208 is a fully integrated stepper motor driver IC specifically developed to drive a wide range of two phase (bipolar) stepper motors. This IC is a one-chip cost effective solution that includes several unique circuit design features. These features, including a decoding logic that can generate three different stepping sequences, allow the device to be used in many applications including microstepping. The principal aim of this development project was to produce an easy to use, fully protected power IC. In addition several key functions such as protection circuit and PWM current control drastically reduce external components count to meet requirements for many different applications.

1 INTRODUCTION

The L6208 is a highly integrated, mixed-signal power IC that allows the user to easily design a complete motor control system for two-phase bipolar stepper motors. Figure 1 shows the L6208 block diagram. The IC integrates eight Power DMOS, a centralized logic circuit which implements the phase generation and a constant tOFF PWM current control technique (Quasi-Synchronous mode) for each of the two phases of the motor plus other added features for safe operation and flexibility.

Figure 1. L6208 block diagram.

	VBOOT	VBOOT
	VCP	CHARGE	THERMAL
		PUMP	PROTECTION
			OCDA
			OCDB

EN

CONTROL

HALF/FULL

CLOCK STEPPING

RESET

SEQUENCE

GENERATION

CW/CCW

VOLTAGE

GND REGULATOR

GND

GND

10V 5V

GND

L6208

VBOOT		VBOOT		VSA
OVER
CURRENT
DETECTION				OUT1A
10V		10V		OUT2A
GATE
LOGIC
				SENSEA
	PWM
ONE SHOT	MASKING		+
MONOSTABLE	TIME	SENSE	-	VREFA
		COMPARATOR
		BRIDGE A		RCA
OVER				VSB
				OUT1B
CURRENT
DETECTION				OUT2B
GATE				SENSEB
LOGIC				VREFB
		BRIDGE B		RCB

D01IN1226

October 2003

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AN1451 APPLICATION NOTE

Table of Contents

1	INTRODUCTION................................................................................................................................			1
2 DESIGNING AN APPLICATION WITH L6208 ...................................................................................				3
	2.1	Current Ratings ........................................................................................................................		3
	2.2	Voltage Ratings and Operating Range ....................................................................................		3
	2.3	Choosing the Bulk Capacitor....................................................................................................		5
	2.4	Layout Considerations .............................................................................................................		6
	2.5	Sensing Resistors ....................................................................................................................		8
	2.6	Charge pump external components .........................................................................................		9
	2.7	Sharing the Charge Pump Circuitry .......................................................................................		10
	2.8	Reference Voltage for PWM Current Control.........................................................................		11
	2.9	Input Logic pins ......................................................................................................................		12
	2.10	EN pin ....................................................................................................................................		12
	2.11	Programmable off-time Monostable ......................................................................................		13
	2.11.1 Off-time Selection and minimum on-time ........................................................................			15
	2.11.2 Decay Modes ..................................................................................................................			16
	2.12	Over Current Protection ........................................................................................................		18
	2.13	Power Management ..............................................................................................................		21
	2.13.1 Maximum output current vs. selectable devices..............................................................			22
	2.13.2 Power Dissipation Formulae for different sequences ......................................................			22
	2.14	Choosing the Decay Mode....................................................................................................		25
	2.15 Choosing the Stepping Sequence.........................................................................................			26
	2.16	Microstepping........................................................................................................................		27
3	APPLICATION EXAMPLE................................................................................................................			30
	3.1	Decay mode, sensing resistors and reference voltage. .........................................................		30
4	APPENDIX - EVALUATION BOARDS .............................................................................................			31
	4.1	PractiSPIN..............................................................................................................................		31
	4.2	EVAL6208N ...........................................................................................................................		33
	4.2.1		Important Notes ................................................................................................................	34
	4.2.2		Thermal Impedance .........................................................................................................	34
	4.3	EVAL6208PD .........................................................................................................................		38
	4.3.1		Important Notes ................................................................................................................	39
	4.3.2		Thermal Impedance .........................................................................................................	39
5	REFERENCES.................................................................................................................................			43

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AN1451 APPLICATION NOTE

2 DESIGNING AN APPLICATION WITH L6208

2.1 Current Ratings

With MOSFET (DMOS) devices, unlike bipolar transistors, current under short circuit conditions is, at first approximation, limited by the RDS(ON) of the DMOS themselves and could reach very high values. L6208 Out pins and the two VSA and VSB pins are rated for a maximum of 2.8A r.m.s. and 5.6A peak (typical values), corresponding to a total (for the whole IC) 5.6A rms (11.2A peak). These values are meant to avoid damaging metal structures, including the metallization on the die and bond wires. In practical applications, though, maximum allowable current is less than these values, due to power dissipation limits (see Power Management section). The device has a built-in Over Current Detection (OCD) that provides protection against short circuits between the outputs and between an output and ground (see Over Current Protection section).

2.2 Voltage Ratings and Operating Range

The L6208 requires a single supply voltage (VS), for the motor supply. Internal voltage regulators provide the 5V and 10V required for the internal circuitry. The operating range for VS is 8 to 52V. To prevent working into undesirable low supply voltage an Under Voltage Lock Out (UVLO) circuit shuts down the device when supply voltage falls below 6V; to resume normal operating conditions, VS must then exceed 7V. The hysteresis is provided to avoid false intervention of the UVLO function during fast VS ringings. It should be noted, however, that DMOS's RDS(ON) is a function of the VS supply voltage. Actually, when VS is less than 10V, RDS(ON) is adversely affected, and this is particularly true for the High Side DMOS that are driven from VBOOT supply. This supply is obtained through a charge pump from the internal 10V supply, which will tend to reduce its output voltage when VS goes below 10V. Figure 2 shows the supply voltage of the high side gate drivers (VBOOT - VS) versus the supply voltage (VS).

Figure 2. High side gate drivers supply voltage versus supply voltage.

	8
	7 .6
VBOOT - VS	7 .2
[V]	6 .8
	6 .4
	6
	8	8 .5	9	9 .5	1 0	1 0 .5
				VS [V]

Note that VS must be connected to both VSA and VSB since the bootstrap voltage (at VBOOT pin) is the same for the two H-bridges. The integrated DMOS have a rated Drain-Source breakdown voltage of 60V. However VS should be kept below 52V, since in normal working conditions the DMOS see a Vds voltage that will exceed VS supply. In particular, when using the fast decay mode, at the beginning of the off-time (when all the DMOS are off during dead-time) the SENSE pin sees a negative spike due to a not negligible parasitic inductance of the PCB path from the pin to GND. This spike is followed by a stable negative voltage due to the drop on RSENSE. One of the two OUT pins of the bridge sees a similar behavior, but with a slightly larger voltage due to the forward recovery time of the integrated freewheeling diode and the forward voltage drop across it (see Figure 3). Typical duration of this spike is 30ns. At the same time, the other OUT pin of the same bridge sees a voltage

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AN1451 APPLICATION NOTE

above VS, due to the PCB inductance and voltage drop across the high-side (integrated) freewheeling diode, as the current reverses direction and flows into the bulk capacitor. It turns out that, in fast decay, the highest differential voltage is observed between the two OUT pins of the same bridge, at the beginning of the off-time, and this must always be kept below 60V [3]. The same high voltage condition exists when a step is made and the direction of current flow reverses in the bridge.

Figure 3. Currents and voltages during the dead time at the beginning of the off-time.

Bulk Capacitor

Equivalent Circuit

	PCB Parasitic
ESR	Inductance
ESL

VS

OUT2

RSENSE*I+VF(Diode) OUT1

		Dangerous	VS+VF(Diode)
RSENSE*I	High Differential Voltage
	SENSE
	RSENSE	PCB Parasitic
		Inductance

Figure 4 shows the voltage waveforms at the two OUT pins referring to a possible practical situation, with a peak output current of 2.8A, VS = 52V, RSENSE = 0.33Ω, TJ = 25°C (approximately) and a good PCB layout. Below ground spike amplitude is -2.65V for one output; the other OUT pin is at about 57V. In these conditions, total differential voltage reaches almost 60V, which is the absolute maximum rating for the DMOS. Keeping differential voltage between two Output pins belonging to the same Full Bridge within rated values is a must that can be accomplished with proper selection of Bulk capacitor value and equivalent series resistance (ESR), according to current peaks and chopping style and adopting good layout practices to minimize PCB parasitic inductances (see below) [3].

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Figure 4. Voltage at the two outputs at the beginning of the off-time.

Out 1

Out 2

2.3 Choosing the Bulk Capacitor

Since the bulk capacitor, placed between VS and GND pins, is charged and discharged during IC operation, its AC current capability must be greater than the r.m.s. value of the charge/discharge current. This current flows from the capacitor to the IC during the on-time (tON) and from the IC (in fast decay; from the power supply in slow decay) to the capacitor during the off-time (tOFF). The r.m.s. value of the current flowing into the bulk capacitor depends on peak output current, output current ripple, switching frequency, duty-cycle and chopping style. It also depends on power supply characteristics. A power supply with poor high frequency performances (or long, inductive connections to the IC) will cause the bulk capacitor to be recharged slowly: the higher the current control switching frequency, the higher the current ripple in the capacitor; r.m.s. current in the capacitor, however, does not exceed the r.m.s. output current. Bulk capacitor value (C) and the ESR determine the amount of voltage ripple on the capacitor itself and on the IC. In slow decay, neglecting the dead-time and output current ripple, and assuming that during the on-time the capacitor is not recharged by the power supply, the voltage at the end of the on-time is:

V		– I			tON
	S		OUT		× ESR + -------- ,
					C
so the supply voltage ripple is:
	I				tON
		OUT		× ESR + -------- ,
					C

where IOUT is the output current. With fast decay, instead, recirculating current recharges the capacitor, causing the supply voltage to exceed the nominal voltage. This can be very dangerous if the nominal supply voltage is close to the maximum recommended supply voltage (52V). In fast decay the supply voltage ripple is about:

I × 2 × ESR tON + tOFF ,

OUT + ---------------------------

C

always assuming that the power supply does not recharge the capacitor, and neglecting the output current ripple and the dead-time. Usually (if C > 100 µF) the capacitance role is much less than the ESR, then supply voltage ripple can be estimated as:

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AN1451 APPLICATION NOTE

IOUT · ESR in slow decay

2 · IOUT · ESR in fast decay

For Example, if a maximum ripple of 500mV is allowed and IOUT = 2A, the capacitor ESR should be lower than:

0.5V
ESR < ------------ = 250mW in slow decay, and
2A
1	0.5V	= 125mW in fast decay.
ESR < -- ×	------------
2	2A

Actually, current sunk by VSA and VSB pins of the device is subject to higher peaks due to reverse recovery charge of internal freewheeling diodes. Duration of these peaks is, tough, very short, and can be filtered using a small value (100÷200 nF), good quality ceramic capacitor, connected as close as possible to the V SA, VSB and GND pins of the IC. Bulk capacitor will be chosen with maximum operating voltage 25% greater than the maximum supply voltage, considering also power supply tolerances. For example, with a 48V nominal power supply, with 5% tolerance, maximum voltage is 50.4V, then operating voltage for the capacitor should be at least 63V.

2.4 Layout Considerations

Working with devices that combine high power switches and control logic in the same IC, careful attention has to be paid to the PCB layout. In extreme cases, Power DMOS commutation can induce noises that could cause improper operation in the logic section of the device. Noise can be radiated by high dv/dt nodes or high di/dt paths, or conducted through GND or Supply connections. Logic connections, especially high-impedance nodes (actually all logic inputs, see further), must be kept far from switching nodes and paths. With the L6208, in particular, external components for the charge pump circuitry should be connected together through short paths, since these components are subject to voltage and current switching at relatively high frequency (600kHz). Primary mean in minimizing conducted noise is working on a good GND layout (see Figure 5).

Figure 5. Typical Application and Layout suggestions.

2-Phase Stepper Motor

D1

D2

C8

			C5
			R4
		OUT1A OUT2AOUT1B OUT2B	VBOOT	CP	VSA	VSB
+						SENSEA				+
		CW / CCW				SENSEB	R5	R6
Logic Supply	µC	CONTROL
	or	RESET	L6208					C6	C7	VS = 8 ÷ 52 V
3.3 ÷ 5 V	Custom Logic

-	HALF / FULL
	CLOCK				-
	EN
	R1
	VrefA	VrefB	RCA	RCB	GND GND GND GND
	C1
			C3		C4
	C2		R2	R3

Vref = 0 ÷1V

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AN1451 APPLICATION NOTE

High current GND tracks (i.e. the tracks connected to the sensing resistors) must be connected directly to the negative terminal of the bulk capacitor. A good quality, high-frequency bypass capacitor is also required (typically a 100nF÷200nF ceramic would suffice), since electrolytic capacitors show a poor high frequency performance. Both bulk electrolytic and high frequency bypass capacitors have to be connected with short tracks to VSA, VSB and GND. On the L6208 GND pins are the Logic GND, since only the quiescent current flows through them. Logic GND and Power GND should be connected together in a single point, the bulk capacitor, to keep noise in the Power GND from affecting Logic GND. Specific care should be paid layouting the path from the SENSE pins through the sensing resistors to the negative terminal of the bulk capacitor (Power Ground). These tracks must be as short as possible in order to minimize parasitic inductances that can cause dangerous voltage spikes on SENSE and OUT pins (see the Voltage Ratings and Operating Range section); for the same reason the capacitors on VSA, VSB and GND should be very close to the GND and supply pins. Refer to the Sensing Resistors section for information on selecting the sense resistors. Traces that connect to VSA, VSB, SENSEA, SENSEB, and the four OUT pins must be designed with adequate width, since high currents are flowing through these traces, and layer changes should be avoided. Should a layer change prove necessary, multiple and large via holes have to be used. A wide GND copper area can be used to improve power dissipation for the device.

Figure 6 shows two typical situations that must be avoided. An important consideration about the location of the bulk capacitors is the ability to absorb the inductive energy from the load, without allowing the supply voltage to exceed the maximum rating. The diode shown in Figure 6 prevents the recirculation current from reaching the capacitors and will result in a high voltage on the IC pins that can destroy the device. Having a switch or a power connection that can disconnect the capacitors from the IC, while there is still current in the motor, will also result in a high voltage transient since there is no capacitance to absorb the recirculation current.

Figure 6. Two situations that must be avoided.

VSA	VSB
	SENSEA
L6208	SENSEB
	R5
	C6	C7
GND GND	GND GND

DON’T put a diode here!

Recirculating current cannot flow into the bulk capacitor and causes a high voltage spike that can destroy the IC.

+

VS = 8 ÷ 52 V

-

DON’T connect the Logic GND here

Voltage drop due to current in sense path can disturb logic GND.

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2.5 Sensing Resistors

Each motor winding current is flowing through the corresponding sensing resistor, causing a voltage drop that is used, by the logic, to control the peak value of the load current. Two issues must be taken into account when choosing the RSENSE value:

–The sensing resistor dissipates energy and provides dangerous negative voltages on the SENSE pin during the current recirculation. For this reason the resistance of this component should be kept low.

–The voltage drop across RSENSE is compared with the reference voltage (on Vref pin) by the internal comparator. The lower is the RSENSE value, the higher is the peak current error due to noise on Vref pin and to the input offset of the current sense comparator: too small values of RSENSE must be avoided.

A good compromise is calculating the sensing resistor value so that the voltage drop, corresponding to the peak current in the load (Ipeak), is about 0.5 V: RSENSE = 0.5 V / Ipeak.

It should be clear that sensing resistor must absolutely be non-inductive type in order to avoid dangerous negative spikes on SENSE pins. Wire-wounded resistors cannot be used here, while Metallic film resistors are recommended for their high peak current capability and low inductance. For the same reason the connections between the SENSE pins, C6, C7, VSA, VSB and GND pins (see Figure 5) must be taken as short as possible (see also the Layout Considerations section).

The average power dissipated by the sensing resistor is:

Fast Decay Recirculation: PR ≈ Irms2 · RSENSE

Slow Decay Recirculation: PR ≈ Irms2 · RSENSE · D,

D is the duty-cycle of the PWM current control, Irms is the r.m.s. value of the load current.

Nevertheless, sensing resistor power rating should be chosen taking into account the peak value of the dissipated power:

PR » Ipk2 × RS ENSE ,

where Ipk is the peak value of the load current.

Using multiple resistors in parallel will help obtaining the required power rating with standard resistors, and reduce the inductance.

RSENSE tolerance reflects on the peak current error: 1% resistors should be preferred.

The following table shows RSENSE recommended values (to have 0.5V drop on it) and power ratings for typical examples of current peak values.

Ipk	RSENSE Value [W]	RSENSE Power Rating [W]	Alternatives
0.5	1	0.25
1	0.5	0.5	2 X 1W, 0.25W paralleled
1.5	0.33	0.75	3 X 1W, 0.25W paralleled
2	0.25	1	4 X 1W, 0.25W paralleled

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2.6 Charge pump external components

An internal oscillator, with its output at CP pin, switches from GND to 10V with a typical frequency of 600kHz (see Figure 7).

Figure 7. Charge Pump.

V S + 10 V - V D 1 - V D 2 f = 600 kH z

V S + 10 V - V D 1

V S - V D 1

				C8
D 1		D 2
	C 5
	R 4
V B O OT	CP	V SA	V S B
T o H igh -Side		10 V		C h arge Pu mp
G ate D r ivers		RD S(O N ) = 70Ω		O scillator

10 V

5 V

10 V

RDS (ON ) = 70Ω

f = 600 kHz

L 6208

When the oscillator output is at ground, C5 is charged by VS through D2. When it rises to 10V, D2 is reverse biased and the charge flows from C5 to C8 through D1, so the VBOOT pin, after a few cycles, reaches the maximum voltage of VS + 10V - VD1 - VD2, which supplies the high-side gate drivers.

With a differential voltage between VS and VBOOT of about 9V and both the bridges switching at 50kHz, the typical current drawn by the VBOOT pin is 1.85 mA.

Resistor R4 is added to reduce the maximum current in the external components and to reduce the slew rate of the rising and falling edges of the voltage at the CP pin, in order to minimize interferences with the rest of the circuit. For the same reason care must be taken in realizing the PCB layout of R4, C5, D1, D2 connections (see also the Layout Considerations section). Recommended values for the charge pump circuitry are:

D1, D2	: 1N4148
R4	: 100 Ω (1/8 W)
C5	: 10nF 100V ceramic
C8	: 220nF 25V ceramic

Due to the high charge pump frequency, fast diodes are required. Connecting the cold side of the bulk capacitor (C8) to VS instead of GND the average current in the external diodes during operation is less than 10 mA (with R4 = 100 Ω); at startup (when VS is provided to the IC) is less than 200 mA while the reverse voltage is about 10 V in all conditions. 1N4148 diodes withstand about 200 mA DC (1 A peak), and the maximum reverse voltage is 75 V, so they should fit for the majority of applications.

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2.7 Sharing the Charge Pump Circuitry

If more than one device is used in the application, it's possible to use the charge pump from one L6208 to supply the VBOOT pins of several ICs. The unused CP pins on the slaved devices are left unconnected, as shown in Figure 8. A 100nF capacitor (C8) should be connected to the VBOOT pin of each device.

Supply voltage pins (VS) of the devices sharing the charge pump must be connected together.

The higher the number of devices sharing the same charge pump, the lower will be the differential voltage available for gate drive (VBOOT - VS), causing a higher RDS(ON) for the high side DMOS, so higher dissipating power. In this case it's recommended to omit the resistor on the CP pin, obtaining a higher current capability of the charge pump circuitry.

Better performance can also be obtained using a 33nF capacitor for C5 and using schottky diodes (for example BAT47 are recommended).

Sharing the same charge pump circuitry for more than 3÷4 devices is not recommended, since it will reduce the VBOOT voltage increasing the high-side MOS on-resistance and thus power dissipation.

Figure 8. Sharing the charge pump circuitry.

To other Devices

C18 = 100 nF

D1 = BAT47

D2 = BAT47

C8 = 100nF

C5 = 33nF

VBOOT

CP

VSA

VSB

VBOOT

CP

VSA

VSB

To High-Side

To High-Side

Gate Drivers

Gate Drivers

L6208

L6208

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AN1451 APPLICATION NOTE

2.8 Reference Voltage for PWM Current Control

The device has two analog inputs, VrefA and VrefB, connected to the internal sense comparators, to control the peak value of the motor current through the integrated PWM circuitry. In typical applications these pins are connected together, in order to obtain the same current in the two motor windings (one exception is the microstepping operation; see the related section). A fixed reference voltage can be easily obtained through a resistive divider from an available 5 V voltage rail (maybe the one supplying the µC or the rest of the application) and GND.

A very simple way to obtain a variable voltage without using a DAC is to low-pass filter a PWM output of a µC (see Figure 9).

Assuming that the PWM output swings from 0 to 5V, the resulting voltage will be:

V 5V × Dμ C × RDIV

ref = ----------------------------------------

RLP + RDIV

where DµC is the duty-cycle of the PWM output of the µC.

Assuming that the µC output impedance is lower than 1kW, with RLP = 56kW, RDIV = 15kW, CLP = 10nF and a µC PWM switching from 0 to 5V at 100kHz, the low pass filter time constant is about 0.12 ms and the remaining

ripple on the Vref voltage will be about 20 mV. Using higher values for RLP, RDIV and CLP will reduce the ripple, but the reference voltage will take more time to vary after changing the duty-cycle of the µC PWM, and too high values of RLP will also increase the impedance of the Vref net at low frequencies, causing a poor noise immunity.

As sensing resistor values are typically kept small, a small noise on Vref input pins might cause a considerable error in the output current. It's then recommended to decouple these pins with ceramic capacitors of some tens of nF, placed very close to Vref and GND pins. Note that Vref pins cannot be left unconnected, while, if connected to GND, zero current is not guaranteed due to voltage offset in the sense comparator. The best way to cut down (IC) power consumption and clear the load current is pulling down the EN pin. In slow decay, with very small reference voltage, PWM integrated circuitry can loose control of the current due to the minimum allowed duration of tON (see the Programmable off-time Monostable section).

Figure 9. Obtaining a variable voltage through a PWM output of a µC.

PWM Output	RLP
of a µC

Vref

RDIV				CLP

GND

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AN1451 APPLICATION NOTE

2.9 Input Logic pins

CW/CCW, CONTROL, RESET, HALF/FULL, CLOCK are CMOS/TTL compatible logic input pins. The input comparator has been realized with hysteresis to ensure the required noise immunity. Typical values for turn-on and turn-off thresholds are Vth,ON = 1.8V and Vth,OFF = 1.3V. Pins are ESD protected (see Figure 10) (2kV human-body electrostatic discharge), and can be directly connected to the logic outputs of a µC; a series resistor is generally not recommended, as it could help inducted noise to disturb the inputs. All logic pins enforce a specific behavior and cannot be left unconnected.

Figure 10. Logic input pins.

CONTROL,	5 V
HALF/FULL, CLOCK,
RESET, CW/CCW
ESD
Protection

2.10 EN pin

The EN pin is, actually, bi-directional: as an input, with a comparator similar to the other logic input pins (TTL/CMOS with hysteresis), it controls the state of the PowerDMOS. When this pin is at a low logic level, all the PowerDMOS are turned off. The EN pin is also connected to the open drain output of the protection circuit that will pull the pin to GND if over current or over temperature conditions exist. For this reason, EN pin must be driven through a series resistor of 2.2kΩ minimum (for 5V logic), to allow the voltage at the pin to be pulled below the turn-off threshold.

A capacitor (C1 in Figure 5) connected between the EN pin and GND is also recommended, to reduce the r.m.s. value of the output current when overcurrent conditions persist (see Over Current Protection section). EN pin must not be left unconnected.

Figure 11. EN input pin.

5 V

EN

ESD

Protection

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AN1451 APPLICATION NOTE

2.11 Programmable off-time Monostable

The L6208 includes a constant off time PWM current controller for each of the two bridges. The current control circuit senses the bridge current by sensing the voltage drop across an external sense resistor connected between the source of the two lower power MOS transistors and ground, as shown in Figure 12. As the current in the motor builds up the voltage across the sense resistor increases proportionally. When the voltage drop across the sense resistor becomes greater than the voltage at the reference input (VREFA or VREFB) the sense comparator triggers the monostable switching the bridge off. The power MOS remain off for the time set by the monostable and the motor current recirculates as defined by the selected decay mode, described in the next section. When the monostable times out the bridge will again turn on. Since the internal dead time, used to prevent cross conduction in the bridge, delays the turn on of the power MOS, the effective off time is the sum of the monostable time plus the dead time.

Figure 12. PWM Current Controller Simplified Schematic

						VSA (or B)
	TO GATE LOGIC	BLANKING TIME	1 s	FROM THE
		MONOSTABLE
				LOW-SIDE
				GATE DRIVERS
5mA					2H	1H
		MONOSTABLE					2 PHASE
	S	SET	BLANKER			IOUT
							STEPPER MOTOR
	Q
(0)	(1)
	R					OUT2A(or B)
				DRIVERS		DRIVERS
	-			+		+
				DEAD TIME		DEAD TIME
5V	+					OUT1A(or B)
	2.5V
			SENSE
			COMPARATOR		2L	1L
				+
		COMPARATOR		-
			OUTPUT
	RCA(or B)			VREFA(or B)		SENSEA(or B)
COFF	ROFF				RSENSE
						D01IN1332

Figure 13 shows the typical operating waveforms of the output current, the voltage drop across the sensing resistor, the RC pin voltage and the status of the bridge. More details regarding the Synchronous Rectification and the output stage configuration are included in the next section.

Immediately after the Power MOS turns on, a high peak current flows through the sensing resistor due to the reverse recovery of the freewheeling diodes. The L6208 provides a 1μs Blanking Time tBLANK that inhibits the comparator output so that this current spike cannot prematurely re-trigger the monostable.

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