ST AN1451 APPLICATION NOTE
AN1451
APPLICATION NOTE
L6208 FULLY INTEGRATED TWO PHASE
STEPPER MOTOR DRIVER
by Domenico Arrigo, Vincenzo Marano and Thomas Hopkins
Modern motion control applications need more flexibility that can be addressed only with specialized IC
products. The L6208 is a full y i ntegr ated steppe r motor dr iv er IC speci ficall y developed to drive a wide r ange
of two phase (bipolar) stepper motors. This IC is a one-chip cost effective solution that includes several
unique circuit design features. These features, including a decoding logic that can generate three different
stepping sequences, allow the device to be used in many applications inc luding microstepping. The prin cipal
aim of this development project was to produce an easy to use, fully protected power IC. In addition several
key functions such as protection circuit and PWM current control drastically reduce external components
count to meet requirements for many different applications.
1 INTRODUCTION
The L6208 is a highly integrated, mixed-signal power IC that allows the user to easily design a complete motor
control system for two-phase bipolar stepper motors. Figure 1 shows the L6208 block diagram. The IC integrates eight Power DMOS, a centralized logic circuit which implements the phase generation and a constant
t
PWM current control technique (
OFF
other added features for safe operation and flexibility.
Quasi-Synchronous mode
) for each of the two phases of the motor plus
Figure 1. L6208 block diagram.
V
BOOT
V
CONTROL
HALF/FULL
CLOCK
RESET
CW/CCW
GND
GND
GND
GND
CP
EN
V
BOOT
CHARGE
PUMP
STEPPING
SEQUENCE
GENERATION
VOLTAGE
REGULATOR
5V10V
L6208
THERMAL
PROTECTION
OCD
OCD
V
V
BOOT
OVER
A
B
CURRENT
DETECTION
GATE
LOGIC
OVER
CURRENT
DETECTION
GATE
LOGIC
10V 10V
PWM
ONE SHOT
MONOSTABLE
MASKING
TIME
V
BOOT
SENSE
COMPARATOR
BRIDGE A
BRIDGE B
+
-
D01IN1226
SA
OUT1
OUT2
SENSE
VREF
RC
A
V
SB
OUT1
OUT2
SENSE
VREF
RC
B
A
A
A
A
B
B
B
B
October 2003
1/43
AN1451 APPLICATION NOTE
Table of Contents
1 INTRODUCTION................................................................................................................................ 1
2 DESIGNING AN APPLICATION WI TH L620 8 ...................................................................................3
2.1 Current Ratings........................................................................................................................3
2.2 Voltage Rating s and Operating Range ....................................................................................3
2.3 Choosing th e Bulk Capacitor....................................................................................................5
2.4 Layout Considerations.............................................................................................................6
2.5 Sensing Resisto r s.............................. ......................................................... ..................... ....... .8
2.6 Charge pump external components.........................................................................................9
2.7 Sharing the Charge Pump Circuitry .......................................................................................10
2.8 Reference Voltage for PWM Current Control.........................................................................11
2.9 Input Logic pins......................................................................................................................12
2.10 EN pin....................................................................................................................................12
2.11 Program mab le off-time Monost able......................................................................................13
2.11.1 Off-time Selection and minimum on-time ........................................................................15
2.11.2 Decay Modes ............................................................................... ..... ....... ....... ..... ...........16
2.12 Over Current Protection........................................................................................................18
2.13 Power Managem ent..............................................................................................................21
2.13.1 Maximum output current vs. selectable devices..............................................................22
2.13.2 Power Dissipation Formulae for different sequences......................................................22
2.14 Choosing the Decay Mode....................................................................................................25
2.15 Choosing the Step ping Sequence. ........................................................................................26
2.16 Microstepping........................................................................................................................27
3 APPLICATION EXAM PL E.............................. ......................................................... .........................30
3.1 Decay mode, sensing resistors and reference voltage..........................................................30
4 APPENDIX - EVALUATI ON BO ARD S...................................................................... .......................31
4.1 PractiSPIN............................................................................. .................................................31
4.2 EVAL6208N ...........................................................................................................................33
4.2.1 Important Not e s......... ................................... ......................................................... ....... ....34
4.2.2 Thermal Impedance .........................................................................................................34
4.3 EVAL6208PD.........................................................................................................................38
4.3.1 Important Not e s......... ................................... ......................................................... ....... ....39
4.3.2 Thermal Impedance .........................................................................................................39
5 REFERENCES.................................................................................................................................43
2/43
AN1451 APPLICATION NOTE
2 DESIGNING AN APPLICATION WITH L6208
2.1 Current Ratings
With MOSFET (DMOS) devices, unlike bipolar transistors, current under short circuit conditions is, at first approximation, limited by the R
and the two V
and VSB pins are rated for a maximum of 2.8A r.m.s. and 5.6A peak (typical values), corre-
SA
of the DMOS themselves and could rea ch ve ry high values . L6208
DS(ON)
sponding to a total (for the whole IC) 5.6A rms (11.2A peak). These values are meant to avoid damaging metal
structures, including the metal lizati on on the die and bond w ires. In prac tical appl ications , though, maxi mum allowable current is less than these values, due to power dissipation limits (
see
Power Management
The device has a built-in Over Current Detection (OCD) that provides protection against short circuits between
the outputs and between an output and ground (
see
Over Current Protection
section
).
2.2 Voltage Ratings and Operating Range
The L6208 requires a single supply voltage (VS), for the motor supply. Internal voltage regulators provide the
5V and 10V required for the internal circuitry. The operating range for V
undesirable low sup ply vol tage an
voltage falls below 6V; to resume normal operating conditions, V
Under Voltage Lock Out
(
UVLO
must then exceed 7V. The hysteresis is pro-
S
vided to avoid false intervention of the UVLO function during fast V
DMOS's R
is a function of the VS supply voltage. Actually, when VS is less than 10V, R
DS(ON)
affected, and this is particularly true for the High Side DMOS that are driven from V
is 8 to 52V. To prevent working into
S
) circuit shuts down the dev ice when suppl y
ringings. It should be noted, however, that
S
DS(ON)
supply. This supply is
BOOT
obtained through a charge pump fr om the internal 10V supply, which will tend to r educe i ts output v oltage when
V
goes below 10V. Figure 2 shows the supply voltage of the high side gate drivers (V
S
supply voltage (V
).
S
- VS) versus the
BOOT
Out
pins
section
is adversely
).
Figure 2. High side gate drivers supply voltage versus supply volta ge.
8
7.6
V
BOOT
- V
[V]
7.2
S
6.8
6.4
6
8 8.5 9 9.5 10 10.5
VS [V]
Note that VS must be connected to both VSA and VSB since the bootstrap voltage (at V
pin) is the same for
BOOT
the two H-bridges. The integrated DMOS have a rated Drain-Source breakdown voltage of 60V. However V
should be kept below 52V, since in normal working conditions the DMOS see a Vds voltage that will exceed V
supply. In particular, when using the
off during dead-time) the
SENSE
PCB path from the pin to GND. This spike is followed by a stable negative voltage due to the drop on R
One of the two
OUT
pins of the bridge sees a similar behavior, but with a slightly larger voltage due to the for-
fast decay
mode, at the beginning of the off-time (when all the DMOS are
pin sees a negative spike due to a not negligible parasitic inductance of the
SENSE
ward recovery time of the integrated freewheeling diode and the forward voltage drop across it (see Figure 3).
Typical duration of this spike is 30ns. At the same time, the other
OUT
pin of the same bridge sees a voltage
S
S
.
3/43
AN1451 APPLICATION NOTE
above VS, due to the PCB inductance and voltage drop across the high-side (integrated) freewheeling diode,
as the current reverses direction and flows into the bulk capacitor. It turns out that, in fast decay, the highest
differential voltage is observed between the two
and this must always be kept below 60V [3]. The same high voltage condition exists when a step is made and
the direction of current flow reverses in the bridge.
OUT
pins of the same bridge, at the beginning of the off-time,
Figure 3. Currents and voltages during the
ESR
Bulk Capacitor
Equivalent Circuit
ESL
PCB Parasitic
Inductance
R
*I+V
SENSE
F(Diode)
R
SENSE
dead time
*I
SENSE
at the beginning of the
V
S
OUT
2
OUT
1
Dangerous
High Differential Voltage
PCB Par a s i ti c
R
SENSE
Inductan ce
off-time
VS+V
F(Diode)
.
Figure 4 shows the voltage waveform s at the two OUT pins referring to a pos sible pr actical situ ation, with a peak
output current of 2.8A, V
ground spike amplitude is -2.65V for one output; the other
= 52V, R
S
= 0.33Ω, TJ = 25°C (approximately) and a good PCB layout. Below
SENSE
OUT
pin is at about 57V . In these conditions, total
differential voltage reaches almost 60V, which is the a bsolute max imum rating for the DMOS. Keepi ng differential voltage between two Output pins belonging to the same Full Bridge within rated values is a must that can
be accomplished with proper selection of Bulk capacitor value and equivalent series resistance (ESR), according to current peaks and chopping style and adopting good layout practices to minimize PCB parasitic inductances (see below) [3].
4/43
AN1451 APPLICATION NOTE
Figure 4. Voltage at the two outputs at the beginning of the off-time.
Out 1
Out 2
2.3 Choosing the Bulk Capacitor
Since the bulk capacitor, placed between VS and
AC current capability
must be greater than the r .m.s . val ue of the c harge/discha rge current. Thi s c urrent flows
from the capacitor to the IC during the on-time (t
slow decay) to the capacitor during the off-time (t
pacitor depends on peak output current, output current ripple, switching frequency, duty-cycle and chopping
style. It also depends on power supply characteristics. A power supply with poor high frequency performances
(or long, inductive connections to the IC) will cause the bulk capacitor to be recharged slowly: the higher the
current control switc hing frequency , the hig her the cur rent rippl e in the capaci t or; r.m.s. cur rent i n the capa citor,
however, does not exceed t he r.m.s. output current. Bulk capacitor value (
of voltage ripple on the capac itor itself and on the IC . In slow decay, neglecti ng the
ripple, and assuming that during the
the end of the
on-time
is:
on-time
GND
pins, is charged and discharged during IC operation, its
) and from the IC (in fast decay; from the power supply in
ON
). The r.m.s. value of the current flowing into the bulk ca-
OFF
C
) and the
ESR
determine the amount
dead-time
and output current
the capacitor is not recharged by the power supply, the voltage at
t
VSI
– ESR
OUT
⋅
-------- -+
ON
C
,
so the supply voltage ripple is:
t
---------+
ON
C
,
where I
I
OUT
is the output current. With fast decay, i nstead, recirculating curr ent recharges the capacitor , causing
OUT
ESR
⋅
the supply voltage to exceed the nominal voltage. This can be very dangerous if the nominal supply voltage is
close to the maximum recommended supply voltage (52V). In fast decay the supply voltage ripple is about:
t
+
I
OUT
2 ESR⋅
⋅
ONtOFF
--------------------------- -+
C
,
always assuming that the power supply does not recharge the capacitor, and neglecting the output current ripple
and the dead-time. Usually (if C > 100 µF) the capacitance role is much less than the ESR, then supply v oltage
ripple can be estimated as:
5/43
AN1451 APPLICATION NOTE
K
I
· ESR in slow decay
OUT
OUT
2A
0.5 V
------------
⋅< 125mΩ=
2A
· ESR in fast decay
= 2A, the capacitor ESR should be lower than:
OUT
in slow decay, and
in fast decay.
2 · I
For Example, if a maximum ri pple of 500mV is all owed and I
0.5 V
ESR
------------
< 250mΩ=
1
---
2
Actually, current sunk by V
ESR
and VSB pins of the device is subject to higher peaks due to reverse recovery
SA
charge of internal freewheeling diodes. Duration of these peaks is, tough, very short, and can be filtered using
a small value (100÷200 nF), good quality ceramic capacitor, connected as close as possible to the V
and GND pins of the IC. Bulk capacitor will be chosen with
maximum operating voltage
25% greater than the
SA
, V
SB
maximum supply voltage, considering also power supply tolerances. For example, with a 48V nominal power
supply, with 5% tol erance, maximum voltage is 50.4V, then operati ng voltage for the capacitor should be at least
63V.
2.4 Layout Considerations
Working with devices that combine high power switches and control logic in the same IC, careful attention has
to be paid to the PCB lay out. In extreme cases, Power DMOS commutation can i nduce nois es that could c ause
improper operation in the logic section of the device. Noise can be radiated by high dv/dt nodes or high di/dt
paths, or conducted through G ND or Supply connectio ns. Logic connec tions, es pecial ly hi gh-i mpedance nodes
(actually all logic inputs, see further), must be kept far from switching nodes and paths. With the L6208, in particular, external components for the charge pump circuitry should be connected together through short paths,
since these components are subjec t to voltage and current swi tching at re lative ly high frequenc y (600kHz ). Primary mean in minimizing conducted noise is working on a good GND layout (see Figure 5).
Figure 5. Typ ic a l App li ca ti on and Layout suggest io ns.
OUT
1B
2-Phase
Stepper Motor
V
BOOT
2B
L6208
C3
R3
D1
C5
R4
RC
B
6/43
+
Logic Supply
3.3 ÷ 5 V
-
µC
or
Custom Logic
V
= 0 ÷1V
ref
OUT
OUT
OUT
1A
2A
CW / CCW
CONTROL
RESET
HALF / F ULL
CLOC
R1
EN
V
refB RCA
V
refA
C1
C2
R2
D2
CP
V
SA VSB
SENSE
SENSE
C8
A
B
R5 R6
C6
+
C7
VS = 8 ÷ 52 V
-
GND GND GND GND
C4
AN1451 APPLICATION NOTE
High current GND tracks (i.e. the tracks connected to the sensing resistors) must be connected directly to the
negative terminal of the bulk capacitor. A good quality, high-frequency bypass capacitor is also required (typically a 100nF÷200nF ceramic would suffice), since electrolytic capacitors show a poor high frequency performance. Both bulk electrolytic and high frequency bypass capacitors have to be connected with short tracks to
V
, VSB and GND. On the L6208 GND pins are the
SA
them. Logic GND and Power GND should be connected together in a
noise in the Power GND from affecting Logic GND. Specific care should be paid layouting the path from the
SENSE
pins through the sensing resistors to the negative terminal of the bulk capacitor (Power Ground). These
tracks must be as s hort as possible in order to mi nimize par asitic inductances that c an cause danger ous voltage
spikes on
the capacitors on V
SENSE
and
OUT
pins (see the
, VSB and GND should be very close to the GND and supply pins. Refer to the Sensing
SA
Voltage Ratings and Operating Range
Resistors section for information on selecting the sense resistors. Traces that connect to V
SENSE
, and the four
B
OUT
pins must be designed with adequate width, since high currents are flowing through
these traces, and l ayer chan ges should be avoided. Should a l ayer ch ange prove necessa ry , multi ple and large
via holes have to be used. A wide GND copper area can be used to improve power dissipation for the device.
Figure 6 shows two typical situations that must be avoided. An important consideration about the location of the
bulk capacitors is the abi lity to abs orb the inductiv e ener gy from the load, without all owing the s upply v oltage to
exceed the maximum rating. The diode shown in Figure 6 prevents the recirculation current from reaching the
capacitors and will res ult in a high voltage on the IC pins th at can destroy the device. H aving a switch or a power
connection that can dis connect the c apacitors from the IC, w hile there is stil l c ur rent in the motor, will a lso result
in a high voltage transient since there is no capacitance to absorb the recirculation current.
Logic
GND, since only the quiescen t curr ent flows thr ough
single point
, the bulk capacitor, to keep
section); for the same reason
, VSB, SENSEA,
SA
Figure 6. Two situations that must be avoided.
V
SA VSB
SENSE
A
SENSE
B
L6208
GND
GND
GND
GND
R5
C6
DON’T connect the Logic GND here
Voltage drop due to c urrent in sens e
path can disturb lo gic GND.
DON’T put a di ode here!
Recircul at ing current cannot flow into t he
bulk cap ac itor and c aus es a high volt age
spike that c an des troy the IC.
+
C7
VS = 8 ÷ 52 V
-
7/43
AN1451 APPLICATION NOTE
2.5 S en sing Resistors
Each motor winding current is flowing through the corresponding sensing resistor, causing a voltage drop that
is used, by the logic, to control the peak value of the load current. Tw o issues must be taken into account when
choosing the R
– The sensing resistor dissipates energy and provides dangerous negative voltages on the
during the current recirculation. For this reason the resistance of this component should be kept low.
– The voltage drop acros s R
comparator. The lower is the R
and to the input offset of the current sense comparator: too small values of R
A good compromise is calculating the sensi ng resistor value so that the voltage drop , corresponding to the peak
current in the load (I
It should be clear that sensing resistor must absolutely be non-inductive type in order to avoid dangerous negative spikes on
ommended for their high peak current capability and low inductance. For the same reason the connections
between the
(see also the
SENSE
Layout Considerations
The average power dissipated by the sensing resistor is:
value:
SENSE
SENSE
SENSE
), is about 0.5 V: R
peak
SENSE
pins. Wire-wounded resistors c annot be used here, whi le Metall ic film res istor s are rec-
pins, C6, C7, VSA, VSB and
section).
SENSE
is compared with the reference voltage (on V
pin) by the internal
ref
value, the higher is the peak current error due to noise on Vref pin
must be avoided.
SENSE
SENSE
= 0.5 V / I
GND
pins (see Figure 5) must be taken as short as possible
peak
.
pin
Fast Decay Recirculation: P
R
≈ I
Slow Decay Recirculation: PR ≈ I
D is the duty-cycle of the PWM current control, I
rms
rms
· R
2
· R
SENSE
· D,
SEN SE
is the r.m.s. value of the load current.
rms
2
Nevertheless, sensing resistor power rating should be chosen taking into account the peak value of the dissipated power:
where I
is the peak value of the load current.
pk
PRI
pk
2
R
⋅≈
SENSE
,
Using multiple resistors in parallel will help obtaining the required power rating with standard resistors, and reduce the inductance.
R
The following table shows R
tolerance reflects on the peak current error: 1% resistors should be preferred.
SENSE
recommended values (to have 0.5V drop on it) and power ratings for typical
SENSE
examples of current peak values.
I
pk
0.5 1 0.25
1 0.5 0.5 2 X 1Ω, 0.25W paralleled
1.5 0.33 0.75 3 X 1Ω, 0.25W paralleled
2 0.25 1 4 X 1Ω, 0.25W paralleled
R
SENSE
Value
[Ω]
R
SENSE
Power Rating
[W]
Alternatives
8/43
AN1451 APPLICATION NOTE
2.6 Charge pump external components
An internal oscillator, with its output at CP pin, switches from GND to 10V with a typical frequency of 600kHz
(see Figure 7).
Figure 7. Charge Pump .
VS + 10 V - VD1 - V
V
10 V
f = 600 kHz
D2
D1
C5
R4
BOOT CP
To High-Side
Gate Drivers
f = 600 kHz
D2
10 V
V
SA VSB
R
DS(ON)
R
DS(ON)
= 70Ω
= 70Ω
VS + 10 V - VD1
V
C8
- VD1
S
Charge Pump
Oscillator
10 V
5 V
L6208
When the oscillator output is at ground, C5 is charged by VS through D2. When it rises to 10V, D2 is r eve rse
biased and the charge flows from C
imum voltage of V
+ 10V - VD1 - VD2, which supplies the high-side gate drivers.
S
With a differential vol tage betw een V
ical current drawn by the V
R4
Resistor
is added to reduce the maxi mum current i n the exter nal components and to reduce the slew rate of
BOOT
the rising and falling edges of the voltage at the
circuit. For the same reason car e must be taken in realiz ing the PC B layout of
also the
Layout Considerations
D1, D2 : 1N4148
R4 : 100
Ω (1/8 W)
C5 : 10nF 100V ceramic
C8 : 220nF 25V ceramic
Due to the high charge pump frequency, fast diodes are required. Connecting the cold side of the bulk capacitor
(C8) to V
R4 = 100
instead of GND the average current in the external diodes during operation is less than 10 mA (with
S
Ω
); at startup (when VS is provided to the IC) is less than 200 mA while the reverse voltage is about
10 V in all condi tions. 1N4148 diodes withstand about 200 mA DC (1 A peak), and the maximum rever se voltage
is 75 V, so they should fit for the majority of applications.
to C8 through D1, so the V
5
and V
S
of about 9V and both the bridges switching at 50kHz, the typ-
BOOT
pin, after a few cycles, reaches the max-
BOOT
pin is 1.85 mA.
CP
pin, in order to minimize interferences with the rest of the
R4, C5, D1, D2
connections (see
section). Recommended values for the charge pump circuitry are:
9/43
AN1451 APPLICATION NOTE
2.7 S ha ring the Charge Pump Circuitry
If more than one device is used in the applic ation, it's possible to use the char ge pump from one L6208 to suppl y
the V
Figure 8. A 100nF capacitor (C8) should be connected to the V
Supply voltage pins (V
The higher the number of devices sharing the same charge pump, the lower will be the differential volt age avail-
able for gate drive (V
In this case it's recommended to omit the resistor on the
charge pump circuitry.
Better performance can als o be obtained using a 33nF capacitor for C5 and using s chottky diodes (for ex ample
BAT47 are recommended).
Sharing the same charge pump ci rcuitr y fo r mor e than 3÷4 devi ces is not recommended, sinc e it wil l reduce the
V
BOOT
Figure 8. Sharing the charge pum p circuitry.
pins of several ICs. The unused CP pins on the slaved devices are left unconnected, as shown in
BOOT
pin of each device.
BOOT
) of the devices sharing the charge pump must be connected together.
S
- VS), causing a higher R
BOOT
for the high side DMOS, so higher dissipating po wer.
DS(ON)
CP
pin, obtaining a higher current capability of the
voltage increasing the high-side MOS on-resistance and thus power dissipation.
To other Devices
V
BO OT
To High-Side
Gate Drivers
D2 = BAT47
CP
V
SA VSB
C8 = 100nF
L6208
V
BOOT
To High-Side
Gate Drivers
D1 = BAT47
C5 = 33nF
C18 = 100 nF
V
V
SA
CP
SB
L6208
10/43
AN1451 APPLICATION NOTE
2.8 Reference Voltage for PWM Current Control
The device has two analog inputs, V
peak value of the motor curr ent through th e integrated PWM circuitry . In typical applications these p ins ar e connected together, in order to obtain the same current in the two motor windings (one exception is the microstepping operation; see the related section). A fixed reference voltage can be easily obtained through a resistive
divider from an available 5 V voltage rail (maybe the one supplying the µC or the rest of the application) and
GND.
A very simple way to obtain a variable voltage without using a DAC is to low-pass filter a PWM output of a µC
(see Figure 9).
Assuming that the PWM output swings from 0 to 5V, the resulting voltage will be:
refA
and V
V
ref
, connected to the internal sense comparators, to control the
refB
5V DµCR
⋅⋅
-----------------------------------------=
R
LPRDIV
DIV
+
where D
Assuming that the µC output impedance is lower than 1k
is the duty-cycle of the PWM output of the µC.
µC
Ω,
with RLP = 56kΩ, R
= 15kΩ, CLP = 10nF and a
DIV
µC PWM switching fr om 0 to 5V at 100kHz , the l ow pass fi lter tim e consta nt is about 0.12 ms an d the remai ning
ripple on the V
voltage will be about 20 mV. Using higher values for RLP, R
ref
and CLP will reduce the ripple,
DIV
but the reference voltage will tak e more time to vary after changing the duty -cycle of the µC PWM, an d too high
values of R
As sensing resistor values are typically kept small, a small noise on V
will also increase the im pedance of the V
LP
net at low frequencies, causing a poor nois e immunity.
ref
input pins might cause a considerable
ref
error in the output current. It's then recommended to decouple these pins with cerami c capaci tors of some tens
of nF, placed very close to V
and GND pins. Note that V
ref
pins cannot be l eft unconnected, while, if connected
ref
to GND, zero current is not guaranteed due to voltage offset in the sense comparator. The best way to cut down
EN
(IC) power consumption and clear the load current is pulling down the
pin. In slow decay, with very small
reference voltage, PWM integrated circuitry can loose control of the current due to the minimum allowed duration of t
(see the
ON
Programmable off-time Monostable
section).
Figure 9. Obt ain in g a va ri abl e v ol ta ge t hro ugh a PWM ou t put of a µC .
PWM Output
of a µC
R
LP
R
DIV
V
ref
C
LP
GND
11/43
AN1451 APPLICATION NOTE
2.9 Input Logi c pin s
CW/CCW, CONTROL, RESET, HALF/FULL, CLOCK
ator has been realized with hysteresis to ensure the required noise immunity. Typical values for turn-on and turn-off
thresholds are V
= 1.8V and V
th,ON
= 1.3V. Pins are ESD protected (see Figure 10) (2kV human-body electro-
th,OFF
static discharge), and can be direc tly connected to the logic outputs of a µC; a series resistor is generally not reco mmended, as i t c ould help inducted noise to disturb the inputs. All logi c pins enforce a specific behavi or and cannot be
left unconnec ted.
Figure 10. Logic input pins.
are CMOS/TTL compatible lo gic input pins. The input compar-
CONTROL,
HALF/FULL, CLOCK,
RESET, CW/CCW
ESD
Protection
5 V
2.10EN pin
The EN pin is, actually, bi-directional: as an input, with a comparator similar to the other logic input pins (TTL/CMOS
with hyst eresis), it c ontrols the s tate of the PowerDMOS. When th is pin is at a low logic level, all t he PowerDMOS ar e
turned off. The EN pin is als o connected to the open drai n output of the protection circuit that will pull the pin to GND
if over current or over temperature conditions exist. For this reason, EN pin must be driven through a series resistor
of 2.2k
Ω
minimum (for 5V logic), to al lo w the voltage at the pin to be pulled below t he turn-off threshold.
A capaci tor (C1 i n Figu re 5) conne cted be tween t he EN pin and GND is al so re commended , to redu ce the r.m.s . val ue
of the output current when overcurrent conditions persist (see
Over Current Protection
section). EN pin must not be
left unconnec ted.
Figure 11. EN input pin.
5 V
12/43
EN
ESD
Protection
AN1451 APPLICATION NOTE
2.11 Programmable off-time Monostable
The L6208 includes a constant off time PWM current controller for each of the two bridges. The current control
circuit senses the bridge current by sensing the voltage drop across an external sense resistor connected between the source of the two lower power MOS transistors and ground, as shown in
the motor builds up the voltage across the sense resistor increases proportionally. When the voltage drop
across the sense resistor becomes greater than the voltage at the reference input (VREF
comparator triggers the monostable switching the bridge off. The power MOS remain off for the time set by the
monostable and the motor current recirculates as defined by the selected decay mode, described in the next
section. When the monostable times out the bridge w ill again turn on. S ince the inter nal dead time, us ed to prevent cross c onduction in the bridge, delays the turn on of the power MOS, the effecti ve off time is the s um of the
monostable time plus the dead time.
Figure 12. PWM Current Controller Simplified Schematic
(or B)
VS
A
TO GATE LOGIC
BLANKING TIME
MONOST ABLE
1µs
FROM THE
LOW-SIDE
GATE DRIVERS
Figure 12
. As the current in
or VREFB) the sense
A
5mA
5V
C
OFF
Figure 13
MONOSTABLE
(0) (1)
RC
R
OFF
A(or B)
2.5V
S
Q
R
-
+
SET
BLANKER
SENSE
COMPARATOR
COMPARATOR
OUTPUT
DRIVERS
+
DEAD TIME
+
-
VREF
shows the typical operating waveforms of the output current, the voltage drop across the sensing re-
2H 1H
2L 1L
A(or B)
R
SENSE
DRIVERS
+
DEAD TIME
SENSE
A(or B)
OUT2
OUT1
I
OUT
A(or B)
A(or B)
D01IN1332
2 PHASE
STEPPER MOTOR
sistor, the RC pin vol tage and the status of the bridge. More d etails regarding the S ynchronous Rectificati on and
the output stage configuration are included in the next section.
Immediately after the Power MOS turns on, a high peak current flows through the sensing resistor due to the
reverse recovery of the freewheeling diodes. The L6208 provides a 1
µ
s Blanking Time t
that inhibits the
BLANK
comparator output so that this current spike cannot prematurely re-trigger the monostable.
13/43
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