ST AN1365 Application note
AN1365
APPLICATION NOTE
GUIDELINES FOR MIGRATING ST72C254
APPLICATIONS TO ST72F264
INTRODUCTION
This application note provides information on us ing ST72264 new series in an application ori ginally designed for the ST72254, 215, 216, 104 series.
1 FEATURE OVE RVI EW
Feature
Package SDIP32/SO28 (no change)
Program Memory FLASH/ROM
Operating Supply 3.2V to 5.5V 2.7V to 5.5V
Register Map 128 bytes (no change)
I/Os 28 pins (see Section 2.2 Pinout)
Slow Mode Yes
Active-HALT No Yes (4096 t
Nested Interrupts No Yes (not by default)
Watchdog Yes
16-bit Timer 1212
SPI Yes
SCI No Yes
2
I
C No Yes No Y es
ADC No Yes (8-bit) No Yes (10-bit)
LVD 3 Levels (CFlash and XFlash levels may differ, refer to the datasheet)
CSS Yes (fixed frequency) -> CRSR No
Emulator ST7MDT1-EMU2B and ST7MTD1-DVP2 ST7MDT10-EMU3
Programming
2)
tools
1)
ST72104 ST72215 ST72216 ST72C254 ST72260 ST7226 2 ST72F264
delay on wake-up)
CPU
2 (minor change in
PWM and One Pulse modes)
ST7MDT1-EPB2 and ST7 MT D 1 - DVP2
ST7MDT10 -EPB and ST7MDT10-
DVP3
Note 1: refer to the corresponding datasheets for more information on electrical characteristics.
Note 2
AN1365/0504 1/13
:
Go to
http://www.st.com > Products > Product Support > Microcontrollers - Forum
informati on on third-party tools.
for
Rev. 2.0
1
GUIDELINES FOR MIGRATING ST72C254 APPLICATIONS TO ST72F264
2 PINOUT CO MPATIBILITY
2.1 PACKAGE
All devices are available in SDIP32 and SO28 packages.
2.2 PINOUT
Some pins have been changed in the pinout of the ST 72F264 (and s ubsets) device to add the
SCI peripheral (see Table 1) and to move the ISP pins (which have be come ICC pi ns) (see
Table 2).
For more information about ICC (In-Circuit Communication) protocol, please refer to the ST7
FLASH Programming and ICC Reference Manuals av ailable on Internet (http://www.st.com).
Table 1 . Addition of SCI Pins
ST72F264 only
SDIP32 Package TDO (pin 20) RDI (pin 22)
SO28 Package TDO (pin 18) RDI (pin 20)
Table 2. Pin Changes
ST72C254 and Subsets ST72F264 and Subsets
SDIP32 Package SO28 Package SDIP32 Package SO28 Package
ISPCLK (pin 5) ISPCLK (pin 5) ICCCLK (pin 29) ICCCLK (pin 25)
ISPDATA (pin 6) ISPDATA (pin 6) ICCDATA (pin 28) ICCDATA (pin 24)
TDO is the Transmit Data Output pin and RDI is the Receive Data Input pin of the SCI (Serial
Communication Interface) peripheral.
2/13
2
GUIDELINES FOR MIGRATING ST72C254 A PPLICATIONS TO ST72F264
3 TIMING
3.1 CYCLE ACCURACY
All timings are compatible between the ST72C254 and the ST72F264 devices except internal
timings linked to the cycle accuracy. The ST72C254 is based on latches (gates) while the
ST72F264 is bas ed o n R TL (fl ip-flop). T her efore , a d ifferen ce of a h alf c ycle may oc cur between those two devices.
This means that all software with timings based on fixed processor cycle times (a practice not
recommended) must be verified in detail. An example of this would be a software wait loop implemented as a sequence of NOP instructions as opposed to polling a busy bit.
This internal difference does not affect the general timings.
3.2 CLOCK SECURITY SYSTEM (CSS)
The backup oscillator of CSS available in the ST72C254 device (and subsets) has a fixed frequency between 250 kHz and 550 kHz in normal conditions (T=25° and Vdd=5V).
In the ST72F264 device (and subsets), there is no backup oscillator frequency.
3.3 PHASE LOCKED LOOP (PLL)
A PLL has been added in the ST72F264 in order to be abl e to multiply the oscillator frequency
by 2 (for a f
input frequency between 2 and 4 MHz). This PLL is activated through an op-
OSC
tion bit.
Figure 1. PLL Dia gram
f
OSC
PLL x 2
/ 2
0
1
PLL OPTION BIT
f
OSC2
Note: Use of the PLL with the internal RC oscillator is not supported.
3/13
GUIDELINES FOR MIGRATING ST72C254 APPLICATIONS TO ST72F264
3.4 WATCHDOG TIMINGS
In the ST72F264, the watchdog timeout does not have an exact duration as in the ST72C254.
It may vary between the min. and max. times specified in Figure 3.. To guarantee upward
compatibility, you have to take this into account when you develop your software. The reason
for this change is that the watchdog counter has been grouped with the Active-HALT counter
and SLOW mode prescaler to enhance power consumption and EMC performance.
Figure 2. Watchdog Bloc k Diagram
f
OSC2
RESET
MCC/RTC
WATCHDOG CONTROL REGISTER (WDGCR)
DIV 64
12-BIT MCC
RTC COUNTER
MSB LSB
11
56
TB[1:0] bits
(MCCSR
0
Register)
WDGA
The watchdog counter is no longer clocked by f
divided by 16 384 (f
if the PLL is disabled).
f
CPU
is the PLL out put freq uency whe n the PLL is activ ated or f
OSC2
CPU
T5
T6 T0
T4
T3
6-BIT DOWNCOUNTER (CNT)
WDG PRESCALER
DIV 4
T2
T1
(as it was for the ST72C254) but by f
OSC
OSC2
/2 =
In the ST72F264 datasheet, the linear relationship between the 6-bit value to be loaded in the
Watchdog Counter (CNT) and the resulting timeout duration in milliseconds is described. This
can be used for a quick calculation without taking the timing variations into account.
If more precision is needed, use the formulae in Figure 3..
4/13
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