ST AN1334 APPLICATION NOTE

AN1334

APPLICATION NOTE

ST10F269/F280 System Reset

By André ROGER

1 - INTRODUCTION

This application note is intended for hardware designers. It explains the different kinds of reset available on ST10F269/ST10F280 and compares ST10F269/ST10F280 reset features with ST10F168 ones.

More specifically, after a quick summar y, it details the new flags added to WDTCON register, then gives an application view of the different resets. A specific chapter is devoted to the bidirectional reset to detail the advantages and constraints of using this mode.

After des c ribing the start-up c on f igu ra ti on , us er s will find a chapter de t ailing ST10 res et key param e t er s.

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AN1334 - APPLICATION NOTE

TABLE CONTENTS PAGE

1 INTRODUCTION......................................................................................................... 1

2 SYSTEM RESET......................................................................................................... 3

3 WDTCON NEW FLAGS FOR RESET CAUSES........................................................ 5

3.1 WDTCON DESCRIPTION........................................................................................... 5

3.2 POWER-ON DETECTION........................................................................................... 5

3.3 SUPPLY MONITORING.............................................................................................. 6

4 RSTOUT PIN............................................................................................................... 6

5 RESET AND RPD PIN ................................................................................................ 6

6 APPLICATION VIEW.................................................................................................. 8

6.1 POWER-ON HARDWARE RESET ............................................................................. 8

6.2 POWER-ON RESET AFTER A PARTIAL POWER FAILURE .................................... 8

6.3 LONG HARDWARE RESET ....................................................................................... 9

6.4 SHORT HARDWARE RESET..................................................................................... 9

6.5 SOFTWARE RESET................................................................................................... 10

6.6 WATCHDOG TIMER RESET...................................................................................... 11

7 BI-DIRECTIONAL RESET.......................................................................................... 11

7.1 BI-DIRECTIONAL RESET AND RSTIN CHARGE TIME ............................................ 12

7.2 BI-DIRECTIONAL RESET AND SHORT HARDWARE RESET.................................. 13

8 SYSTEM START-UP CONFIGURATION ................................................................... 13

9 RESET KEY PARAMETERS...................................................................................... 15

9.1 RSTIN ACTIVATION TIME.......................................................................................... 15

9.1.1 Power-on Reset Time.................................................................................................. 15

9.1.2 Asynchronous Reset................................................................................................... 15

9.1.3 Software or Watchdog Reset....................................................................................... 15

9.2 CONFIGURATION RESISTORS ON PORT0............................................................. 15

9.2.1 Pull-down Resistors..................................................................................................... 15

9.2.2 Pull-up Resistors ......................................................................................................... 15

9.2.3 PLL Lock Sequen ce, Configuration Resistors and Reset Duration............................. 15

9.3 COMPONENTS ON RPD PIN ..................................................................................... 16

9.3.1 Difference with ST10F168........................................................................................... 16

9.3.2 Interruptible Power-down Mode Not Used................................................................... 16

9.3.3 Interruptible Mode is Used........................................................................................... 16

10 APPLICATION NOTE VERSION INFORMATION...................................................... 16

10.1 REVISION OF 5TH OF FEBRUARY 2001.................................................................. 16

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2 - SYSTEM RESET

System reset initializes a device into a pre-defined default state.

ST10F269 and ST10F280 h ave the same types of reset as ST10F16 8

– Asynchronous hardware reset : defined by assertion of the RSTIN – Synchronous short hardware reset: defined by assertion of the RSTIN

level on RPD pin.

– Synchronous long hardware reset: defined by assertion of the RSTIN

high level on RPD pin. – Software reset: reset initiated by the execution of SRST instruction. – Watchdog reset: reset triggered by an overflow of the watchdog timer.

The functionalities associated to reset are unchan ge d

– Bidirectional reset can be enabled to convert software and watchdog resets to hardware reset. – RSTOUT

is activated once reset conditions are detected and rema ins active until the execution o f the

EINIT instruction. The CPU and peripherals are set in their predefined default state. – The content of some sp ecial fun ction re gister s (SYSCON, BUSCO N0, RP0H) ar e control led duri ng sys-

tem start-up configuration via PORT0 pins. The sy stem start-up configuration is sampled differently

upon the different reset types. – After the internal reset condition is removed, the microcontroller will start program execution from mem-

ory location 00’0000h in code segment zero. This start location will typically hold a branch instruction to

the start of a software initialization routine for the application specific configuration of peripherals and

CPU Special Function Registers.

pin with a low level on RPD pin.

pin for less 1032 TCL, with a high

pin more than 1032 TCL, with a

Difference with ST10F168

The main difference with ST10F168 is that register W DTCON has been modified to suppor t 1 flag per reset source to indicate the reset cause.

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ST10F269 and ST10F280 internal reset circuitry is the following: Figure 1 : Internal Reset Circuitry

EINIT Instruction

Clr

Set

Reset State

Machine

Clock

RSTOUT

Internal Reset Signal

Trigger

Clr

Reset Seq uen ce (512 CPU Clock Cycles)

Asynchronous Reset

From/to Exit Powerdown Circuit

SRST instruction watchdog overflow

BDRSTEN

Weak pull-down (~200

RSTIN

RPD

Note: ST10F269 and ST10F 280 internal reset circuitr y is the same as ST10 F168 except that VPP pin

is used only for the timing control during "Return from Powerdown" and to select the type of reset: asynchronous or synchronous type of reset. Pin 84 name is now "RPD" .

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3 - WDTCON NEW FLAGS FOR RESET CAUSES

3.1 - WDTCON Desc rip tion

Compared to ST 10F168, ST10 F269 and ST10 F280 WDTC ON registers have been modified t o indicate the cause of the reset:

Each of the different reset sources is now indicated in the WDTCON register. The indicated bits are cleared with the EINIT instruction. It is thus possible to identify the reset during the initialisation phase.

WDTCON (FFAEh / D7h) SFR Reset Value: 00XXh

1514131211109876543210

WDTREL - - PONR LHWR SHWR SWR WDTR WDTIN

RW HR HR HR HR HR RW

WDTIN Watchdog Timer Input Frequency Selection

‘0’: Input Frequency is f ‘1’: Input Frequency is f

1 - 3

WDTR

1-3

SWR

1-3

SHWR

1-3

LHWR

1- 2-3

PONR

Notes: 1. More tha n one reset indication flag may be set. After EINIT, all flags are clear ed.

2. Power-on is dete ct ed when a risi ng edge from V cc = 0V to Vcc > 2.0V i s recognized on the inter nal 3.3V supply.

3. Those bits cannot be directly modified by software...

Watchdog Timer Reset Indication Flag

Set by the watchdog timer on an overflow. Cleared by a hardware reset or by the SRVWDT instruction.

Software Reset Indication Flag

Set by the SRST execution. Cleared by the EINIT instruction.

Short Hardware Reset Indication Flag

Set by the input Cleared by the EINIT instruction.

Long Hardware Reset Indication Flag

Set by the input RSTIN Cleared by the EINIT instruction.

Power-On (Asynchronous) Reset Indication Flag

Set by the input RSTIN Cleared by the EINIT instruction.

RSTIN.

/2.

CPU

/128.

CPU

if a power-on condition has been detected.

3.2 - Power-on Detection

ST10F269 and ST10F280 have power-on detection circuitry . The PONR flag of WDTCON register is set if the output voltage of the internal 3.3V supply falls below the

threshold (typically 2V) of the power-on detection circuit. This circuit is efficient to detect major failures of the external 5V supply but if the internal 3.3V supply does not drop under 2 volts, the PONR flag is not set. This coul d be the case on fast switch-off / switch-on of the 5V supply. The time need ed for such a sequence to activate the PONR flag depends on the value of the capacitors connected to the supply and on the exact value of the internal threshold of the detection circuit.

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AN1334 - APPLICATION NOTE

3.3 - S u pply Monitorin g

ST10F269 and ST10F280 have on-chip power-on detection circuitry. This circuitry is detecting major failure on the supply and will not generate a reset when the external supply is going out of ST10 circuit specification (either marginally, either for a very short period).

As a consequence, when an exter nal supply monitoring circuit is used, the ta ble of WDTCO N af ter reset becomes:

The following table is showing the value of WDTCON bits for the 6 possible causes of reset:

Reset Source PONR LHWR SHWR SWR WDTR

Power-on Reset (all bit are set) X X X X Power-on after Partial Supply Failure * X X X Long Hardware Reset X X X Short Hardwar e Reset X X Software Reset (only SWR bit is set) X Watchdog Reset XX

* P O NR bit may not be s et for sh ort supply failure.

For Power on reset aft er supply partial failure, asynchronous res e t mu st be used. In case bi-di rectional reset is enabl ed, and if the RSTIN reset, a software reset or a watchdog reset will trigger a Long hardware reset. Thus, Reset Indications flags will be set to indicate a Long Hardware Rese t.

pin is latched l ow after the end of internal reset sequen ce, then a Shor t hardware

4 - RSTOUT PIN

The behaviour or RSTOUT The RSTOUT

pin is dedicated to generate a reset signal for the system components besides the

pin of ST10F269 and ST10F280 is identical to ST10168:

controller itself. RSTOUT For synchronous reset, as the CPU is completing its current bus cycle, RSTOUT

pin is activated once reset conditions are detected.

may be activated before

the internal CPU reset sequence is star ted. RSTOUT

remains activated until the execution of the EINIT instruction. This allows the complete configuration of the controller including its on-chip peripheral units before releasing the reset signal for the external peripherals of the system.

RSTOUT pulses on RSTOUT

will float as long as pins P0L.0 and POL.1 selec t emulation mode or adapt mode ; to avoid

P0L.0 and P0L.1 are latched at the end of the reset sequence (see diagrams showing

sampling point of PORT0 pins).

5 - RESET AND RPD PIN

As explained before, the level on pin RPD (pin 84) defines the reset type when RSTIN – Asynchronous reset: defined by assertion of the RSTIN – Synchronou s reset: defined by assertion of the RSTIN

pin with a low level on RPD pin.

pin with a high level on RPD pin.

is activated:

Then, if RPD is pulled low in synchronous reset, the chip immediatly enters in asynchronous reset.

Synchronous Reset

Advantage: this reset shall be used when short pulses on RSTIN

pin can be applied to generate a circuit

reset during circuit operation.

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