AN1330
Application note
Designing with the L5970D 1A high efficiency DC-DC converter
Introduction
The L5970D is a step-down monolithic power switching regulator capable of delivering up to
1 A at output voltages from 1.235 V to 35 V. The operating input voltage ranges from 4.4 V to
36 V. It has been designed using BCDV technology and the power switching element is
implemented through a P-channel DMOS transistor. It does not require a bootstrap
capacitor, and the duty cycle can range up to 100%. An internal oscillator fixes the switching
frequency at 250 kHz. This minimizes the LC output filter.
A synchronization pin is available for cases where a higher frequency (up to 500 kHz) is
required. Pulse-by-pulse and frequency foldback overcurrent protection offer effective short
circuit protection. Other features are voltage feed-forward, protection against feedback
disconnection, inhibit and thermal shutdown.
Figure 1. Demonstration board
L5970D (SO-8) board dimensions: 23 x 20 mm
Figure 2. Package Figure 3. Pin connection
May 2008 Rev 3 1/31
VCC
8
7
6
5
AM00004v1
GND
VREF
FB
www.st.com
SO-8
OUT
SYNC
INH
COMP
1
2
3
4
Contents AN1330
Contents
1 Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 Power supply and voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2 Voltages monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.3 Oscillator and synchronizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.4 Current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.5 Error amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.6 PWM comparator and power stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.7 Inhibit function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.8 Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3 Additional features and protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1 Feedback disconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2 Output overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.3 Zero load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4 Closing the loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1 Error amplifier and compensation network . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2 LC filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.3 PWM comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.1 Component selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.2 Layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.3 Thermal considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.4 Short-circuit protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.5 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6 Application ideas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2/31
AN1330 Contents
6.1 Positive buck-boost regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.2 Buck-boost regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.3 Dual output voltage with auxiliary winding . . . . . . . . . . . . . . . . . . . . . . . . 27
6.4 Synchronization example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7 Compensation network with MLCC (multiple layer ceramic capacitor) at
the output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.1 External SOFT_START network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3/31
List of figures AN1330
List of figures
Figure 1. Demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2. Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 3. Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 4. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 5. Internal regulator circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 6. Oscillator circuit block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 7. Current limitation circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 8. Driving circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 9. Block diagram of the loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 10. Error amplifier equivalent circuit and compensation network . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 11. Module plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 12. Phase plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 13. Layout example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 14. Short-circuit current (V
Figure 15. Short-circuit current (V
Figure 16. Demonstration board application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 17. PCB layout (component side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 18. PCB layout (bottom side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 19. PCB layout (front side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 20. Junction temperature vs. output current (V
Figure 21. Junction temperature vs. output current (V
Figure 22. Junction temperature vs. output current (V
Figure 23. Efficiency vs. output current (V
Figure 24. Junction temperature vs. output current (V
Figure 25. Positive buck-boost regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 26. Buck-boost regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 27. Dual output voltage with auxiliary winding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 28. Synchronization example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 29. MLCC compensation network example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 30. Soft start network example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
= 25 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
IN
= 30 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
IN
= 5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
CC
= 12 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
CC
= 24 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
= 5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
CC
CC
= 12 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
CC
4/31
AN1330 Pin functions
1 Pin functions
1.1 Pin description
Table 1. Pin description
N. Name Description
1 OUT Regulator output
Master/slave synchronization. When open, a signal synchronous with the turn-OFF of
the internal power is present. When connected to an external signal at a frequency
2 SYNC
3INH
4 COMP E/A output to be used for frequency compensation
5FB
higher than the internal one, then the device is synchronized by the external signal.
Connecting the SYNC pins of two devices, the one with the higher frequency works as
master and the other one works as slave.
A logical signal (active high) disables the device. With an IHN higher than 2.2 V the
device is OFF and with an INH lower than 0.8 V, the device is ON.
If INH is not used the pin must be grounded. When it is open, an internal pull-up
disables the device.
Step-down feedback input. Connecting the output voltage directly to this pin results in
an output voltage of 1.235 V. An external resistor divider is required for higher output
voltages (the typical value for the resistor connected between this pin and ground is
4.7 k).
6V
Reference voltage of 3.3 V. No filter capacitor is needed for stability
REF
7 GND Ground
8V
Unregulated DC input voltage.
CC
1.2 Block diagram
Figure 4. Block diagram
TRIMMING
INH
COMP
FB
1.235V
SYNC
INHIBIT
E/A
-
+
OSCILLATOR
VOLTAGES
MONITOR
PWM
+
-
THERMAL
SHUTDOWN
VCC
SUPPLY
1.235V 3.5V
PEAK TO PEAK
CURRENT LIMIT
DCkQ
DRIVER
FREQUENCY
SHIFTER
GND OUT
V
REF
BUFFER
LPDMOS
POWER
AM00003v1
V
REF
5/31
Functional description AN1330
2 Functional description
The main internal blocks are shown in the device block diagram in Figure 4. They are:
● A voltage regulator supplying the internal circuitry. From this regulator, a 3.3 V
reference voltage is externally available.
● A voltage monitor circuit which checks the input and internal voltages.
● A fully integrated sawtooth oscillator with a frequency of 250 kHz ±15%, including also
the voltage feed forward function and an input/output synchronization pin.
● Two embedded current limitation circuits which control the current that flows through
the power switch. The pulse-by-pulse current limit forces the power switch OFF cycle
by cycle if the current reaches an internal threshold, while the frequency shifter reduces
the switching frequency in order to significantly reduce the duty cycle.
● A transconductance error amplifier.
● A pulse width modulation (PWM) comparator and the relative logic circuitry necessary
to drive the internal power.
● A high side driver for the internal P-MOS switch.
● An inhibit block for standby operation.
● A circuit to implement the thermal protection function.
2.1 Power supply and voltage reference
The internal regulator circuit (shown in Figure 5) consists of a start-up circuit, an internal
voltage Preregulator, the Bandgap voltage reference and the Bias block that provides
current to all the blocks. The Starter gives the start-up currents to the entire device when the
input voltage goes high and the device is enabled (inhibit pin connected to ground). The
Preregulator block supplies the Bandgap cell with a preregulated voltage V
very low supply voltage noise sensitivity.
2.2 Voltages monitor
An internal block continuously senses the VCC, V
their thresholds, the regulator begins operating. There is also a hysteresis on the V
(UVLO).
and VBG. If the voltages go higher than
REF
that has a
REG
CC
6/31
AN1330 Functional description
Figure 5. Internal regulator circuit
V
CC
STARTER
2.3 Oscillator and synchronizer
Figure 6 shows the block diagram of the oscillator circuit.
The Clock Generator provides the switching frequency of the device, which is internally fixed
at 250 kHz. The Frequency Shifter block acts to reduce the switching frequency in case of
strong overcurrent or short circuit. The clock signal is then used in the internal logic circuitry
and is the input of the Ramp Generator and synchronizer blocks.
The Ramp Generator circuit provides the sawtooth signal, used for PWM control and the
internal voltage feed-forward, while the synchronization circuit generates the
synchronization signal. The device also has a synchronization pin which can works both as
Master and Slave.
PREREGULATOR
VREG
BANDGAP
IC BIAS
VREF
AM00006v1
As Master, it serves to synchronize external devices to the internal switching frequency, and
as Slave to synchronize itself using an external signal up to 500 kHz.
In particular, when connecting together two devices the one with the lower switching
frequency works as Slave and the other as Master.
To synchronize the device, the SYNC pin must pass from a low level to a level higher than
the synchronization threshold with a duty cycle that can vary from approximately 10% to
90%, depending also on the signal frequency and amplitude.
The frequency of the synchronization signal must be, at a minimum, higher than the internal
switching frequency of the device (250 kHz).
7/31
Functional description AN1330
Figure 6. Oscillator circuit block diagram
FREQUENCY
FREQUENCY
SHIFTER
Ibias_osc
GENERATOR
GENERATOR
SHIFTER
CLOCK
CLOCK
RAMP
RAMP
GENERATOR
GENERATOR
SYNCHRONIZATOR
SYNCHRONIZER
CLOCK
RAMP
SYNC
t
AM00007v1
2.4 Current protection
The L5970D has two types of current limit protection: pulse-by-pulse and frequency
foldback.
The schematic of the current limitation circuitry for the pulse-by-pulse protection is shown in
Figure 7. The output power PDMOS transistor is split into two parallel PDMOS transistors.
The smallest one includes a resistor in series, R
R
and if reaches the threshold, the mirror becomes unbalanced and the PDMOS is
SENSE
switched off until the next falling edge of the internal clock pulse. Due to this reduction of the
ON time, the output voltage decreases. Since the minimum switch ON time (necessary to
avoid a false overcurrent signal) is too short to obtain a sufficiently low duty cycle at 250
kHz, the output current, in strong overcurrent or short circuit conditions, could increase
again. For this reason the switching frequency is also reduced, thus keeping the inductor
current under its maximum threshold. The Frequency Shifter (Figure 6) functions based on
the feedback voltage. As the feedback voltage decreases (due to the reduced duty cycle),
the switching frequency decreases also.
. The current is sensed through
SENSE
Figure 7. Current limitation circuitry
VCC
RSENSE
A1
PWM
DRIVER
OUT
A1/A2=95
I
OFF
2.5 Error amplifier
The voltage error amplifier is the core of the loop regulation. It is a transconductance
operational amplifier whose non inverting input is connected to the internal voltage
8/31
RTH
I
A2
II
L
NOT
AM00008v1
AN1330 Functional description
reference (1.235 V), while the inverting input (FB) is connected to the external divider or
directly to the output voltage. The output (COMP) is connected to the external compensation
network. The uncompensated error amplifier has the following characteristics:
Table 2. Uncompensated error amplifier characteristics
Description Values
Transconductance 2300 µS
Low frequency gain 65 dB
Minimum sink/source voltage 1500 µA/300 µA
Output voltage swing 0.4 V/3.65 V
Input bias current 2.5 µA
The error amplifier output is compared with the oscillator sawtooth to perform PWM control.
2.6 PWM comparator and power stage
This block compares the oscillator sawtooth and the error amplifier output signals
generating the PWM signal for the driving stage.
The power stage is a highly critical block, as it functions to guarantee a correct turn ON and
turn OFF of the PDMOS. The turn ON of the power element, or more accurately, the rise
time of the current at turn ON, is a very critical parameter. At a first approach, it appears that
the faster the rise time, the lower the turn ON losses. However, there is a limit introduced by
the recovery time of the recirculation diode.
In fact, when the current of the power element is equal to the inductor current, the diode
turns OFF and the drain of the power is able to go high. But during its recovery time, the
diode can be considered a high value capacitor and this produces a very high peak current,
responsible of many problems:
● Spikes on the device supply voltage that cause oscillations (and thus noise) due to the
board parasitics
● Turn ON overcurrent leads to a decrease in the efficiency and system reliability
● Major EMI problems
● Shorter freewheeling diode life
The fall time of the current during the turn OFF is also critical, as it produces voltage spikes
(due to the parasitic elements of the board) that increase the voltage drop across the
PDMOS.
In order to minimize these problems, a new driving circuit topology has been used and the
block diagram is shown in Figure 8. The basic idea is to change the current levels used to
turn the power switch ON and OFF, based on the PDMOS and the gate clamp status.
This circuitry allows the power switch to be turned OFF and ON quickly and addresses the
freewheeling diode recovery time problem. The gate clamp is necessary to avoid that V
the internal switch goes higher than V
max. The ON/OFF Control block protects against
GS
GS
of
any cross conduction between the supply line and ground.
9/31
Functional description AN1330
Figure 8. Driving circuitry
VCC
Vgs
STOP
DRIVE
DRAIN
max
CLAMP
ON/OFF
CONTROL
GATE
OFF
ON
I
OFF
DRAIN
I
ON
PDMOS
ESR
C
VOUT
AM00009v1
I
LOAD
L
2.7 Inhibit function
The inhibit feature is used to put the device in standby mode. With the INH pin higher than
2.2 V the device is disabled and the power consumption is reduced to less than 100 µA.
With the INH pin lower than 0.8 V, the device is enabled. If the INH pin is left floating, an
internal pull up ensures that the voltage at the pin reaches the inhibit threshold and the
device is disabled. The pin is also V
compatible.
CC
2.8 Thermal shutdown
The shutdown block generates a signal that turns OFF the power stage if the temperature of
the chip goes higher than a fixed internal threshold (150 °C). The sensing element of the
chip is very close to the PDMOS area, ensuring fast and accurate temperature detection. A
hysteresis of approximately 20 °C avoids that the devices turns ON and OFF continuously.
10/31
AN1330 Additional features and protection
3 Additional features and protection
3.1 Feedback disconnection
If the feedback is disconnected, the duty cycle increases towards the maximum allowed
value, bringing the output voltage close to the input supply. This condition could destroy the
load.
To avoid this hazardous condition, the device is turned OFF if the feedback pin is left
floating.
3.2 Output overvoltage protection
Overvoltage protection, or OVP, is achieved by using an internal comparator connected to
the feedback, which turns OFF the power stage when the OVP threshold is reached. This
threshold is typically 30% higher than the feedback voltage.
When a voltage divider is required to adjust the output voltage (Figure 14), the OVP
intervention will be set at:
Equation 1
R1R2+
V
OVP
1.3
--------------------- -
• VFB•=
R
2
Where R
R
is between the feedback pin and ground.
2
is the resistor connected between the output voltage and the feedback pin, and
1
3.3 Zero load
Due to the fact that the internal power is a PDMOS, no bootstrap capacitor is required and
so the device works properly even with no load at the output. In this condition it works in
burst mode, with random burst repetition rate.
11/31
Closing the loop AN1330
4 Closing the loop
Figure 9. Block diagram of the loop
4.1 Error amplifier and compensation network
The output L-C filter of a step-down converter contributes with 180 degrees phase shift in
the control loop. For this reason a compensation network between the COMP pin and
GROUND is added. The simplest compensation network together with the equivalent circuit
of the error amplifier are shown in Figure 10. R
open loop gain. C
does not significantly affect system stability but it is useful to reduce the
P
noise of the COMP pin.
The transfer function of the error amplifier and its compensation network is:
Equation 2
A
V0
Where A
A0s()
= Gm · R
vo
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------=
2
s
R0• C0Cp+()RcCcsR0Cc• R0C0Cp+()RcCc•+•+()1+•+•••
o
and CC introduce a pole and a zero in the
C
1s+ RcCc••()•
12/31
AN1330 Closing the loop
Figure 10. Error amplifier equivalent circuit and compensation network
The poles of this transfer function are (if C
Equation 3
Equation 4
where the zero is defined as:
Equation 5
is the low frequency which sets the bandwidth, while the zero FZ1 is usually put near to
F
P1
the frequency of the double pole of the L-C filter (see below). F
frequency.
4.2 LC filter
The transfer function of the L-C filter is given by:
Equation 6
A
LC
s()
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------=
s2LC
OUT
>> C0+CP):
c
-------------------------------------=
F
P1
F
------------------------------------------------------- -=
P2
2 π• R
F
Z1
R
LOAD
ESR R
+()s ESR C
LOAD
• Cc•
2 π• R
• C0Cp+()•
c
-------------------------------------=
• Cc•
2 π• R
1 ESR C
1
0
1
1
c
is usually at a very high
P2
s••+()•
OUT
• R
OUT
LOAD
L+•()R
+•+•••
LOAD
where R
If R
LOAD
is defined as the ratio between V
LOAD
OUT
and I
OUT
.
>>ESR, the previous expression of ALC can be simplified and becomes:
13/31
Closing the loop AN1330
Equation 7
ALCs()
----------------------------------------------------------------------------------------------=
LC
1 ESR C
• s2ESR C
OUT
• s•+
OUT
• s1+•+•
OUT
The zero of this transfer function is given by:
Equation 8
F
--------------------------------------------------- -=
O
2 π• ESR• C
F
is the zero introduced by the ESR of the output capacitor and it is very important to
0
1
•
OUT
increase the phase margin of the loop.
The poles of the transfer function can be calculated through the following expression:
Equation 9
F
PLC1 2,
ESR C
--------------------------------- ---------------------------------------------------------- -----------------------------------------------=
OUT
ESR C
•()
2L• C
•
OUT
OUT
2
4L• C
•–±•–
OUT
In the denominator of A
LC
Equation 10
If the damping coefficient δ is very close to zero, the roots of the equation become a double
root whose value is ω
Similarly, for A
LC
.
n
the poles can usually be defined as a double pole whose value is:
Equation 11
4.3 PWM comparator
The PWM gain is given by the following formula:
Equation 12
where V
OSCMAX
minimum value. A voltage feed forward is implemented to ensure a constant GPWM. This is
obtained by generating a sawtooth waveform directly proportional to the input voltage V
is the maximum value of a sawtooth waveform and V
the typical second order system equation can be recognized:
s22 δ•ω
F
PLC
G
PWM
s()
• s ω
n
----------------------------------------------=
2 π• LC
-------------------------------------------------------------=
V
OSCMAXVOSCMIN
2
+•+
n
1
••
OUT
V
cc
–()
OSCMIN
is the
CC
.
Equation 13
V
OSCMAXVOSCMIN
Where K is equal to 0.076. Therefore the PWM gain is also equal to:
Equation 14
G
PWM
14/31
– KV
1
s()
--- - const==
K
•=
CC
AN1330 Closing the loop
This means that even if the input voltage changes, the error amplifier does not change its
value to keep the loop in regulation, thus ensuring a better line regulation and line transient
response.
To sum up the Open Loop Gain can be written as:
Equation 15
R
2
Gs() G
PWM
s()
--------------------
• AOs()• ALC• s()=
R1R2+
Example:
Considering R
If L = 22 µH, C
Finally R
F
= 9 Hz
P1
F
= 256 kHz
P2
F
= 2.68 kHz
Z1
F
PLC
F
= 19.89 kHz
0
= 5.6 kΩ and R2 = 3.3 kΩ.
1
= 2.7 kΩ, CC = 22 nF and CP = 220 pF, the poles and zeroes of A0 are:
C
= 100 µF and ESR = 80 mΩ, the poles and zeroes of ALC become:
OUT
= 3.39 kHz
The gain and phase bode diagrams are plotted respectively in Figure 11 and Figure 12.
Figure 11. Module plot
15/31
Closing the loop AN1330
Figure 12. Phase plot
The cut-off frequency and the phase margin are:
Equation 16
F
22.8kHz=
C
Phase margin = 39.8°
16/31
AN1330 Application information
5 Application information
5.1 Component selection
● Input capacitor
The input capacitor must be able to withstand the maximum input operating voltage and the
maximum RMS input current.
Since step-down converters draw current from the input in pulses, the input current is
squared and the height of each pulse is equal to the output current. The input capacitor has
to absorb all this switching current, which can be up to the load current divided by two (worst
case, with duty cycle of 50%). For this reason, the quality of these capacitors has to be very
high to minimize the power dissipation generated by the internal ESR, thereby improving
system reliability and efficiency. The critical parameter is usually the RMS current rating,
which must be higher than the RMS input current.
The maximum RMS input current (flowing through the input capacitor) is:
Equation 17
2
2
D
-------+
η
I
RMSIO
•=
----------------- -–
η
2D
•
D
Where η is the expected system efficiency, D is the duty cycle and I
the output DC current.
O
This function reaches its maximum value at D = 0.5 and the equivalent RMS current is equal
to I
divided by 2 (considering η = 1). The maximum and minimum duty cycles are:
O
Equation 18
V
V
+
OUTVF
--------------------------------------- -
V
INMINVSW
–
=
Where V
D
MAX
is the freewheeling diode forward voltage and VSW the voltage drop across the
F
internal PDMOS. Considering the range D
I
going through the input capacitor. Capacitors that can be considered are:
RMS
MIN
and
to D
D
=
-----------------------------------------
MIN
V
INMAXVSW
, it is possible to determine the max
MAX
+
OUTVF
–
– Electrolytic capacitors: These are widely used due to their low price and their
availability in a wide range of RMS current ratings. The only drawback is that,
considering ripple current rating requirements, they are physically larger than
other capacitors.
– Ceramic capacitors: If available for the required value and voltage rating, these
capacitors usually have a higher RMS current rating for a given physical dimension
(due to very low ESR). The drawback is the considerably high cost.
– Tantalum capacitors: Good, small tantalum capacitors with very low ESR are
becoming more available. However, they can occasionally burn if subjected to very
high current during charge. Therefore, it is better to avoid this type of capacitor for
the input filter of the device. They can, however, be subjected to high surge current
when connected to the power supply.
● Output capacitor
The output capacitor is very important to meet the output voltage ripple requirement.
Using a small inductor value is useful to reduce the size of the choke but it increases the
current ripple. So, to reduce the output voltage ripple, a low ESR capacitor is required.
17/31
Application information AN1330
Nevertheless, the ESR of the output capacitor introduces a zero in the open loop gain,
which helps to increase the phase margin of the system. If the zero goes to a very high
frequency, its effect is negligible. For this reason, ceramic capacitors and very low ESR
capacitors in general should be avoided.
Tantalum and electrolytic capacitors are usually a good choice for this purpose.
Ta bl e 3 below provides a list of some tantalum capacitor manufacturers.
Table 3. Output capacitor selection
Manufacturer Series Cap value (µF) Rated voltage (V) ESR (mΩ)
AVX TPS 100 to 470 4 to 35 50 to 200
KEMET T494/5 100 to 470 4 to 20 30 to 200
Sanyo POSCAP
Sprague 595D 220 to 390 4 to 20 160 to 650
1. POSCAP capacitors have characteristic very similar to tantalum capacitors.
● Inductor
(1)
TPA/B/C 100 to 470 4 to 16 40 to 80
The inductor value is very important because it fixes the ripple current flowing through
output capacitor.
The ripple current is usually fixed at 20-40% of I
max, which is 0.2 - 0.4 A with IOmax = 1 A.
O
The approximate inductor value is obtained using the following formula:
Equation 19
V
–()
INVOUT
-------------------------------------- -
where T
is the ON time of the internal switch, given by D · T.
ON
For example, with V
L
= 3.3 V, VIN = 12 V and ∆IO = 0.3 A, the inductor value is about
OUT
I∆
T
•=
ON
35 µH.
The peak current through the inductor is given by:
Equation 20
I
PKIO
I∆
---- -+=
2
and it can be observed that if the inductor value decreases, the peak current (which must be
lower than the current limit of the device) increases. So, when the peak current is fixed, a
higher inductor value allows a higher value for the output current.
In Table 4: Inductor selection, some inductor manufacturers are listed.
Table 4. Inductor selection
Manufacturer Series Inductor value (µH) Saturation current (A)
Coilcraft
18/31
DO1813HC 22 to 33 1 to 1.2
DO3316 33 to 47 1.6 to 2
AN1330 Application information
Table 4. Inductor selection (continued)
Manufacturer Series Inductor value (µH) Saturation current (A)
Coiltronics
UP1B 22 to 33 1 to 1.2
UP2B 33 to 47 1.7 to 2
HM76-2 22 to 33 1 to 1.2
BI
HM76-3 33 to 47 2 to 2.5
Murata LQN6C 22 to 33 0.9 to 1.2
Panasonic ELLATV 22 to 47 1.4 to 2.05
Sumida CR75 22 to 33 1.2 to 1.5
Epcos B82476 33 to 47 1.6 to 2
Wurth Elektronik 744561 33 to 47 1.6 to 2
5.2 Layout considerations
The layout of switching DC-DC converters is very important to minimize noise and
interference. Power-generating portions of the layout are the main cause of noise and so
high switching current loop areas should be kept as small as possible and lead lengths as
short as possible.
High impedance paths (in particular the feedback connections) are susceptible to
interference, so they should be as far as possible from the high current paths. A layout
example is provided in Figure 13 below.
The input and output loops are minimized to avoid radiation and high frequency resonance
problems. The feedback pin connections to the external divider are very close to the device
to avoid pick-up noise. Moreover the GND pin of the device is connected to the ground plane
directly with VIA on the bottom side of the PCB.
Figure 13. Layout example
COMPENSATION NETWORK FAR
FROM HIGH CU RRENT PATHS
MINIMUN SIZ E OF FEEDBAC K
PIN CONNECTIONS TO AVOID
PICKUP
R2
R1
CONNECTION TO
GROUNDPL ANE
THROUGH VIA
VERY SMALL HIGH CURRENT
CIRCULATING PATH T O MINIMIZE
RADIATION AND HIGH FREQUENCY
RESONANCE PROBLEMS
Vin Vout
to output voltage
L5970
8
Cin D Cou t
Inhibit signal
45
1
AM00012v1
L
Gnd
OUTPUT CAPACITOR
DIRECTLY CON NECTED
TO HEAVY GROUND
19/31
Application information AN1330
5.3 Thermal considerations
The dissipated power of the device is tied to three different sources:
● switching losses due to the not negligible R
Equation 21
P
ON
R
DS on()IOUT
Where D is the duty cycle of the application. Note that the duty cycle is theoretically given by
the ratio between V
and VIN, but in practice it is substantially higher than this value to
OUT
compensate for the losses of the overall application. For this reason, the switching losses
related to the R
● Switching losses due to turning ON and OFF. These are derived using the following
increase compared to an ideal case.
DSON
equation:
Equation 22
T
+()
ONTOFF
P
SWVINIOUT
•
---------------------------------------- -
• FSW• VINI
2
. These are equal to:
DSON
()
• D•=
2
• TSW• FSW•==
OUT
where T
current flowing into it during the turn ON and turn OFF phases. T
ON
and T
are the overlap times of the voltage across the power switch and the
OFF
is the equivalent
SW
switching time.
● Quiescent current losses.
Equation 23
P
VINIQ•=
Q
Where I
● Example:
R
DSON
is the quiescent current.
Q
–V
–V
–I
IN
OUT
OUT
= 5 V
= 3.3 V
= 1 A
has a typical value of 0.25 Ω @ 25 °C and increases up to a maximum value of 0.5 Ω
@ 150 °C. We can consider a value of 0.4 Ω.
T
is approximately 120 ns. IQ has a typical value of 2.5 mA @ VIN = 12 V. The overall
SW
losses are:
Equation 24
P
TOT
R
DSONIOUT
0.4 120.7 5 1 120 109–250 10352.5103–0.44W≅⋅⋅+⋅⋅ ⋅ ⋅ ⋅+⋅⋅
()2DVINI
OUTTSWFSWVINIQ
=⋅+⋅⋅⋅+⋅⋅=
The junction temperature of the device will be:
Equation 25
T
J
where T
is the ambient temperature and Rth
A
ambient.
20/31
TARth
+=
J-A
P•
JA–
TOT
is the thermal resistance junction-to-
AN1330 Application information
Considering the device in an SO-8 package mounted on the board with a good groundplane,
that it has a thermal resistance-junction to-ambient (Rth
) of about 115 °C/W and an
J-A
ambient temperature of about 70 °C.
Equation 26
TJ70 0.44 115 121°C≅•+=
5.4 Short-circuit protection
In overcurrent protection mode, when the peak current reaches the current limit, the device
reduces the T
frequency to approximately one third of its nominal value (see Section 2.4: Current
protection). In these conditions, the duty cycle is strongly reduced and, in most of
applications, this is enough to limit the current to I
circuit at the output (V
parasitic effect of external components) the current peak could reach values higher than
I
.
LIM
This can be understood considering the inductor current ripple during the ON and OFF
phases:
● ON phase
down to its minimum value (approximately 250 ns) and the switching
ON
. In any event, in case of heavy short-
=0 V) and depending on the application conditions (VCC value and
OUT
LIM
Equation 27
● OFF phase
VINV
-------------------------------------------------------------------- -
IL∆
DCRLI•––()
out
L
T
•=
ON
Equation 28
where V
VDV
------------------------------------------------------------------
IL∆
is the voltage drop across the diode, and DCRL is the series resistance of the
D
out
L
DCR
I•++()
L
T
•=
OFF
inductor.
In short-circuit conditions, V
is negligible. So, during the T
OUT
, the voltage applied to the
OFF
inductor is very small and it may be that the current ripple in this phase does not
compensate for the current ripple during the T
The maximum current peak can be easily measured through the inductor with V
(short-circuit) and V
CC=VIN
max. In cases where the application must sustain the short-
ON
.
=0 V
OUT
circuit condition for an extended period, the external components (mainly the inductor and
diode) must be selected based on this value.
21/31
Application information AN1330
Figure 14. Short-circuit current (VIN = 25 V)
Figure 15. Short-circuit current (V
In Figure 14 and Figure 15, for example, it can be observed that when the input voltage
increases for a given component list, the current peak increases also. The current limit is
immediately triggered but the current peak increases until the current ripple during the T
is equal to the current ripple during the T
5.5 Application circuit
Figure 16 shows the demonstration board application circuit for the device in the SMD
version, where the input supply voltage, V
voltage of the input capacitor and the output voltage is adjustable from 1.235 V to V
= 30 V)
IN
.
ON
, can range from 4.4 V to 25 V due to the rated
CC
CC
.
OFF
22/31
AN1330 Application information
Figure 16. Demonstration board application circuit
VIN = 4.4V to 25V
C1
10∝F
25V
CERAMIC
3.3V
C4
22nF
C3
220pF
VREF
VCC
SYNC.
COMP
R3
4.7K
6
8
2
4
INH.
L5970D
3
1
5
7
GND
OUT
FB
L1 33∝H
D1
STPS2L25U
AM00017v1
R1
5.6K
R2
3.3K
VOUT=3.3V
C2
100∝F
10V
Table 5. Component list
Reference Part number Description Manufacturer
C1 GRM32DR61E106KA12L 10 µF, 25 V Murata
C2 POSCAP 10TPB100M 100 µF, 10 V Sanyo
C3 C1206C221J5GAC 220 pF, 5%, 50 V KEMET
C4 C1206C223K5RAC 22 nF, 10%, 50 V KEMET
R1 5.6 K, 1%, 0.1 W 0603 Neohm
R2 3.3 K, 1%, 0.1 W 0603 Neohm
R3 4.7 K, 1%, 0.1 W 0603 Neohm
D1 STPS2L25U 2 A, 25 V STMicroelectronics
L1 DO3316P-333 33 µH, 2 A Coilcraft
Figure 17. PCB layout (component side)
L5970D
EVAL.BOARD
R2
R3
REF
R1
VIN
U1
C1
D1
GND
www.st.com
C3
C4
L1
VOUT
C2
AM00018v1
R
INH
SYN
GND.
23/31
Application information AN1330
Figure 18. PCB layout (bottom side)
AM00019v1
Figure 19. PCB layout (front side)
Below, some graphs are provided which show the T
and output voltage conditions, as well as some efficiency measurements.
Figure 20. Junction temperature vs. output
Tj(°C)
current (V
130
120
110
100
90
80
Vcc=5V
Tamb=25°C
70
60
50
40
30
20
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6
24/31
CC
Io(A)
= 5 V)
Vo=3.3V
Vo=2.5V
Vo=1.8V
AM00020v1
versus output current in different input
j
Figure 21. Junction temperature vs. output
current (V
Tj(°C)
130
120
110
100
Vcc=12V
90
Tamb=25°C
80
70
60
50
40
30
20
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6
CC
Io(A)
= 12 V)
Vo=5V
Vo=3.3V
Vo=2.5V
AN1330 Application information
Figure 22. Junction temperature vs. output
Tj(°C)
140
120
100
80
60
40
20
0
current (V
Vcc=24V
Tamb=25°C
0.2 0.4 0.6 0.8 1 1.2 1.4
= 24 V)
CC
Vo=18V
Io(A)
Vo=12V
Vo=5V
Figure 23. Efficiency vs. output current (V
5 V)
94
92
90
88
86
84
82
80
Efficiency (%)
78
76
74
Vcc=5V
72
70
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Figure 24. Junction temperature vs. output current (VCC = 12 V)
92
90
88
86
84
82
80
78
Efficiency (%)
76
74
72
70
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Vo=5V
Vo=3.3V
Vo=2.5V
Vcc=12V
Io (A)
Vo=3.3V
Vo=2.5V
Vo=1.8V
Io (A)
CC
=
25/31
Application ideas AN1330
6 Application ideas
6.1 Positive buck-boost regulator
The device can be used to implement a step-up/down converter with a positive output
voltage. Figure 25 below shows the schematic diagram of this topology for an output voltage
of 12 V.
The input voltage can range from 5 V and 35 V. The output voltage is given by V
D/(1-D), where D is duty cycle. The maximum output current is given by I
current capability is reduced by the term (1-D) and so, for example, with a duty cycle of 0.5,
the maximum output current deliverable to the load is 0.5 A. This is due to the fact that the
current flowing trough the internal power switch is delivered to the output only during the
OFF phase.
Figure 25. Positive buck-boost regulator
VIN=5V
C1
10uF
C2
25V
220pF
Ceramic
Vin=5V Vout=12V Iout=0.3A Efficiency=76%
C3
22nF
R3
4.7k
VCC
COMP
8
4
2
SYNC VREF
L5970
6.2 Buck-boost regulator
In Figure 26, the schematic circuit for a standard buck-boost topology is shown. The output
voltage is given by V
D), for the same reason as that of the up-down converter. An important thing to take into
account is that the ground pin of the device is connected to the negative output voltage.
Therefore, the device is subjected to a voltage equal to V
V (the maximum operating input voltage).
= - VIN · D/(1-D). The maximum output current is equal to I
O
3.3V
·
O=VIN
=1× (1-D). The
OUT
L1
OUT
GND
1
D1
STPS2L25U
FB
5
3
7
INH
U1
6
33uH
IN-VO
D2
STPS2L25U
M1
STN4NE03L
24k
2.7k
VOUT=12V/0.3A
C4
100uF
16V
OUT
=1 · (1-
, that has to be lower than 36
Figure 26. Buck-boost regulator
26/31
AN1330 Application ideas
6.3 Dual output voltage with auxiliary winding
When two output voltages are required, it is possible to create a dual output voltage
converter by using a coupled inductor. During the ON phase, the current is delivered to
V
while D2 is reverse-biased.
OUT
During the OFF phase, the current is delivered through the auxiliary winding to the output
voltage V
be certain that the application is working properly, the load related to the second output
V
should be much lower than the load related to V
OUT1
Figure 27. Dual output voltage with auxiliary winding
. This is possible only if the magnetic core has stored sufficient energy. So, to
OUT1
.
OUT
6.4 Synchronization example
Two or more devices (up to 6) can be synchronized simply by connecting the
synchronization pins. In this case, the device with a slightly higher switching frequency value
will work as master and the ones with a slightly lower switching frequency values will work
as a slaves.
The device can also be synchronized from an external source. In this case the logic signal
must have a frequency higher than the internal switching frequency of the device (250 kHz).
Figure 28. Synchronization example
27/31
Compensation network with MLCC (multiple layer ceramic capacitor) at the output AN1330
7 Compensation network with MLCC (multiple layer
ceramic capacitor) at the output
MLCCs with values in the range of 10 µF-22 µF and rated voltages in the range of 10 V-25 V
are available today at relatively low cost from many manufacturers.
These capacitors have very low ESR values (a few mΩ) and thus are occasionally used for
the output filter in order to reduce the voltage ripple and the overall size of the application.
However, a very low ESR value affects the compensation of the loop (see Section 4: Closing
the loop) and in order to keep the system stable, a more complicated compensation network
may be required. Figure 29 shows an example of a compensation network that stabilizes the
system with ceramic capacitors at the output (the optimum component value depends on
the application).
Figure 29. MLCC compensation network example
7.1 External SOFT_START network
At the start-up, the device can quickly increase the current up to the current limit in order to
charge the output capacitor. If a soft ramp-up of the output voltage is required, an external
soft-start network can be implemented as shown in Figure 30.
The capacitor C is charged up to an external reference (through R), and the B
COMP pin.
This clamps the duty cycle, limiting the slew rate of the output voltage.
28/31
clamps the
JT
AN1330 Compensation network with MLCC (multiple layer ceramic capacitor) at the output
Figure 30. Soft start network example
33uH
33uH
Coilcraft
VIN=4.4V to 25V
VIN=4.4V to 25V
C1
C1
10uF
10uF
25V
25V
CERAMIC
CERAMIC
VREF
VREF
VREF
R=4K7
R=4K7
R=4K7
Css=2.7nF
Css=2.7nF
BC327
BC327
C4=22nF
C4=22nF
C3=220pF
C3=220pF
Vcc
Vcc
VREF
VREF
COMP
COMP
SYNC
SYNC
R3=4.7K
R3=4.7K
OUT
8
8
6
6
L5970D
L5970D
4
4
2
2
GND
GND
7
7
OUT
1
1
5
5
3
3
INH
INH
D1
D1
FB
FB
Coilcraft
STPS2L25U
STPS2L25U
AM00026v1
L1
L1
R2=3.3K
R2=3.3K
R1=5.6K
R1=5.6K
VOUT=3.3V
VOUT=3.3V
C2
C2
100uF
100uF
10V
10V
29/31
Revision history AN1330
8 Revision history
Table 6. Document revision history
Date Revision Changes
– the document has been reformatted
22-May-2007 2
19-May-2008 3
– Section 4: Closing the loop modified
– Minor text changes
– Restructured document sections
– Minor text changes
30/31
AN1330
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