ST AN1330 Application note

AN1330

Application note

Designing with the L5970D 1A high efficiency DC-DC converter

Introduction

The L5970D is a step-down monolithic power switching regulator capable of delivering up to 1 A at output voltages from 1.235 V to 35 V. The operating input voltage ranges from 4.4 V to 36 V. It has been designed using BCDV technology and the power switching element is implemented through a P-channel DMOS transistor. It does not require a bootstrap capacitor, and the duty cycle can range up to 100%. An internal oscillator fixes the switching frequency at 250 kHz. This minimizes the LC output filter.

A synchronization pin is available for cases where a higher frequency (up to 500 kHz) is required. Pulse-by-pulse and frequency foldback overcurrent protection offer effective short circuit protection. Other features are voltage feed-forward, protection against feedback disconnection, inhibit and thermal shutdown.

Figure 1. Demonstration board

L5970D (SO-8) board dimensions: 23 x 20 mm

Figure 2. Package		Figure 3. Pin connection
		OUT	1	8	VCC
		SYNC	2	7	GND
		INH	3	6	VREF
	SO-8	COMP	4	5	FB
				AM00004v1
May 2008		Rev 3			1/31

www.st.com

Contents	AN1330

Contents

1	Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 5
	1.1	Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	5
	1.2	Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	5
2	Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		6
	2.1	Power supply and voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	6
	2.2	Voltages monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	6
	2.3	Oscillator and synchronizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	7
	2.4	Current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	8
	2.5	Error amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	8
	2.6	PWM comparator and power stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	9
	2.7	Inhibit function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	10
	2.8	Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	10
3	Additional features and protection . . . . . . . . . . . . . . . . . . . . . . . . . . . .		11

3.1 Feedback disconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.2 Output overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.3 Zero load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4	Closing the loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		12
	4.1	Error amplifier and compensation network . . . . . . . . . . . . . . . . . . . . . . . .	12
	4.2	LC filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	13
	4.3	PWM comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	14

5	Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		17
	5.1	Component selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	17
	5.2	Layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	19
	5.3	Thermal considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	20
	5.4	Short-circuit protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	21
	5.5	Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	22
6	Application ideas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		26

2/31

AN1330			Contents
	6.1	Positive buck-boost regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . 26
	6.2	Buck-boost regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 26
	6.3	Dual output voltage with auxiliary winding . . . . . . . . . . . . . . . . . . . .	. . . . 27
	6.4	Synchronization example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 27
7	Compensation network with MLCC (multiple layer ceramic capacitor) at
	the output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . 28
	7.1	External SOFT_START network . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 28
8	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . 30

3/31

List of figures	AN1330

List of figures

Figure 1. Demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2. Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 3. Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 4. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 5. Internal regulator circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 6. Oscillator circuit block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 7. Current limitation circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 8. Driving circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 9. Block diagram of the loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 10. Error amplifier equivalent circuit and compensation network . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 11. Module plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 12. Phase plot. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 13. Layout example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 14. Short-circuit current (VIN = 25 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 15. Short-circuit current (VIN = 30 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 16. Demonstration board application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 17. PCB layout (component side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 18. PCB layout (bottom side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 19. PCB layout (front side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 20. Junction temperature vs. output current (VCC = 5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 21. Junction temperature vs. output current (VCC = 12 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 22. Junction temperature vs. output current (VCC = 24 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 23. Efficiency vs. output current (VCC = 5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 24. Junction temperature vs. output current (VCC = 12 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 25. Positive buck-boost regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 26. Buck-boost regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 27. Dual output voltage with auxiliary winding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 28. Synchronization example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 29. MLCC compensation network example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 30. Soft start network example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4/31

AN1330	Pin functions

1 Pin functions

1.1Pin description

	Table 1.		Pin description
	N.	Name	Description
	1	OUT	Regulator output
			Master/slave synchronization. When open, a signal synchronous with the turn-OFF of
			the internal power is present. When connected to an external signal at a frequency
	2	SYNC	higher than the internal one, then the device is synchronized by the external signal.
			Connecting the SYNC pins of two devices, the one with the higher frequency works as
			master and the other one works as slave.
			A logical signal (active high) disables the device. With an IHN higher than 2.2 V the
	3	INH	device is OFF and with an INH lower than 0.8 V, the device is ON.
			If INH is not used the pin must be grounded. When it is open, an internal pull-up
			disables the device.
	4	COMP	E/A output to be used for frequency compensation
			Step-down feedback input. Connecting the output voltage directly to this pin results in
	5	FB	an output voltage of 1.235 V. An external resistor divider is required for higher output
			voltages (the typical value for the resistor connected between this pin and ground is
			4.7 k).
	6	VREF	Reference voltage of 3.3 V. No filter capacitor is needed for stability
	7	GND	Ground
	8	VCC	Unregulated DC input voltage.

1.2Block diagram

Figure 4. Block diagram

				VCC
TRIMMING		VOLTAGES
		MONITOR			VREF
						VREF
			SUPPLY
					BUFFER
		THERMAL
		SHUTDOWN	1.235V 3.5V
INH	INHIBIT
			PEAK TO PEAK
COMP			CURRENT LIMIT
FB	E/A	PWM
	-		D Q
	+	+
		-	Ck	DRIVER
1.235V
				LPDMOS
				POWER
SYNC	OSCILLATOR		FREQUENCY
			SHIFTER
			GND	OUT	AM00003v1

5/31

Functional description	AN1330

2 Functional description

The main internal blocks are shown in the device block diagram in Figure 4. They are:

●A voltage regulator supplying the internal circuitry. From this regulator, a 3.3 V reference voltage is externally available.

●A voltage monitor circuit which checks the input and internal voltages.

●A fully integrated sawtooth oscillator with a frequency of 250 kHz ±15%, including also the voltage feed forward function and an input/output synchronization pin.

●Two embedded current limitation circuits which control the current that flows through the power switch. The pulse-by-pulse current limit forces the power switch OFF cycle by cycle if the current reaches an internal threshold, while the frequency shifter reduces the switching frequency in order to significantly reduce the duty cycle.

●A transconductance error amplifier.

●A pulse width modulation (PWM) comparator and the relative logic circuitry necessary to drive the internal power.

●A high side driver for the internal P-MOS switch.

●An inhibit block for standby operation.

●A circuit to implement the thermal protection function.

2.1Power supply and voltage reference

The internal regulator circuit (shown in Figure 5) consists of a start-up circuit, an internal voltage Preregulator, the Bandgap voltage reference and the Bias block that provides current to all the blocks. The Starter gives the start-up currents to the entire device when the input voltage goes high and the device is enabled (inhibit pin connected to ground). The Preregulator block supplies the Bandgap cell with a preregulated voltage VREG that has a very low supply voltage noise sensitivity.

2.2Voltages monitor

An internal block continuously senses the VCC, VREF and VBG. If the voltages go higher than their thresholds, the regulator begins operating. There is also a hysteresis on the VCC (UVLO).

6/31

AN1330	Functional description
Figure 5. Internal regulator circuit
VCC
STARTER	PREREGULATOR
	VREG
	BANDGAP

IC BIAS

VREF

AM00006v1

2.3Oscillator and synchronizer

Figure 6 shows the block diagram of the oscillator circuit.

The Clock Generator provides the switching frequency of the device, which is internally fixed at 250 kHz. The Frequency Shifter block acts to reduce the switching frequency in case of strong overcurrent or short circuit. The clock signal is then used in the internal logic circuitry and is the input of the Ramp Generator and synchronizer blocks.

The Ramp Generator circuit provides the sawtooth signal, used for PWM control and the internal voltage feed-forward, while the synchronization circuit generates the synchronization signal. The device also has a synchronization pin which can works both as Master and Slave.

As Master, it serves to synchronize external devices to the internal switching frequency, and as Slave to synchronize itself using an external signal up to 500 kHz.

In particular, when connecting together two devices the one with the lower switching frequency works as Slave and the other as Master.

To synchronize the device, the SYNC pin must pass from a low level to a level higher than the synchronization threshold with a duty cycle that can vary from approximately 10% to 90%, depending also on the signal frequency and amplitude.

The frequency of the synchronization signal must be, at a minimum, higher than the internal switching frequency of the device (250 kHz).

7/31

Functional description	AN1330

Figure 6. Oscillator circuit block diagram

FREQUENCY
FREQUENCY
SHIFTER
SHIFTER		CLOCK
		t
Ibias_osc
CLOCK	RAMPP
CLOCK
GENERATOR	GENERATOR
GENERATOR	GENERATOR	RAMP
	SYNCHRONIZATORSYNCHRONIZER	SYNC

AM00007v1

2.4Current protection

The L5970D has two types of current limit protection: pulse-by-pulse and frequency foldback.

The schematic of the current limitation circuitry for the pulse-by-pulse protection is shown in Figure 7. The output power PDMOS transistor is split into two parallel PDMOS transistors. The smallest one includes a resistor in series, RSENSE. The current is sensed through

RSENSE and if reaches the threshold, the mirror becomes unbalanced and the PDMOS is switched off until the next falling edge of the internal clock pulse. Due to this reduction of the

ON time, the output voltage decreases. Since the minimum switch ON time (necessary to avoid a false overcurrent signal) is too short to obtain a sufficiently low duty cycle at 250 kHz, the output current, in strong overcurrent or short circuit conditions, could increase again. For this reason the switching frequency is also reduced, thus keeping the inductor current under its maximum threshold. The Frequency Shifter (Figure 6) functions based on the feedback voltage. As the feedback voltage decreases (due to the reduced duty cycle), the switching frequency decreases also.

Figure 7. Current limitation circuitry

VCC
RSENSE			RTH
IOFF
DRIVER
A1	A2		IL
OUT
A1/A2=95
	I	I	NOT

PWM

AM00008v1

2.5Error amplifier

The voltage error amplifier is the core of the loop regulation. It is a transconductance operational amplifier whose non inverting input is connected to the internal voltage

8/31

AN1330	Functional description

reference (1.235 V), while the inverting input (FB) is connected to the external divider or directly to the output voltage. The output (COMP) is connected to the external compensation network. The uncompensated error amplifier has the following characteristics:

Table 2.	Uncompensated error amplifier characteristics
	Description	Values
	Transconductance	2300 µS
Low frequency gain			65 dB
Minimum sink/source voltage		1500	µA/300 µA
Output voltage swing		0.4	V/3.65 V
	Input bias current	2.5 µA

The error amplifier output is compared with the oscillator sawtooth to perform PWM control.

2.6PWM comparator and power stage

This block compares the oscillator sawtooth and the error amplifier output signals generating the PWM signal for the driving stage.

The power stage is a highly critical block, as it functions to guarantee a correct turn ON and turn OFF of the PDMOS. The turn ON of the power element, or more accurately, the rise time of the current at turn ON, is a very critical parameter. At a first approach, it appears that the faster the rise time, the lower the turn ON losses. However, there is a limit introduced by the recovery time of the recirculation diode.

In fact, when the current of the power element is equal to the inductor current, the diode turns OFF and the drain of the power is able to go high. But during its recovery time, the diode can be considered a high value capacitor and this produces a very high peak current, responsible of many problems:

●Spikes on the device supply voltage that cause oscillations (and thus noise) due to the board parasitics

●Turn ON overcurrent leads to a decrease in the efficiency and system reliability

●Major EMI problems

●Shorter freewheeling diode life

The fall time of the current during the turn OFF is also critical, as it produces voltage spikes (due to the parasitic elements of the board) that increase the voltage drop across the PDMOS.

In order to minimize these problems, a new driving circuit topology has been used and the block diagram is shown in Figure 8. The basic idea is to change the current levels used to turn the power switch ON and OFF, based on the PDMOS and the gate clamp status.

This circuitry allows the power switch to be turned OFF and ON quickly and addresses the freewheeling diode recovery time problem. The gate clamp is necessary to avoid that VGS of the internal switch goes higher than VGSmax. The ON/OFF Control block protects against any cross conduction between the supply line and ground.

9/31

	Functional description		AN1330
	Figure 8. Driving circuitry
		VCC
	Vgsmax
		IOFF
	CLAMP	GATE
		PDMOS
		DRAIN	VOUT
	STOP	L
		OFF
	ON/OFF		ILOAD
	DRIVE CONTROL	ESR
	DRAIN	ON
		C
		ION
			AM00009v1

2.7Inhibit function

The inhibit feature is used to put the device in standby mode. With the INH pin higher than 2.2 V the device is disabled and the power consumption is reduced to less than 100 A. With the INH pin lower than 0.8 V, the device is enabled. If the INH pin is left floating, an internal pull up ensures that the voltage at the pin reaches the inhibit threshold and the device is disabled. The pin is also VCC compatible.

2.8Thermal shutdown

The shutdown block generates a signal that turns OFF the power stage if the temperature of the chip goes higher than a fixed internal threshold (150 °C). The sensing element of the chip is very close to the PDMOS area, ensuring fast and accurate temperature detection. A hysteresis of approximately 20 °C avoids that the devices turns ON and OFF continuously.

10/31