ST AN1326 Application note

AN1326

APPLICATION NOTE

L6565 QUASI-RESONANT CONTROLLER

by Claudio Adragna

A variable frequency version of flyback converter, commonly known as Quasi-resonant (QR) ZVS fly­back, is largely used in certain applications, such as SMPS for TV, though it is well suited for other ap­plications too.

This peculiar topology features several merits. Besides the others, which will be highlighted in the text,
one of them is to be a simple derivative of the standard square-wave flyback, well known to ever y SMPS
designer.

After deriving the equations governing QR ZVS flyback topology and dealing with the related issues,
ST's L6565, a PWM controller specifically designed to fit this particular topology, will be presented and
its internal functions discussed in details.

Some clues on the design based on this device will be provided and, finally, a design example will be
given that will show how easy and cost-effective such L6565-based systems are.

INTRODUCTION

Over the past two decades plenty of resonant and quasi-resonant converters have been developed and pro­posed as an answer to the difficulties raised by square-wave converters, especially those related to their para­sitic elements. The basic idea is to put these parasitics in use.

The core of both classes of converters is a tank circuit. Unlike resonant converters, where it takes part actively
in the power conversion process, quasi-resonant converters use the tank circuit only to create either a zero­voltage or a zero-current condition for the power switch, to turn on or turn off respectively.

The existing type s of quasi-r esonant converter s can be then c lassi fied as either Zero-Voltage Switchi ng tur n-on
(ZVS) or Zero-Curre nt Switching turn-off (ZCS) converters.

In ZVS converters the power switch is dy namical ly c onnected i n par allel to the tank ci rcuit. The super positi on of
the resonant voltage across the tank circuit (and the switch, while it is in off state) on the DC input voltage gen­erates the zero-voltage condition for the switch to turn on. Conversely, in ZCS converters the power switch is
connected in series to the tank c ircuit. The super positi on of the resonan t cur rent flow ing through the tank ci rcuit
(and the switch, while it is in on state) on the normal current flow generates the zero-current condition for the
switch to turn off.

An interesting property of quasi-resonant converters is that they will be turned back into a normal square-wave
converter if the tank circuit is removed. Vice versa, a quasi-resonant converter can be obtained starting from a
normal square-wave topology.

QR ZVS FLYBACK TOPOLOGY

In principle there are many ways to make a quasi-resonant (QR) ZVS flyback converter, but most of them are
not suitable for offline applications because of the too high voltages involved. With the above-mentioned prop­erty in mind, it i s pos sible to d eri ve a QR vers ion s tart ing from a s tandar d square-w ave fl yback pow er stage and
pointing out its major parasitic elements, as illustrated in figure 1.

L

is the leakage inductanc e, which represents the magnetic flux gener ated by the primary winding and no t cou-

lk

pled to the secondary. It stores energy that will not be delivered to the secondary and that needs to be trans­ferred or dissipated elsewhere. Besides, it prevents a portion of the energy stored in the mutual inductance L
(which is perfectly coupled to the secondary) from being transferred to the secondary and delays the energy
transfer process. The energy s tored in L
turn-off.

is the cause of the large overvoltag e spike on the MOSFET's drain at

lk

m

November 2002

1/34

AN1326 APPLICATION NOTE

Figure 1.

Vin

Cd is the total capacitance of the drain node. It is the sum of the MOSFET's C

Flyback power stage with major parasitics (a) and VDS waveform with fixed frequency, DCM (b).

Cin

Vf

Lm

Lp

L

Rp

Ls

lk

Cd

V

Vout

DS

a)

V

V

DSs

V

V

DSmin

DS

L

in

lk & Cd

T

d

t = 0

Tv

T

ON

FW

T

OFF

T

Lp & C

V

R

V

R

t

b)

, transformer intrawinding ca-

oss

pacitance, stray capacitance due to the layout of the circuit (e.g. a heatsink) as well as other contributions re­flected from the secondary side, such as an R-C damper on the rectifier diode.

Actually, C
and the impact is however limited. Therefore, it is possible to assume for C

= 25V by manufacturers.

V

DS

is discharged inside the MOSFET as it is turned on, thus causing a current spike. This spike not only gives

C

d

is modulated by the drain voltage but the variation becomes significant at very low VDS values

oss

the value specified usually at

oss

origin to additional losses in the MOSFET but may also cause noise problems, especially in case of current
mode control and under light load conditions.

R

is the resistance of the primary side mesh, mostly located in the primary winding. It is important to notice that

p

the resistance of the primary winding has to account not only for the ohmic resistance of the wire but also for
the high frequency effec ts in copper ( skin and proximity), the magnet ic materi al losses (hysteresis and eddy cur­rents) and radiation.

At least a couple of tank circuits can be then identified in the schematic, whose effect is conspicuous on the
drain voltage waveform in Discontinuous Conduction Mode (DCM) operation (see figure 1b).

The first one shows up after the overvoltage spike at MOSFET turn-off and is due to the resonance of L
demagnetized, with C

. The drain voltage falls in under dumped fashion from the peak to the settling value:

d

, just

lk

where V

= Vin + VR = Vin + n · (V

V

DSs

is the DC input voltage, VR the so-called reflected voltage , n the pr imary-to- secondar y turn r atio, V

in

+ Vf)(1)

out

out

the regulated output voltage of the converter and Vf the forward drop across the secondary rectifier.
The second tank circuit, made up of L

and Cd, resonates as the secondary winding has run dry of energy,

p

thus the secondary rectifier no longer conducts, and both windings are open. In principle, it is an RLC circuit
and the drain voltage follows the natural evolution of such circuit starting from the condition of C

@ t = 0 (see waveform in figure 1b). Rp is normally by far less than the critical damping impedance of the

V

DSs

charged at

d

tank circuit, thus the equation describing the under-damped evolution of the drain voltage is:

(t) ≈ Vin + VR · e

V

DS

-α·t

· cos(2 · π · fr · t)

where:

R

p

------------- -=

2/34

α

-------------------------------------=

f

r

π

2

,(2)

⋅

2L

p

1

L

⋅⋅⋅

pCd

(3)

are the decay factor and the resonance frequency, respectively.

)

)

The first valley of the resonance occurs at t = T

⋅⋅⋅()

cos 1–T

π

2

frT

v

, where Tv can be derived from:

v

1

v

---------- - π
⋅

2f

r

⇒

L

pCd

AN1326 APPLICATION NOTE

⋅⋅===

;(4)

At that point, the drain voltage experiences an absol ute minim um, given by V
imation ( e

-α·Tv

≈ 1). Therefore, a zero-voltage condition can be generated provided that:

≤ 0 ⇒ VR ≥ V

V

DSmin

in

≈ Vin - VR with good approx-

DSmin

(5)

and, if the system is controlled so that the MOSFET is switched on as the drain voltage reaches either zero or
the minimum of the first valley, a QR ZVS converter will be obtained. The resulting waveforms are shown in
figure 2.

Figure 2. (a) Typical QR waveforms; (b) How Vin affects ZVS conditions.

DS

V

R

in

V

I

PKs

I

I

PKp

Pri Sec

T

ON

T

sw

T

= 1/ f

FW

V

DS

V

t

in2

V

in1

V

NO ZVS! ZVS

v

T

V

DS

@ Vin=V

in2

VDS@ Vin=V

in1

t

a

b

It is worthwhile noticing that the operation of the tank circuit depends only on circuit parameters and not on the
operating conditions of the c onverter . The input v oltage jus t impacts on the zero- vol tage conditi on, as state d by
eqn. 5 and shown in figure 2b.

The key point to generate such kind of functionality is to synchronize MOSFET's turn-on to the transformer de­magnetization after an appropriate delay (T

(t). Therefore, in princ iple, any PWM con trol ler with synchr oni zation c apability can be us ed to control thi s

of V

DS

), which can be done just by detecting the negative-going portion

v

kind of converter. The L6565, in partic ular, is provided with a dedicated pin (ZCD) that allows doing the job with
a very simple interface, just one resistor.

Variable frequency operation - as a result of input voltage and/or output current changes - is inherent in such
functionality. The sys tem works clos e to the boundar y between D CM and CCM (Continuous Conduct ion Mode)
operation of the transfor mer. This is what i s otherwise c alled TM ( Transition Mode) operation. The shor ter T

is,

v

compared with the ON and OFF times of the MOSFET, the closer to TM the operation will be. Hence this QR
ZVS flyback converter can be identif ied with the TM flyback converter mentioned in [1], as well as with the well­known self-oscillating flyback or Ringing Choke Converter (RCC).

As opposed to fixed-frequency standard flyback converter, this approach to quasi-resonance has several ad­vantages.

The main benefit probably c oncerns conducted EMI emi ssions. In mains operated applications , due to the ri pple
appearing across the input bulk capacitor, the switching frequency is modulated at twice the mains frequency
f

, with a depth depending on the ripple amplitude. This causes the spectrum to be spread over frequency

L

3/34

AN1326 APPLICATION NOTE

)b)

bands, rather than bei ng concentrated on singl e frequency values. Especiall y when measuring conducted e mis­sions with the average detection method, the level reduction can be of several dBµV. Figure 3 shows a compar­ison made on the same L6565-based SMPS, fixed frequency first and then QR-operated. It is then possible to
reduce the size and the cost of the EMI filter.

Figure 3. Conducted EMI (average detection): a) fixed-frequency operation; b) QR operation.

a

Another important benefit is a high safety degree under short circuit conditions: since the conduction cycles of
the MOSFET are inhibited until the transformer is fully demagnetized, flux runaway and, therefore, transformer
saturation are not poss ible. Mor eover, as during a shor t circuit the dem agnetizatio n voltage is very low, the s ys­tem will be led to work at a very low frequency, with a very s mall duty c ycle. As a result, the power that the con­verter will be able to carry is very low.

Additionally, QR approach makes use of the otherwise undesirable parasitic drain capacitance to generate a
zero-voltage condition that minimizes turn-on losses of the MOSFET. An external capacitor may be added in
parallel to the MOSFET or across the primary winding. This will reduce the impact that the spread of the parasitic
C

has on fr, smooth the negative-going edge of the drain voltage after transformer's demagnetization (in the

d

interests of EMI) and reduce the dV/dt at turn-off, with the benefit of lower turn-off losses and EMI generation.
Finally, the way the system processes power does not change, thus designer's experience with standard flyback

can be fully exploited and there is very little additional know-how needed.
To complete the pictur e, it must be sai d that t here are al so some draw backs. The sy stem ac tually work s in DCM,

thus currents' peak and RMS values are quite high: this will result mainly in higher conduction losses in the
MOSFET and greater high frequency loss es in the transformer. Thi s suggests not using this appr oach for power
levels above 120-150W in wide range mains applicati ons and above 200 W with European mains. Furthermore,
the high operating frequency when the converter is lightly loaded partly cancels the advantages of the ZVS in
terms of power losses. Finally, while in a standard flyback the design can be optimized in order for a 600V-rated
MOSFET to be used in European or wide range mains applications, optimizing the design in a QR system will
likely lead to the use of a more expensive 800 V-rated MOSFET.

In the following, the topology's operation wil l be d iscus sed in details and a set of equations useful for the des ign
will be given. Then the use of the L6565, a PWM controller specific for this particular topology, will be discussed
in details. Finally, an application (an SMPS for TV) will be developed and the evaluation result of its prototype,
as well as some significant waveforms, will be presented.

QR OPERATION: TIMING AND ENERGETIC RELATIONSHIPS

To generate the equations governing the operation of a QR ZVS flyback converter, with the aim of providing a
design method, some simplifying assumptions will be made:

1) Fall and rise times of both voltage and current waveforms are negligible.

2) Transformer's non-idealities will be neglected (no delay in the primary-to-secondary energy transfer,
peak secondary cu rrent proportional to the primary one dep ending on primary- to-secondary tu rn ra tio n).

3) The system is controlled so that the time elapsed from transformer's demagnetization to MOSFET's
turn-on is kept equal to T

4/34

, eqn. (4), under all operating conditions.

v

AN1326 APPLICATION NOTE

That being stated, it will be useful to refer to the simplified schematic of figure 4 as well as the waveforms of
figure 2. The ON-time of the MOSFET is expressed by:

⋅

LpI

PKp

ON

----------------------=

V

in

T

(6)

After T

has elapsed the MOSFET is turned off and energy is transferred to the secondary winding. The time

ON

needed for the discharge of this energy to the output, referred to as "freewheeling time", will be:

L

p

where L

⋅

LsI

PKs

FW

----------------------­+

V

outVf

T

is the inductance of the secondary winding and I

s

----- -

n

---------------------------------- -

⋅()⋅

nI

2

+

V

outVf

PKp

⋅

L

pIPKp

----------------------== =

the peak secondary current.

PKs

,(7)

V

R

Figure 4. Block diagram of an L6565-based QR ZVS flyback converter.

+Vin

Vout

3

VFF

2.5V
+

INV

1

-

E/A

COMPENSATION

NETWORK

LINE VOLTAGE

FEEDFORW AR D

E/A

2

COMP

ZCD

ZCD

+

-

COMPARATOR

5

PWM

STARTER

L6565

starter STOP

S

RQ

reset

dominant

6

GND

DRIVER

Lp

Ls

GD

7

CS

4

Rs

ISOLATED

FEEDBACK

The total conversion cycle period TSW is the sum of TON, TFW and Tv, and the switching frequency is:

f

SW

1

----------- -

T

SW

-------------------------------------------- -==

T

1

++

ONTOFFTv

.(8)

Since the system actuall y works in DCM, the peak pr imary c urrent is related to the input power of the conver ter,

(more precisely, to transformer's input power), according to the well-known relationship:

P

in

P

in

1

---

2

⋅⋅ ⋅=

L

pIPKp

2

.(9)

f

SW

By substituting (4), (6) and (7) in (8) and combining with (9), the switching frequency can be expressed as a
function of the characteristic parameters of the circuit (L

, VR, fr) and of the operating conditions (Pin, Vin). The

p

result can be conveniently expressed in the following terms:

⋅

2f

T

f

----

f

T

r

12

⋅+++

f

----

f

1

1

1



--------

-------+



V

V

in

R

, (10)

T

r

2

(11)

5/34

where:

f

T

f

SW

--------------------------------------------------------------=

⋅⋅⋅

2P

----------------------------------------------- -=

1

inLp

AN1326 APPLICATION NOTE

D

'

1

V

R

-------

2P

out

Lpf

sw

⋅⋅⋅⋅

=

I

ACs

I

RMSs

2

I

DCs

2

–=

V

REV

V

out

1

V

in

V

R

--------+





⋅

=

is the "transition frequency", that is the frequency the system would work at if fr
occur if C
Actually, in case f
(10). The two quantities become more and more different as the ratio f
figure 5), that is as the delay T

= 0. The name comes from the fact that this frequency is characteristic of TM operation.

d

<< fr, it is possible to estimate fsw by using eqn. (11) instead of the more complex formula

T

becomes a significant portion of the switching period Tsw.

v

/ fr increases (see the right diagram of

T

→ ∞ ⇒

Tv = 0, which would

Figure 5. Switching frequency vs. operating conditions (left) and fsw vs. fT (right) relati onships

5

4

sw

f

3

swmin

f

2

1

1 1.5 2 2.5 3 3.5 4

V

0.1·P

0.2·P

0.5·P

in

V

inmin

P

inmax

inmax

inmax

inmax

1.0

0.8

sw

f

0.6

T

f

0.4

0.2
0 0.25 0.5 0.75 1 1.25 1.5 1.75 2

T

f

r

f

The switching frequenc y fsw changes with the operating conditions in so far as the transiti on frequency fT chang-

, f

es, as shown in the l eft diagram of figur e 5. Eqn. ( 11) s hows that the minimum value of f
ally a design constraint, will be reached at maximum input power (P
minimum, V

. Being the converter operated from the AC mains, V

inmin

) when the input voltage Vin is at its

inmax

is the valley voltage across the input

inmin

sw

, which is usu-

swmin

bulk capacitor. Therefore, to fulfill the design requir ement concerning the minimum operating frequency, the pr i­mary inductance L

L

pmax

will be selected not exceeding the following upper limit:

p

---------------------------------------------------------------------------------------------------------------------------------------------------------=

⋅⋅

2P

in maxfsw min

1

1



----------------- -



V

in min

1

-------+

V

R

⋅⋅+⋅

π

f

sw min

C

2

d

, (12)

The equations that provide the quantities of interest in the design of a QR ZVS flyback converter can be easily
derived considering that the system is inherently of DCM type, although working at a frequency subject to
change with the operating conditions. Table 1 summarizes these relationships.

Table 1. Main Electrical Quantities in QR ZVS Flyback Converters

Parameter Primary Side Secondary Side

1

--------

1 Duty Cycle

2 Peak Current

3 DC Current

4 Total RMS Current

5 AC RMS Current

6 Peak Voltage

7 Switching frequency modulation depth

6/34

D

=

I

I

I

ACp

V

PKDSVinVRVspike

2P

in

PKp

⋅⋅⋅⋅

1

---

=

2

=

2

I

RMSp

2P

------------------=

L

pfsw

I

PKp

V

I

DCp

RMSpIPKp

++=

f

∆

sw

-----------

f

sw

inLpfsw

⋅

in

⋅

D⋅⋅

D

⋅

----

3

2

I

–=

DCp

2f

⋅

-------------------------

=

2f

⋅

2V

–

rfsw

+

rfsw

⋅

----------------------

⋅⋅

V

+

RVin

PKs

I

DCs

∆

-----------

V

V

=

in

in

2I

-------------------=

I

I

RMSsIPKs

R

⋅

DCs

D

'

P

out

-----------=

V

out

D

'

⋅

-----

3

AN1326 APPLICATION NOTE

Once the switching frequency has been found from (10), or simply from (11) if that is the case, all of the quan­tities listed in the table c an be easi ly ca lculated. Obvious ly, c urrent stresses wil l be cal culated at minimum input
voltage and maximum load, while voltage stresses will be calculated at maximum input voltage.

is the power delivered to the load, while the input power Pin that appears explicitly or not in all of the rela-

P

out

tionships should be the one processed by the primary side of the transformer. This is the sum of the power com­ing out of the secondary side, that lost inside the transformer due to copper and ferrite losses and the one not
transferred (and mostly dissipated in a clamping circuit) because of the leakage inductance. A transformer effi-

η

ciency

could be estimated, such that:

t

P

in



⋅

P

-------------------------------------------=

1



out



η

t

V

f

-----------+

V

out

(13)

The efficiency
technique. If at design-time the designer feels more confident of estimating conv erter's overall efficiency
than transformer's

η

is usually quite high, typically 92 to 98%, depending on transformer's size and construction

t

η

, Pin can be considered as the input power of the converter, that is the ratio of P

t

η

rather

out

to η,

with acceptable approximation.

QR OPERATION: CONVERTER'S POWER CAPAB ILITY AND L6565'S LINE FEEDFORW AR D FUNCTION

Current-mode control wil l be used, thus the maximum power that the sy stem is able to deliver to the output (P

inlim

),
that is its power capability, is controlled by means of pulse-by-pulse current limitation. This is usually done by
clamping the control voltage that programs the peak primary current I
the maximum peak primary current I

PKpmax

.

at a fix ed value V

PKp

, in this way limiting

csx

In fixed-frequency DCM flyback converters, this provides a power capability that, ideally, is independent of the
input voltage V

. Actually, there is a slight dependence due to the internal propagation delay of the controller

in

and the MOSFET's turn-off delay (200 to 500 ns overall).
Differently, in QR ZVS flyback even in the ideal case of no delay , power capability strongly depends on the input

voltage. In wide-range mains applications this can be an issue.
The situation is illustrated in figure 6a. The upper trace shows the primary current waveform at minimum input

voltage: the peak current is close to the maximum, thus just a small extra output power will trip the current lim­itation circuit. The lower trace shows the primary curr ent waveform under the same load conditions at maximum
input voltage. Being the switching frequency higher, then the peak current will be lower: a much larger power
will be allowed to pass before pulse-by-pulse limitation is tripped.

Figure 6. a) Primary current at min. and max. input voltage; b) Power capability vs. input voltage

I

@Vin=V

p

min

in

I

PKp

max

2.2

2

T

delay

= 400 ns

1.8

in

t

p

I

@Vin=V

in

max

PKp

I

max

t

a)

The effect of such delay is shown in figure 6b, where P
typical design (V

Even ideally (T

= 100 to 400V; P

in

= 0), at 400V input the power throughput that trips the pulse-by-pulse current limitation is

delay

= 125W, f

inlim

swmin

inlim

= 100 kHz, Lp = 110µH, VR = 150V, Cd = 1.5nF).

inmin

@ V

1.6

@ V

inlim

P

inlim

1.4

P

1.2

1

1 1.5 2 2.5 3 3.5 4

in

V

inmin

V

b)

T

delay

vs. Vin is shown for both zero and 400 ns delay in a

about 1.65 times higher than what needed at 100V. Accounting for the delay the limit rises at 2.11 times.

= 0

7/34

AN1326 APPLICATION NOTE

To overcome this problem, the L6565 has the Line Feedforward function available. It acts on the clamp level of
the control voltage V
sensed through a dedicated pin (#3, VFF): the higher the input voltage, the lower the setpoint. The diagram of
figure 7a shows the relationship between the voltage at the pin VFF and V
high in the attempt of keeping output voltage regulation). The schematic in figure 7b shows how the function is
included in the control loop.

Figure 7. a) Ove rcurrent se tpoi nt vs . VF F vol t age ; b) Li ne Feedforw ard function blo c k

V

[V]

csx

1.5

, that is on the overcurrent setpoint, so that it is a functi on of the conv erter's input v oltage,

csx

(with the error amplifier saturated

csx

+Vin

V

COMP

= Upper clamp

R1

1

0.5

0

0 0.5 1 1.5 2 2.5 3 3.5

V

[V]

VFF

Quantitatively, the maximum power capability P

PKp

= I

which I

Ideally, the maximum peak primary current I
in table 1 @ V

, substituted in (9):

PKpmax

P

in lim

in

= V

) would be equal to V

inmin

1

---

2

------------------------------------------------------------------------------ -

⋅⋅=

L

p

I

PKp maxLp

PKpmax

/Rs, however the internal pr opagation delay as well as the MOS-

csx

INV

1

2.5V

can be expressed by means of eqns. (6), (7) and (8), in

inlim

2

I

PKp max




(which should slightly exceed the value derived from line 2

R2

COMP VFF CS

23

­E/A

+

1

1

--------

-------+

+⋅⋅

T

V

V

in

R

VOLTAGE
FORWARD

v

FET's turn-off delay, has to be accounted for . This causes the actual I

ZCD

5

4

ZCD

FEED

+

PWM

-

+

Hiccup

-

2 V

. (14)

to exceed the ideal value by an

PKpmax

STARTER

Rs

starter STOP

S

R

(reset-dominant)

DISABLE

DRIVER

7

GD

Q

L6565

amount proportional to the input voltage:

I

PKp max

V

------------

csx

Rs

V

--------

L

in

⋅+=

T

p

. (15)

delay

The Line Feedforward bloc k c ombines the v oltage at pin VFF (proportional to the converter's input voltage) with
the E/A output, thus determining th e internal reference (V

) for the PWM comparator, accor ding to the following

cs

relationship:

= 0.16 · (V

V

cs

Note that in this equation V

= 0, which forces the L6565 to stop switching. Actually eqn. (16) is not very accurate when either V

is V

cs

or V
the real V
of V

get close to their respective limits: the effect of offsets and some non-linearity becomes sig nificant. Thus

VFF

= 0 condition and the switching halting may occur for values of V

cs

slightly above 3V

VFF

The overcurrent setpoint (V

is ≥ 2.5V and V

COMP

), graphically illustrated in the diagram of figure 7a, can be found considering the

csx

error amplifier at the limit of its linear dynamics (V

- 2.5) · (3 - V

COMP

) (16)

VFF

is ≤ 3V. Ideally, if either V

VFF

≅ 5.4V). The resulting analytical V

COMP

= 2.5 or V

COMP

slightly below 2.5V and values

COMP

csx

VFF

vs. V

= 3 the result

VFF

COMP

relation-

ship is:

V

= 0.467 · (3 - V

csx

) = 0.467· (3 - k · Vin), (17)

VFF

where k is the divider ratio R2/(R1+R2).
If this function is not needed for any reason, e.g. because of a narrow input volta ge range, the pin w ill be ground­ed. The overcurrent setpoint will be set at V

8/34

= 1.4V regardless of the converter's input voltage.

csx

Figure 8. Correction characteristics of Line Feedforward

2.5

AN1326 APPLICATION NOTE

2

in

inmin

@ V

1.5

@ V

inlim

inlim

P

P

1

in

V

inmin

-3

k=5.07387·10

0.5
1 1.5 2 2.5 3 3.5 4

optimum value

V

The diagram of figure 6b, as well as equations 14 and 15, shows a non-linear relationship between P
and V

, hence the linear correction (17) will not result in a perfect compensation. A considerable reduction of

csx

k=0

k=3.0·10
k=4.0·10

k=6.0·10

-3

-3

-3

, V

inlim

the power capability change over the input voltage range will be achieved anyway.
Figure 8 shows the effect of the compensation circuit on the converter's power capability for different values of

k (a T
The optimum value of k, k

be found by combining equations 14, 15 and 17, imposing that the value of P

of 400 ns is assumed) in the typical design previously considered.

delay

, which minimizes the pow er capability variation over the input voltage range, c ould

opt

is the same at the extremes

inlim

of the input voltage range and sol ving for k. However, the val ue of the sens e r esisto r Rs, which app ears in (15) ,
is a function of k

in turn. The exact calculation is very complex, and non-idealities shift the actual optimum

opt

value from the theoretical one. It is therefore more practical to provide a first cut value, simple to be calculated.
Then, Rs will be chosen on this basis and k

A great simplification comes from assuming T

k

3

opt

⋅=

found empirically.

opt

= 0 (exact TM operation) and T

v

V

-----------------------------------------------------------------------------------------------------------

V

in minVin maxVin minVin max

R

+()V

⋅+⋅

= 0; k

delay

R

will then be:

opt

(18)

in

With k = k

exceeds P
input voltage range and delay, this result does not depend on the specific design, only k

The value of Rs, can be determined from (15), again with T

The approximate calculation yields a value of kopt equal to 3.913·10

5.074·10
After choosing Rs, the value of k

, the maximum value of P

opt

V

@ Vin = V

inlim

-3

.

It can be a useful rule of thum b to use the v alue resul ting from (18) increased by 20% as the st arting point .

inmin

(= P

inlim

opt

, reached at:

inlim

V

in

inx

@ Vin = V

=

s0.467



⋅

VRV



) by about 20%. It is worthwhile pointing out that, for gi ven

inma x

–

3k

-----------------------------------------

⋅

I

----------+

R

k

delay

⋅

V

opt

PKpmax

3

–==

, (19)

V

opt

R

changes.

opt

= 0, resulting in:

inmin

. (20)

-3

, about 23% less than the exact value

can be fine-tuned experimentally to minimize converter's power capability
changes over the input voltage range. To do so, it is necessary to check the power level where the converter
loses regulation just at minimum and maximum input voltage and adjust k (e.g. using a trimmer) so as to make
them equal. This could require, in turn, a modification of Rs, because the power level achieved in the previous
step is slightly higher or lower than the target, thus some iteration might be needed. The values of R1 and R2
will be high enough to minimize the power dissipated on them, especially if there are requirements on the con­verter's efficiency under light load or no-load conditions.

The small-signal control-to-output-gain of the Line Feedforward block, needed for stability analysis, can be de­termined by differentiation of the large-signal model (16) and considering that V

ˆ

v

cs

------------------

==

G

FF

ˆ

v

COMP

0.16 3 k

–

⋅()⋅

V

opt

in

VFF

= k

opt

·Vin:
(21a)

9/34

AN1326 APPLICATION NOTE

)

)

y

g

Line Feedforward improves also the input ripple r ejection abi lity of the system and limits the variation of the gain­bandwidth product of the smal l-signal contr ol-to-output tr ansfer function with the input voltage (see APPENDIX).

The small-signal line-to-output gain of the block is found again by differentiation of (16):

ˆ

v

-------­ˆ

v

cs

in

0.16k

optVCOMP

–()–

2.5

'

G

FF

QR OPERATION: BEHAVIOR UNDER SHORT CIRCUIT CONDITIONS

As previously said, a QR flybac k conv erte r operates safely under shor t circui t conditio ns at the output. The r ea­son of that is that any new conduc tion of the MOSFET is i nhibited as long as the tr ans former is n ot fully demag­netized. Equation 7, which is here recalled:

T

FW

⋅

LPI

PKp

---------------------- -

V

R

⋅

L

PIPKp

----------------------------------- -==

nV

outVf

shows that, as the overload is progressively increased, the demagnetization time T

is kept constant by the pulse-by-pulse limitation and the output voltage drops becaus e the system is out of

I

PKp

regulation. However, if T
before the demagnetization is complete. In some cases, before T

exceeds the period T

FW

of the internal starter, the MOSFET will be switched on

START

FW

so low that the oscillation on the ZCD pin can no longer arm the internal circuit.
Whichever condition is met first, the converter will be forced to work at the frequency of the internal starter (1/

T

) and, likely, in CCM. Flux runaway, though now theoretically possible, is however extremely unlikely.

START

Referring to [2] for the details of the calculations, the flux runaway condition for a dead short at the output is:

⋅

nV

------------------- -

V

inVf

T

f

ONmin

-------------------- -

+

T

START

–

≅≤

10

which is very tough to meet in normal offline applications, as one can easily see by using sensible values for n,
V

and Vf. T

in

is the minimum ON-Time that the L6565 can provi de because of its inter nal delays and MOS-

ONmin

FETS’s Turn-Off delay, usually around 300-400ns.
To guarantee the operation described so far, the L6565 blanks the ZCD input for some time (3.5 µs min.) after

the MOSFET has been turned off. In this way, situations like the one shown in figure 9a, relevant to a short circuit
in a 50W converter using a controller not provided with this safety feature, are prevented. In that picture it is
possible to see that the system is detecting the demagnetization of the leakage inductance and not that of the
primary inductance. This causes a very high frequency operation - instead of a very low one - that has led to
transformer saturation: the primary current reaches a peak of 8A in 400 ns with a slope pointing out only 15 µH
inductance (the overcurrent setpoint was 2A, the primary inductance was 400 µH).

k

opt

-------------------------------- -

–== =

3k

optVin

,

+()⋅

> T

START

3

,

V

.

cs

⋅–

gets longer and longer:

FW

(21b)

, the reflected voltage VR can be

Figure 9. Short circuit waveforms in a system a) without ZCD blanking; b) with ZCD blanking

Primary current

(zoomed)

Drain voltage

(zoomed)

Primary current

Vin = 300 V

Drain voltage

10/34

T

ONmin

LLK ≅15 µH

ON OFF

fsw ≅550 kHz

Primary current

b

T

BLANK

Duty cycle ≈1%

ON

Leakage

inductance

netization

dema

Drain voltage

Vin = 300 V

Internal starter

perio d

ZCD circuit dela

a

T

AN1326 APPLICATION NOTE

Figure 9b shows instead the operation previously described, allowed by the L6565, where the converter works
at the frequency of the internal starter with a duty cycle of about 1%.

Dangerous short circuit conditions occur when there is an isolation failure on the secondary winding, e.g. due
to a damaged wire coating, or when the secondary diode fails short (typical of axial diodes). Both of these fail­ures reflect a shor t c ircuit to the transfo rmer' s prim ary sid e while the MOSFET is turned on [2]. The prim ary cur ­rent rate of rise is then limi ted only by the leakage inductance of the transformer, like in figure 9a. If not properly
handled, this very likely leads to the destruction of the system.

To protect the converter in the event of such failure, a comparator (shown in fig. 7b) senses the voltage on the
current sense input and disables the gate driver if this voltage exceeds the 2

enable the driver, first the IC must be turned off and then restarted: in other words, the Vcc voltage must fall
below the UVLO threshold and then exceed again the start-up threshold.

With the gate driver disabled the quiescent current of the IC is unchanged and, since no energy is coming from
the self-supply circuit, the Vcc capacitor will be discharged below the UVLO threshold after some time (see pin
8 in "L6565 pin usage" section). Then the device will initiate a new start-up cycle. This will result in a low -fre­quency intermittent operation (Hiccup-mode operation), with very low stress on the power circuit.

QR OPERATION: HIGH SWITCHING FREQUENCY AT LIGHT LOAD AND L6565'S FREQUENCY FOLD­BACK FUNCTION

Equations (6) and (7) show that TON and TFW can be however short if I

→ ∞

case f

and fsw → 2·fr. Although in the real-world operation the maximum switching frequency would be

T

PKp

significantly lower than this theor etic al l imit, it cou ld be of som e hundred k Hz and c ause a consi derable efficien­cy drop. This is why the L6565 has been provided with the Frequency Foldback function.

In principle, this function lies in putting a limit to the minimum OFF-time of the switch [3]. The blanking time of
the ZCD circuit, used for safe operation under short circuit conditions and mentioned in the previous section,
serves this purpose as well. Therefore, the QR operation considered so far will be maintained as long as:

nd

level OCP, fixed at 2V. To re-

(i.e. the load) tends to zero, in whi ch

T

where T

BLANKmin

+ TV ≥ T

FW

BLANKmin

is the aforesaid minimum blanking time (3.5 µs) of the Zero Current Detector (ZCD) circuit.

, (22)

The maximum operating frequency will then not exceed:

f

swmax

----------------------------------------------------------------------------------- -=

T

BLANKmin

1

V



R

------- -+

V

in

–

T

⋅⋅

1




V

R

------- -

v

V

in

.

Figure 10. Frequency foldback: ringing cycle skipping as the load is progressively reduced

V

DS

T

T

FW

V

T

BLANKmin

Pin= P

in'

(limit condition)

V

DS

t

T

BLANK

in''

Pin= P

< P

in'

V

DS

t

T

BLANK

in'''

Pin= P

< P

in''

t

If the load current and the input voltage are such that the condition (22) is not fulfilled, the system will enter the
"Frequency Foldback" mode, a sort of "ringing cycle skipping" illustrated schematically in figure 10.

11/34