ST AN1317 Application note

AN1317

®

- APPLICATION NOTE

NON ISOL ATED POWER SUPPLIES IN BUCK AND

INVERTER CONFIGUR ATION USING VIP e r2 0 DEVICE

A. Bailly - S. Luciano

INTRODUCTION

The VIPer20 is a full integrated switching device. It replace s the con ventional PWM driver circuit, its
associated high voltage Power MOS FET switch and a full set of other passive com ponen ts, and provi de
a high level of performance thanks to its current mode structure and standby operation capability.

1. SCOPE

The VIPer20 is initi all y de sig ned to be used at the pri m ary si de of an y off line po w er supp lie s in isolated
flyback configuration but it is also the right solution for different types of not isolated power supplies
applications whe re low power (1W to 5W) , wide input vol tage range and low price s are requi red. In this
case, a simple two pins inductor can replace an expensive safety transformer. The basic principle of this
type of supplies is to convert a high voltage source to a low voltage one by the only way of the switching
frequency and duty cycle management.

The applications like home appliances (microwave oven, washing ma chine, triac drivers...), industrial
applications (motor s control,...) do not require galvanic isolation between the mains lines and the low
voltage load, especia lly when one of the low voltage outputs must be connec ted to one of the mains
line s.

All these applications will take benefits from VIPer20 features:

• Full integrate d PWM start up cu rrent source and high voltage Po wer MOSFET, allow to build simple,
robust, cost effective and compact power supplies.

• Built in overtemperature and overcurrent protection provide a safe control in overload conditions.

This application note gi ves al l the ele ments to ena ble th e designer to s tart the d evelopment of his own
non isolated power supply using the VIPer20. It defines the key components, and highlights the
differences between the Buck and the Inverter (also called Buck-Boost) topologies.

2. NOT ISOLATED TOPOLOGIES

2.1 VIPer20 In Buck Topology

The basic schemati c of a VIPer20 in Buck topology deli vering 2W typi cal, with a fixed outp ut voltage, is
given fig. 1. T he Buck structu re is compos ed her e by the o n chip Power MO SFET, the ind uctor L1, the
free wheeling diode D3, the output filtering capacitor C5 and the output load itself.

In this topology, the VIPer20 switching duty cycle is very low (a few percent) because of the very high
difference between the input and t he output voltages. Its value w ould be at the maximum equ al to the
voltages ratio, when in continuous mode and even less in discontinuous mode. If the switching frequency
is too high, the Power MOSFET conduction time will decre ase accordingly, which may result in early
burst mode operation if lower than the minimum turn on time of the device. In practice, the chosen

Janua ry 20 01 1/23

AN1317 - APPLICATION NOTE

switching frequency will be comprised between 20 kHz and 30 kHz, just above audible values.
During the star t up phase, the V IPer20 is i n standby mode and i ts on chip high voltage current source

sources a cur rent o n the VDD pin until the volt age a cross the capacitor C2 reaches th e V
Then, this current sou rce is turned off and the device starts switching. After a transition phas e during

which the output voltage grows up, the VDD supply of the VIPer20 is provi ded by the capacitor C2 and
finally, from the positive out put throug h the diode D2 when the outpu t voltage b ecomes highe r than the

current VDD value.

Figure 1: 2W typical single output not isolated power supply with Buck topology

DDon

threshold.

AC IN

AC IN

D1

1N4007

C1

22uF

400V

C2

10uF
16V

R1

10k

C3

10nF

OSC

VIPer20

D2

BYT01-400V

DRAINVDD

-

13V

+

COMP SOURCE

R2

3.9k

C4

100nF

BYT01-400V

D3

L1

470uH

C5
33uF
16V

+13V

DZ1

BZX55C15V

GND OUT

In normal operation, the output voltage regulation is achieved by the VIPer20 error amplifier which
accurately compares the VDD value to the internal 13V voltage reference. The forward voltage across the

diode D2 is here partially compensated by the forward voltage across the diode D3. So, the output
voltage and the on chip voltage refer ence val ues ar e equal, exc ep t for diode for ward vol tage differences
due to different dio des cur rent : It is g ener al ly hi ghe r in th e fr ee w hee ling di od e D3, r esul ting i n a sligh t ly
lower output voltage.

A typical characteristic of the Buc k is that the inductor cha rge and discharge paths a re exclu s ivel y done
through the output load. It is a slight advantage i n norma l operation because the energy is transferre d to
the load during both turn on and turn off cycles, but in very low or no load conditions, it has two
drawbacks:

• The charge of the star t up tank capacitor C2 is imp ossibl e, especial ly when the input v oltage is slow ly

2/23

AN1317 - APPLICATION NOTE

increased. If no protecti on is fores een, it is p ossible to ap ply the inpu t voltage dire ctly on the outp ut,
with large overvoltages.

• Once started, overvoltages may also occur at the output, mainly for low input voltage values.

The root cause of the last phenomeno n resides in the duty cycle i ncrease at low input voltage, togethe r
with a low output load. Fig. 2 shows the drain current shape for two input voltages. The lower is the input
voltage, and the hi gher is the turn on . As a consequ ence, the tur n off phase du ring which t he energy is
sent to C2 through D2 i s reduced, and the device is increasi ng its drain current to maintain a correct
regulated vo ltage on the VDD pin at 13 V. If the load is not a ble to absorb the corresponding curre nt

during the on phase, overvoltage is resulting on the output.

Figur e 2: Drain current for two input voltages in low load conditions

50mA/Div - 10µs/ Div

Vin = 200V

Iout = 5mA

Vin = 50V

Iout = 5mA

Fig. 3 shows an extreme case where the phenomenon reaches its critical phase, with a continuous mode
of operatio n. The followi ng compu tation d emonstrate s the ri sk of overvolt age an d/or over current on t he
output.

3/23

AN1317 - APPLICATION NOTE

Figure 3: Switching cycle in continuous mode in low input voltage condition

I

DRAIN

T

s

Ts

tON

I

P

PP

I

0

- ton

Charge

The average currents consumed by the VIPer20 I

1

DD

------------­2T

⋅

+()T

I

PI0

s

I

and the output current I

DD

t

–()⋅⋅=

S

on

Discharge

t

can be expressed as:

out

and

out

------------­2T

⋅

+()t

⋅⋅=

I

pI0

s

on

I

1

By using these two equations:

I

DD

I

out

Finally, by introducing the duty cycle expression in continuous mode:

t

on

----------------- -

⋅=

Tston–

t

on

------

==

d

T

s

V

---------- ­V

out

in

The minimum output current mandatory to keep the output voltage under control is given by:

V

out

-------------------------

out

I

DD

⋅=

VinV

–

out

I

To prevent th es e distur banc e s resul ting i n possi ble o utput overvoltage or incor rec t start up, a 1 5V ze ner
diode DZ1 is added . It allows a curr ent to flow at the output, insur ing a corr ect start up and cl amps any
possible overvol tage. Nev ert heless , as show n in the abo v e last formula, the current flowi ng in this zener
can be very high when the input voltage approaches the output one. Sectio n 5 describes a schematic
modification to overcome this issue.

Fig. 4 presents the operation of the free wheeling diode in this condition: Actually it is always blocked, as
the voltage on the cathode never becomes negative. Also on this figure, it can be observed that the
voltage drop Vd across D3 is about 5V while the output voltage is at 15V. It means that VDD is about 10V

4/23

AN1317 - APPLICATION NOTE

because the input v o ltage is to o low to i nsure a prop er ope ration of the con verter, which is about to sh ut
down.

Figur e 4: Buck non isolated - VIPer20 source voltage with VIN = 47 V, I

Vd

=5 mA. DZ1 conducting

OUT

2.2 VIPer20 In Inverter Topology

The inverter sche matic is derive d from the Buck one of fig. 1 by just swapping the in ductor L1 and the
free wheeling diode D3. The resulting schematic is given fig. 5. There is a major difference with the Buck
from a functional point of view : when the on chip Power MOSFET is turned on, the inductor L1 does not
charge anymore through the load but betwee n the mains lines. The out put load now gets all its energy
during the MOSFET off state, through the inductor L1 and the free wheeling diode D3.

As a consequence, the zener diode DZ1 is no more necessary because of two reasons:

• The charge of the tank capacitor C2, now independent from the load, is always possible.

• Both VIPer20 supply (VDD pin) and output load are re ceiving ene rgy form the ind uctor L 1 at the same

period of time. So, there is no possible difference between the VDD voltage and the output one, which is
always under control.

Compared to the Buck, the current flowing through the load is in the opposite direction so that the output
voltage beco mes now negati ve. As a conseq uence, the output capacitor C5 polarity m ust be swapp ed
and the anode o f the diod e D 2, supplyi ng the VI Per20, must now be connecte d to the groun d l ead GND
OUT to insure a correct positive supply to the VDD pin.

5/23

AN1317 - APPLICATION NOTE

Figure 5: 2W typical single output not isolated power supply with Inverter topology

AC IN

AC IN

D1

1N4007

C1
22uF
400V

C2

10uF

16V

R1
10k

10nF

C3

OSC

VIPer20

D2

DRAINVDD

-

13V

+

COMP SOURCE

R2

3.9k

C4

100nF

L1

470uH

BYT01-400V

D3

BYT01-400V

C5

33uF

16V

GND OUT

-13V

3. DESIGN METHODOLOGY

The schematic of either fig. 1 or fig. 5 can be separated into six blocks:

• The oscillator network composed by R1 and C3.

• The Buck or inverter structu re, whic h is compo sed by the o n chip MOS FET, the inductor L1, the fr ee
wheeling diode D3 and the output filtering capacit or C5.

• The VIPer20 supply circuit, composed by D2 and C2.

• The front rectifier and filter.

• The error amplifier compensation network composed by R2 and C4.

All these functions will be detailed in the next paragraphs.

3.1 Switching Frequency And Duty Cycle

Sections 1 and 2 showed that the input voltage transformation is entirely managed by the VIPer20 which
controls the switching duty cycle. Whatever the topology is, the goal is to look for the widest load
regulation range, trying to reach the VIPer20 minimum turn on time (T

= 500 ns typ.) for the lowest

ONmin

output load. For maximum load, although the VIPer20 is perfectly compatible from the continuous mode,
it must be avoided becaus e the power dis sipation in the fre e wheeling di ode D3 would be too high and
the inductor s ize a nd price would inc re ase. F or all the above rea s ons, th ese topologies are ope rated at

6/23

AN1317 - APPLICATION NOTE

dtonFs⋅=

low switching frequency and always in discontinuous mode.
As an example, to get a 13V output voltage with a 265 Vrms input voltag e, the maximum duty cycle

V

out

---------- -

d

=

time would always be equal or lower than T
practice the switching frequency is chosen just above the audio ones, in the 20 kHz to 30 kHz range and

the VIPer20 will work in discon tinuou s mod e with a d uty cycle of a bout 2% to 3% at h igh line and abo ut
6% to 10% at low line.

From the VIPer20 datasheet, the switching frequency is given here below:

would be l ess than 5%. With a switch ing frequency of 100 kHz, the maximum c onduction

V

in

, leading to a permanent burst mode operation. In

ONmin

2.3

---------------- -

F

s

R

1C3

On the schema tic of fig. 1 and fig. 5, R1=10kΩ and C3=10nF have been chosen to get a switch ing
frequency near by 20 kHz (21.7 kHz typical).

3.2 Inductor

In normal o peration, for both topologies, the switching cycle consists of tw o phases. First, the Power
MOSFET is switch ed on during ton, D3 is blocked, the i nductor connected to the high v oltage source

stores the energy. Second, the Power MOSFET is switched off during t
energy to the load through D3, and to the VDD pin through D2. As described in section 2, th e load is
supplied du ring t
switching cycle is shown on fig. 6.
Knowing the ou tput power, the switching frequenc y and the m aximum VIP er20 peak cu rren t, L1 can be

computed as follow:

for the Buck:

with and

on

and t

dis

P

out

with the Buck top ology, a nd only during t

1

2

-- -

I

out

F

p

L

1

2

tonVinV

–()L



⋅=



⋅

1

-- -

I

s

pVout

2

I

⋅=

1

550

---------------------

1

–

R1150–

dIDDV⋅

p

, the inductor restores its

dis

with the inverter o ne. A typical

dis

–⋅⋅+⋅⋅=

out

7/23

1

out

-- -

L

2

L

1

P

1

2

I

p

2



Fs1

--------------------------------------------------------------

⋅=

2

I

p

-------------------------

+



VinV

P

+

outIDD



Fs1

⋅⋅



V

out

–

out

V⋅
V

-------------------------

+

VinV

–

–⋅⋅⋅=

I

DD

out
out

out

V⋅

out