ST AN1301 APPLICATION NOTE
AN1301
APPLICATION NOTE
STE100P - SINGLE PORT FAST ETHERNET TRANSCEIVER
1.0 GENERAL DESCRIPTION
The STE100P, also referred to as STEPHY1, is a high perf ormance Fast Ethernet phy si cal l ayer i nt erfac e for
10BASE-T and 100BASE-TX applications. It was designed with advanced CMOS technology to provide a Media
Independent Interface (MII) for easy attachment to 10/100 Media Access Controllers (MAC) and a physical media interface for 100BASE-TX and 10BASE-T. The twist ed pair int erface direct ly drives a 10/100 twisted pai r
connection. STE100P is an excellent device perfectly suited for hub, switch, router and other embedded Ethernet applications.
The system diagram is as shown below:
Figure 1. System Diagram of the STE100P Application
Serial
EEPROM
M A C
D ev ic e
PCI Interface
Boot ROM
LEDs
STE100P
STEPHY1
25 MH z
Crystal
RJ-45
Transformer
2.0 FEATURES
n Integrates the whole physical layer functions of the 100BASE-TX and 10BASE-T
n 3.3V low power operation
n The hardware control pins set the initial state of the STE100P at power-up
n Designed with a power down feature, which can save the power consumption significantly
n Can operate for either full duplex or half duplex network applications.
n MI I in terface
n Provides auto-negotiation, parallel detection or manual control for mode setting
n Provides MLT-3 transceiver with DC restoration for Base-line wander compensation
November 2003
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AN1301 APPLICATION NOTE
n Provides transmit wave-shaper, receive filters, and adaptive equalizer
n Provides loop-back modes for diagnostic testing
n Builds in Stream Cipher Scrambler/Descrambler and 4B/5B encoder/decoder
n Supports external transmit transformer with turn ratio 1:1
n Supports external receive transformer with turn ratio 1:1
3.0 DESIGN AND LAYOUT GUIDELINES
3.1 General Guidelines
n Verify that all components meet application requirements.
n Design in filters for the analog power circuits.
n Use bulk capacitors (10-22uF) between the power and ground planes t o minimize switching noise, par-
ticularly near high-speed busses (>25 MHz).
n Use an ample supply of 0.1uF decoupling capacitors to reduce high-frequency noise on the power and
ground planes.
n Use a single analog power and ground plane for multiple devices. Keep ferrite bead currents under 65%
of the rated load
n Avoid breaks in the ground plane, especially in areas where it is shielding high-frequency signals.
n Keep power and ground noise levels below 50mV
n Keep high-speed signals out of the area between STE100P and the magnetics
n Ensure that the power supply is rated for the load and that output ripple is minimal (<50mV)
n Route high-speed signals next to a continuous, unbroken ground plane.
n Provide impedance matching on long traces to prevent reflections.
n Do not route any digital signals between the STE100P and the RJ-45 connectors at the edge of the
board
n It is recommended to fill in unused areas of the signal planes with solid copper and attach them with
vias to a Vcc or ground plane that is not located adjacent to the signal layer.
3.2 Differential Signal Layout Guidel ines
n Route differential pairs close together and away from everything else
n Keep both traces of each differential pair as close to the same length as possible.
n Avoid vias and layer changes
n Keep transmit and receive pairs away from each other. Run orthogonally, or separate with a ground
plane layer.
3.3 Power and Ground
In order to obtain high speed communications design, the power and ground planes may be conceptually divided into three regions (the analog and digital power planes and the signal ground plane)
The analog power region extends from the magnetics back to the STE100P, whereas the digital power region
extends from the MII interfaces of t he STE100P through the rest of the board. Only components and signals
pertaining to the particular interface should be placed or routed through each respective region. The digital section supplies power to the digital Vcce/i pin and to the external components. The analog section supplies power
to Vcca pins of the STE100P.
The signal ground region is one continuous, unbroken plane that extends from the magnetics through the rest
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AN1301 APPLICATION NOTE
of the board. The signal ground pl ane may be combined wit h chass is ground or i solated f r om it. If the ground
planes are combined, an isolation area is not required. When laying out ground planes, special care must be
taken to avoid creating loop antenna effect. Some guidelines are as follows-
n Run all ground plane as solid square or rectangular regions
n Avoid creating loops with ground planes around other planes
3.4 Recommendations
The following recommendations apply to design and layout of the power and ground planes and w ill p reven t the
most common signal and noise issues.
n Divide the Vcc plane into two sections - analog and digital. The break between the planes should run
under the device.
n When dividing the Vcc plane, it is not necessary to add extra layers to the board. Simply crate moats or
cutout regions in existing layers.
n Place a high-frequency bypass cap (0.1uF) near each analog Vcc pin
n Join the digital and analog sections at one or more points by ferric beads. Ensure that the maximum
current rating of the bead is at least 150% of the nominal current that is expected to flow through it.
(250mA per STE100P)
n Place a bulk capacitor (22uF) on each side of each ferrite bead to stop switching noise from travelling
through the ferrite.
For designs with multiple STE100P’s, it is acceptable to supply all from one analog Vcc plane. This plane can
be joined to the digital Vcc plane at multiple points, with a ferrite bead at each one.
4.0 TWISTED PAIR INTERFACE
4.1 Transmit Interface Circuitry
Figure 2 shows a typical transmit interface circuitry. Current is sourced by the AVddt output to the centertap of
the primary side of the winding. Current flows from the centertap to TX+ and TX-. Other components are as follows:
n R1 and R2 are 49.9 ohm resistors that provide impedance matching to the line, which has a nominal
impedance of 100 ohm.
n C1 shunts any common-mode energy present in the output to ground.
n The magnetics consists of the main winding and a common-mode choke.
n The common-mode choke stops common mode energy from reaching the line. It works together with
capacitor C1 to direct common-mode energy away from the line.
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