ST AN1256 APPLICATION NOTE
AN1256
Application note
High-power RF MOSFET targets VHF applications
Introduction
The SD2933, which utilizes a double-diffused metal oxide (DMOS) semiconductor
technology, is the latest addition to STMicroelectronics’ RF Power MOSFET family. The
packaged version is shown in Figure 1. The SD2933 is a single-ended, 50 V, 300 W, gold
(Au) metallized, N-channel, vertical Power MOSFET, intended for use up to 150 MHz, with
exceptionally high gain, and enhanced thermal packaging which makes it ideal for various
applications including plasma generation, excitation and FM broadcast applications. The
unique design of this single-ended 300 W Power MOSFET, makes it the only one of its class
available on the market today.
Figure 1. SD2933 Package
Figure 2. Two Enhancement - mode DMOS mounted in parallel
July 2007 Rev 2 1/7
www.st.com
Device assembly AN1256
1 Device assembly
The SD2933 discrete component design consists of two 40 cell, N-channel, enhancement
mode DMOS transistor dice eutectically mounted in a parallel configuration (see Figure 2).
Each cell consists of 60, 127 µm gate fingers, yielding a source periphery of 1220 mm
allowing a maximum drain current of 40 A. The transistor dice are separated by a metallized
gate rail on which two, thin film, Au metallized resistors are eutectically mounted. For
improved current capability and lower inductance, the components are connected to each
other and to the package by Au wire with a diameter of 2 mils (50 µm). Since the dice and
package utilize gold metallization and the bonding wires are also gold, reliability issues
pertaining to the contact of dissimilar metals between wire, package, and die are eliminated.
The package is sealed with a ceramic lid ensuring the complete integrity of the wires and
silicon die and also preventing any foreign objects from entering the package which could
ultimately cause device reliability problems.
2 Device characteristics
The SD2933 has a very high transconductance. The transconductance (gfs) denotes the
DC gain of a Power MOSFET. It is defined as the ratio of the infinitesimal change in drain
current corresponding to the infinitesimal change in gate voltage at a specified current level
and drain bias. It is important to measure the gfs in the device’s region of operation where
the gfs is independent of the drain bias (VDS). The gfs of the SD2933 measured at a drainsource voltage of 10 V and a corresponding drain current of 10 A, is typically 13 siemens.
Impedance data across a range of frequencies may be the most important information an
amplifier designer needs. Without it, the RF performance may not come close to the
published values found in the datasheet. With properly measured data, and sound
impedance matching techniques, many frustrating hours of circuit design iterations can be
saved.
For this reason, the following impedances were measured to help in the design of amplifiers
for the HF, FM broadcast, and plasma generation markets as shown in Figure 1.
Table 1. Impedance data for the design of amplifiers
Frequency (MHz) ZIN(Ω) ZDL(Ω)
30 1.8 - j0.2 2.8 + j2.3
108 1.9 + j0.2 1.6 + j1.4
175 1.9 + j0.3 1.5 + j1.6
One important item to note is the relatively small change in input impedance from 30 MHz to
150 MHz. This can be attributed to the series gate resistors which present a real impedance
at the input across the full band of frequencies. Matching is easily accomplished by using
transmission line transformers and lumped elements commonly found in many amplifiers.
The SD2933 was characterized in a common source mode at 30 MHz with a circuit
optimized for best return loss and maximum power delivered to the load with a typical gain
and efficiency of 23.5 dB and 65% respectively, as shown in Figure 3. The junction to case
thermal resistance (R
2/7
) was measured under RF operating conditions using infrared
TH-JC
AN1256 Device characteristics
techniques to be 0.27 °C/W allowing for a maximum power dissipation of approximately
650 W (see Figure 4).
Additionally, data was taken at 150 MHz demonstrating the gain and efficiency at the upper
limits of the device characterization (see Figure 5).
Figure 3. Power Gain and efficiency vs. output power
450
400
350
300
250
200
150
Output power (W)
100
50
0
0 0.5 1 1.5 2 2.5 3
Pout Efficiency
Input power (W)
90
80
70
60
50
40
30
Efficiency (%)
20
10
0
Figure 4. Maximum thermal resistance vs. case temperature
Figure 5. Power gain and efficiency vs. output power
27
26
25
24
23
22
Gain (dB)
21
20
19
0 50 100 150 200 250 300 350 400
Gain Efficiency
Output power (W)
80
70
60
50
40
30
Efficiency (%)
20
10
0
3/7
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