This application note gives a description of a broadband power amplifier operating over the
frequency range 88 - 108 MHz using the new STMicroelectronics RF MOSFET transistor
SD2932.
Table 1.Typical achievable performances
ParameterPerformance
Device 1 X SD2932
Frequency 88-108 MHz
Vdd 50 V
Idq 200 mA
Pout 300 W
Gain >19 dB
Input return loss < -11 dB
Drain efficiency >70%
July 2007Rev 3 1/7
www.st.com
Amplifier designAN1229
1 Amplifier design
1.1 Input matching network
Typical input gate-to-gate impedance of SD2932 at 100 MHz is Zin = Rs + jXs = 2 - 2.6 j,
and can also be expressed as the combination of parallel resistance and reactance using
the following formulas:
Equation 1
2
Xs
⎛⎞
⁄4.14jΩ–==
P
-------
+•5.38Ω==
⎝⎠
Rs
X
S
⎛⎞
-------
⎝⎠
R
S
RpRs1
Equation 2
XPR
Therefore, in order to achieve good input matching performances over the frequency range
88-108 MHz the unbalanced 50 Ω is to be transformed into an impedance with a value as
close as possible to Rp of 5.38 Ω.
From the circuit schematic given in Figure 6 , we can see that the input matching network is
based on a two section balun (1:1 balun in cascade with a 9:1 balun transformer) which
transforms the unbalanced 50 Ω to a balanced 5.56 Ω (2 x 2.78 Ω / 9:1 ratio). The first
section, a 5" long - 50 Ω coaxial cable and the second section, a two 3.9" long - 25 Ω flexible
coaxial cables with ferrite core NEOSIDE, are connected as described: a 10 nH inductor
(L1) is connected between the two gates to compensate SD2932 input parallel reactance
Xp.
1.2 Input matching network tuning
Figure 1.Input Impedance of 1:1 balun in cascade with 4:1 balun
-10
-15
-20
S11 (dB)
-25
-30
-35
050100150200250300350
Frequency (MHz)
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AN1229Amplifier design
Figure 2.Input Impedance of 1:1 balun in cascade with 9:1 balun
0
-5
-10
-15
-20
S11 (dB)
-25
-30
-35
050100150200250300350
Frequency (MHz)
SD2932 input matching network was tuned in order to achieve the best compromise in
terms of power gain (Gp) and input return loss (Rtl) over the frequency range 88 - 108 MHz.
Best results were achieved by adding a 10 pF chip capacitor (C1) between RFIN and the
1 nF blocking capacitor (C2).
1.3 Output matching network
The output impedance of each side is a combination of the output capacitance Coss (
195 pF) and the optimum load resistance which can be determined as follows:
Equation 3
0.85 Vd d•()
------------------------------------ -
Rp
2 Pout•
2
0.85 2500•
------------------------------ -
2 150W•
6.02Ω===
The total optimum load, seen by SD2932 (drain to drain), is 2 x 6.02 = 12.04 Ω. Therefore, a
simple two section balun (1:1 balun in cascade with a 4:1 balun transformer) is used to
transform the unbalanced 50 Ω to a balanced 12.5 Ω (2 x 6.25 Ω) which is very near to the
total optimum load resistance.
The first section, a 5" long - 50 Ω flexible coaxial cable, and the second section, two 5" long
- 25 Ω flexible coaxial cables, are connected as described in Figure 6.
To compensate for the output capacitance Coss of SD2932 , a 40 nH inductor (L2) is
connected between the two drains. This LC network (L2 & Coss) is a high pass filter with a
resonance frequency calculated at 10 % below the minimum operating frequency:
Equation 4
C
OSS
C
-------------- -=
OSS
2
(per side)
180p F
-----------------
2
90pF==
Equation 5
Frequency of resonance
0.9 88MHz 80MHz=•=
Equation 6
L2 Coss2 pi F••()••
2
1 L2 44nH=→=
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Amplifier designAN1229
Figure 3.Power gain vs. frequency
22
21
20
19
Power Gain (dB)
18
17
859095100105110
Pout = 300W Vdd = 50V Idq = 200 mA
Frequency (MHz)
Figure 4.Drain efficiency vs. frequency
80
78
76
74
72
70
68
66
Drain Efficiency (%)
64
62
60
859095100105110
Pout = 300W Vdd = 50V Idq = 200 mA
Frequency (MHz)
Figure 5.Drain efficiency vs. frequency
0
-2
-4
-6
-8
-10
-12
-14
-16
Return Loss - Rtl (dB)
-18
-20
859095100105110
4/7
Pout = 300W Vdd = 50V Idq = 200 mA
Frequency (MHz)
AN1229SD2932 typical performances and conclusion
2 SD2932 typical performances and conclusion
Figure 3, Figure 4 and Figure 5 show power gain, efficiency and input return loss over the
frequency range 88 - 108 MHz at a constant output power of 300 W and a drain supply
voltage of 50 V and a quiescent current of 200 mA. Typical performances are as follows:
Table 2.Typical performances
ParametersMinMax
Gp 19.3 dB 19.6 dB
R
-18 dB -11 dB
TL
Eff 71% 73%
Finally, in this report we have demonstrated ST’s SD2932 MOSFET transistor excellent
performance as a wideband 300 W - 50 V push-pull amplifier for FM applications.
Figure 6.88-108 MHz circuit schematic
Table 3.88-108 MHz circuit components list
SymbolDescription
PCB 1/32” Woven fiberglass 0.0030 Cu, 2 side, er
T1 50 Ω Flexible coax cable OD 0.006”, 5” long
T2/ T3 9:1 Transformer, 25 Ω flexible coax cable OD 0.1” 3.9”. ferrite core NEOSIDE
Table 3.88-108 MHz circuit components list (continued)
SymbolDescription
C9 470 pF ATC chip capacitor
C10 100 nF chip capacitor
R1 56 Ω Resistor
R2/R4 10 Ω Chip resistor
R3 10 K Ω Resistor
R5 5.6 K Ω Resistor
R6 10K Ω 10 Turn trim resistor
R7 3.3 K Ω/ 1 W Resistor
R8 15 Ω/ 1 W Resistor
D1 6.8 V Zener diode
L1 10 nH inductor
L2 40 nH inductor
L3 70 nH inductor
3 Revision history
Table 4.Revision history
DateRevisionChanges
21-Jun-20062Minor text changes
30-Jul-20073The document has been reformatted
6/7
AN1229
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