ST AN1228 APPLICATION NOTE

AN1228

Application note

How to relate LMOS device parameters to RF performance

Introduction

This second installment of a two-part paper series on LDMOS technology (see Understanding LDMOS Device Fundamentals, AN1226) will explain LDMOS circuit-level performance through MOS intrinsic device characteristics. Understanding current laterally diffused Metal-Oxide-Semiconductor (LDMOS) technology is necessary to optimally use these devices in high-power RF circuitry. RF circuit designers must come to an understanding of the relationship between circuit performance and device characteristics beyond first-order approximations. These higher-order device relationships can offer insight into many common device parameters and their interdependencies and, more importantly, enable the design engineer to monitor the semiconductor manufacturing process more effectively.

In general, for LDMOS devices and MOS field-effect transistors (MOSFETs) the channel is of primary importance. The channel is the inversion layer created within the body of the device that electrically connects the source and drain, as described in the first part of this series. The channel dimensions and its doping determine the forward transconductance (gfs) and contribute to the body-related capacitances that ultimately influence RF power gain and frequency response. The body-doping profile is critical for device ruggedness and reliability. Since the introduction of LDMOS devices for high-voltage commercial RF applications, device dimensions have evolved from supermicron to submicron in only a few short years.

This progress is indicative of future LDMOS generations and it should be noted that the reduction in device size below one micron has not necessarily followed traditional scaling laws.

Specification sheets for RF MOSFETs include many parameters that will be explained in the context of circuit design and performance criteria. The order in which these device parameters are presented here is not indicative of relative importance.

July 2007

Rev 3

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Breakdown voltage	AN1228

1 Breakdown voltage

The saturated-drain-source breakdown voltage (BVDSS) of a MOSFET device is specified at a particular value of current with the drain biased and the gate, as well as the source, shorted. BVDSS can take many forms as represented in Figure 1 which shows the curve tracer displays for LDMOS breakdown. A BVDSS curve can have a soft breakdown with multiple breaks in the curve which is indicative of non-uniformities in the stress within the inter-digitated cell structure.

Figure 1 shows a BVDSS curve with characteristics that are typical of a device exhibiting punch-through due to an improper body-doping profile. There are four significant areas on this curve - the low, mid, high and breakdown drain-voltage regions which reflect leakage, punch-through, space-charge-limited current and avalanche current respectively. Figure 1 also shows a curve with a very sharp break where the current suddenly increases. There are two significant regions on this curve - pre-breakdown and post-breakdown. Prior to breakdown, leakage current exists that could be from many sources, such as the normal p- type, n-type (pn) junction leakage due to recombination and generation of carriers in the quasi-neutral region of the junction. The breakdown-voltage regime is the avalanching of carriers due to the electric field being greater than the critical electric field (approximately 1x105 V/cm). Under these conditions an electron can be accelerated by the electric field. Due to elastic and inelastic scattering this electron acceleration can generate more than one carrier and thus a multiplication scheme transpires.

Figure 1. Typical breakdown curves of a LDMOS transistor

Operating near BVDSS is a reliability risk since the device sustains high-stress conditions. Under these conditions the high-energy carriers can alter the device characteristics by creating, filling and emptying interface traps. For an LDMOS device, if this avalanche condition exists under or near the gate, the hot carriers can penetrate the gate oxide as well as alter the onand off-state characteristics. Typical problems due to this avalanching include threshold-voltage drift and increased gate leakage. While evaluating devices for this parameter, large variations are indicative of inconsistencies in device fabrication. For RF circuit design a general rule of thumb states that the BVDSS should be 2 to 2.5 times the operating voltage in order to support variations in RF voltage.

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