ST AN1214 Application note

AN1214

APPLICATION NOTE

DESIGN TIPS FOR L6561 POWER FACTOR CORRECTOR

IN WIDE RANGE

by Cliff Ortmeyer & Claudio Adragna

This application note will describe some basic steps to optimize the design of the L6561 PFC for wide range voltage input (105V300V) while also having a broad output power range (65W - 105W). Initial design steps are covered in application note AN966. This is to serve as a supplement to that application note and also give an example of a wide range demo board optimized for the US market (110V - 277V). A deeper look at the control of the L6561 can also be found in application note AN1089 “Control loop modeling of L6561-based TM PFC”.

Introduction

Designing a PFC circuit with a singular input voltage and a singular output power is a task that is rather straight forward and gives a very good set of component values when the design equations are used. The task becomes a little more difficult when a wide range PFC is needed and the specifications are tight. This is common in applications such as lighting where there is a demand for good power factor ( >.99) and THD less than 10% in the full range of nominal operating conditions. The problem occurs since the design must be done for the worst case conditions which are a low input voltage and maximum output power. As we will see, this will diminish the performance of the PFC circuit when the input voltage is high and the output power is low. What must be done in this case is to look closely at the limits of the L6561 and external components and to optimize or compromise where needed.

Design Tips

Multiplier Operation. Once the initial design is done and measurements have been made, the next step is to look at the operating parameters of the L6561 to see that it is working within its full capabilities without going over its linear operating range. A copy of the table we will be referring to is shown in Fig. 1.

Figure 1. Multiplier Characteristics

	VCS(pin4)						D97IN555A			VCOMP(pin2)
	(V)	upper voltage									(V)
	1.6	clamp
										3.5
	1.4				5.0
					5
			4	.
					4.0
	1.2
	1.0									3.2
	0.8
	0.6									3.0
	0.4
	0.2									2.8
	0									2.6
		0.5	1.0		1.5	2.0	2.5	3.0	3.5	4.0	4.5
	0

VMULT(pin3) (V)

For optimal operation the device should stay in the linear operation of the multiplier. As can be seen, there are three pins that should be measured in the worst case conditions. The first is with the lowest input voltage (low line) and the highest output power. The second is at the highest input voltage (high line) and the lowest output power. The first pin to be measured is the Vcomp (pin2). This is the output of the error amplifier (Figure 2) and will determine which curve will be referenced when measuring the other two parameters - Vcs and Vmult. Once this is established, the peak voltage of the multiplier input (pin 3) should be measured and noted. Next measure the peak voltage of the current sense resistor (Vcs - pin 4). Looking at the graph in Figure 1, determine which curve to use from the Vcomp voltage.

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AN1214 APPLICATION NOTE

Next, note where the Vcs and Vmult are on the curve to make sure that they are in the linear operating region. If operation in the linear region is not met, adjust the variable that allows linear operation to be met. If however the device is operating in the linear region but is not allowing the full range of the multiplier to be used, then increasing one of the variables (the multiplier voltage for example) can help to maximize the full operating range of the multiplier.

Figure 2. Multiplier Block Diagram.

		Rs
2	3	4
		-
	X	CURR.CMP
		+

E/A

1.7V

D97IN675

Zero crossing dead time. Once the multiplier operating parameters have been met, the input voltage as well as the input current should be looked at together. One problem to look for is a distortion of the current waveform especially at high line and low load. An example can be seen in figure 3.

Figure 3. Current Shape at Zero Crossing with High Capacitance FET and slow Turn-on Diode.

The main reason for this effect is that near zero-crossings the energy stored in the inductor is very low, not enough to charge up the drain node total capacitance (basically, the FET’s drain-to-source capacitance Coss and the inductor’s parasitic intrawinding capacitance) to turn the boost diode on. The turn-on speed of the boost diode adds to the problem as well. As a result, energy is exchanged between reactive components and there is no input-to-output transfer. This can be seen in figure 3.

To minimize Coss, the Rds(ON) of the FET should be maximized within the limits of acceptable conduction losses, and its voltage rating should be the minimum that still provides adequate breakdown capability. In fact, both

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